target/linux/sunxi/patches-3.14/205-nmi-add-driver.patch

   1 From b9ad0253e6c68ac3d37fd2ed8ed9bf8a334e4b65 Mon Sep 17 00:00:00 2001
   2 From: Carlo Caione <carlo@caione.org>
   3 Date: Sat, 15 Mar 2014 14:40:59 +0100
   4 Subject: [PATCH] ARM: sun7i/sun6i: irqchip: Add irqchip driver for NMI
   5  controller
   6
   7 Allwinner A20/A31 SoCs have special registers to control / (un)mask /
   8 acknowledge NMI. This NMI controller is separated and independent from GIC.
   9 This patch adds a new irqchip to manage NMI.
  10
  11 Signed-off-by: Carlo Caione <carlo@caione.org>
  12 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  drivers/irqchip/Makefile        |   1 +
  15  drivers/irqchip/irq-sunxi-nmi.c | 208 ++++++++++++++++++++++++++++++++++++++++
  16  2 files changed, 209 insertions(+)
  17  create mode 100644 drivers/irqchip/irq-sunxi-nmi.c
  18
  19 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
  20 index 5194afb..1c0c151 100644
  21 --- a/drivers/irqchip/Makefile
  22 +++ b/drivers/irqchip/Makefile
  23 @@ -12,6 +12,7 @@ obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)  += irq-metag.o
  24  obj-$(CONFIG_ARCH_MOXART)              += irq-moxart.o
  25  obj-$(CONFIG_ORION_IRQCHIP)            += irq-orion.o
  26  obj-$(CONFIG_ARCH_SUNXI)               += irq-sun4i.o
  27 +obj-$(CONFIG_ARCH_SUNXI)               += irq-sunxi-nmi.o
  28  obj-$(CONFIG_ARCH_SPEAR3XX)            += spear-shirq.o
  29  obj-$(CONFIG_ARM_GIC)                  += irq-gic.o
  30  obj-$(CONFIG_ARM_NVIC)                 += irq-nvic.o
  31 diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
  32 new file mode 100644
  33 index 0000000..12f547a
  34 --- /dev/null
  35 +++ b/drivers/irqchip/irq-sunxi-nmi.c
  36 @@ -0,0 +1,208 @@
  37 +/*
  38 + * Allwinner A20/A31 SoCs NMI IRQ chip driver.
  39 + *
  40 + * Carlo Caione <carlo.caione@gmail.com>
  41 + *
  42 + * This file is licensed under the terms of the GNU General Public
  43 + * License version 2.  This program is licensed "as is" without any
  44 + * warranty of any kind, whether express or implied.
  45 + */
  46 +
  47 +#include <linux/bitops.h>
  48 +#include <linux/device.h>
  49 +#include <linux/io.h>
  50 +#include <linux/irq.h>
  51 +#include <linux/interrupt.h>
  52 +#include <linux/irqdomain.h>
  53 +#include <linux/of_irq.h>
  54 +#include <linux/of_address.h>
  55 +#include <linux/of_platform.h>
  56 +#include <linux/irqchip/chained_irq.h>
  57 +#include "irqchip.h"
  58 +
  59 +#define SUNXI_NMI_SRC_TYPE_MASK        0x00000003
  60 +
  61 +enum {
  62 +       SUNXI_SRC_TYPE_LEVEL_LOW = 0,
  63 +       SUNXI_SRC_TYPE_EDGE_FALLING,
  64 +       SUNXI_SRC_TYPE_LEVEL_HIGH,
  65 +       SUNXI_SRC_TYPE_EDGE_RISING,
  66 +};
  67 +
  68 +struct sunxi_sc_nmi_reg_offs {
  69 +       u32 ctrl;
  70 +       u32 pend;
  71 +       u32 enable;
  72 +};
  73 +
  74 +static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
  75 +       .ctrl   = 0x00,
  76 +       .pend   = 0x04,
  77 +       .enable = 0x08,
  78 +};
  79 +
  80 +static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
  81 +       .ctrl   = 0x00,
  82 +       .pend   = 0x04,
  83 +       .enable = 0x34,
  84 +};
  85 +
  86 +static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
  87 +                                     u32 val)
  88 +{
  89 +       irq_reg_writel(val, gc->reg_base + off);
  90 +}
  91 +
  92 +static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
  93 +{
  94 +       return irq_reg_readl(gc->reg_base + off);
  95 +}
  96 +
  97 +static void sunxi_sc_nmi_handle_irq(unsigned int irq, struct irq_desc *desc)
  98 +{
  99 +       struct irq_domain *domain = irq_desc_get_handler_data(desc);
 100 +       struct irq_chip *chip = irq_get_chip(irq);
 101 +       unsigned int virq = irq_find_mapping(domain, 0);
 102 +
 103 +       chained_irq_enter(chip, desc);
 104 +       generic_handle_irq(virq);
 105 +       chained_irq_exit(chip, desc);
 106 +}
 107 +
 108 +static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
 109 +{
 110 +       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
 111 +       struct irq_chip_type *ct = gc->chip_types;
 112 +       u32 src_type_reg;
 113 +       u32 ctrl_off = ct->regs.type;
 114 +       unsigned int src_type;
 115 +       unsigned int i;
 116 +
 117 +       irq_gc_lock(gc);
 118 +
 119 +       switch (flow_type & IRQF_TRIGGER_MASK) {
 120 +       case IRQ_TYPE_EDGE_FALLING:
 121 +               src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
 122 +               break;
 123 +       case IRQ_TYPE_EDGE_RISING:
 124 +               src_type = SUNXI_SRC_TYPE_EDGE_RISING;
 125 +               break;
 126 +       case IRQ_TYPE_LEVEL_HIGH:
 127 +               src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
 128 +               break;
 129 +       case IRQ_TYPE_NONE:
 130 +       case IRQ_TYPE_LEVEL_LOW:
 131 +               src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
 132 +               break;
 133 +       default:
 134 +               irq_gc_unlock(gc);
 135 +               pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
 136 +                       __func__, data->irq);
 137 +               return -EBADR;
 138 +       }
 139 +
 140 +       irqd_set_trigger_type(data, flow_type);
 141 +       irq_setup_alt_chip(data, flow_type);
 142 +
 143 +       for (i = 0; i <= gc->num_ct; i++, ct++)
 144 +               if (ct->type & flow_type)
 145 +                       ctrl_off = ct->regs.type;
 146 +
 147 +       src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
 148 +       src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
 149 +       src_type_reg |= src_type;
 150 +       sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
 151 +
 152 +       irq_gc_unlock(gc);
 153 +
 154 +       return IRQ_SET_MASK_OK;
 155 +}
 156 +
 157 +static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 158 +                                       struct sunxi_sc_nmi_reg_offs *reg_offs)
 159 +{
 160 +       struct irq_domain *domain;
 161 +       struct irq_chip_generic *gc;
 162 +       unsigned int irq;
 163 +       unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 164 +       int ret;
 165 +
 166 +
 167 +       domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
 168 +       if (!domain) {
 169 +               pr_err("%s: Could not register interrupt domain.\n", node->name);
 170 +               return -ENOMEM;
 171 +       }
 172 +
 173 +       ret = irq_alloc_domain_generic_chips(domain, 1, 2, node->name,
 174 +                                            handle_fasteoi_irq, clr, 0,
 175 +                                            IRQ_GC_INIT_MASK_CACHE);
 176 +       if (ret) {
 177 +                pr_err("%s: Could not allocate generic interrupt chip.\n",
 178 +                        node->name);
 179 +                goto fail_irqd_remove;
 180 +       }
 181 +
 182 +       irq = irq_of_parse_and_map(node, 0);
 183 +       if (irq <= 0) {
 184 +               pr_err("%s: unable to parse irq\n", node->name);
 185 +               ret = -EINVAL;
 186 +               goto fail_irqd_remove;
 187 +       }
 188 +
 189 +       gc = irq_get_domain_generic_chip(domain, 0);
 190 +       gc->reg_base = of_iomap(node, 0);
 191 +       if (!gc->reg_base) {
 192 +               pr_err("%s: unable to map resource\n", node->name);
 193 +               ret = -ENOMEM;
 194 +               goto fail_irqd_remove;
 195 +       }
 196 +
 197 +       gc->chip_types[0].type                  = IRQ_TYPE_LEVEL_MASK;
 198 +       gc->chip_types[0].chip.irq_mask         = irq_gc_mask_clr_bit;
 199 +       gc->chip_types[0].chip.irq_unmask       = irq_gc_mask_set_bit;
 200 +       gc->chip_types[0].chip.irq_eoi          = irq_gc_ack_set_bit;
 201 +       gc->chip_types[0].chip.irq_set_type     = sunxi_sc_nmi_set_type;
 202 +       gc->chip_types[0].chip.flags            = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
 203 +       gc->chip_types[0].regs.ack              = reg_offs->pend;
 204 +       gc->chip_types[0].regs.mask             = reg_offs->enable;
 205 +       gc->chip_types[0].regs.type             = reg_offs->ctrl;
 206 +
 207 +       gc->chip_types[1].type                  = IRQ_TYPE_EDGE_BOTH;
 208 +       gc->chip_types[1].chip.name             = gc->chip_types[0].chip.name;
 209 +       gc->chip_types[1].chip.irq_ack          = irq_gc_ack_set_bit;
 210 +       gc->chip_types[1].chip.irq_mask         = irq_gc_mask_clr_bit;
 211 +       gc->chip_types[1].chip.irq_unmask       = irq_gc_mask_set_bit;
 212 +       gc->chip_types[1].chip.irq_set_type     = sunxi_sc_nmi_set_type;
 213 +       gc->chip_types[1].regs.ack              = reg_offs->pend;
 214 +       gc->chip_types[1].regs.mask             = reg_offs->enable;
 215 +       gc->chip_types[1].regs.type             = reg_offs->ctrl;
 216 +       gc->chip_types[1].handler               = handle_edge_irq;
 217 +
 218 +       sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
 219 +       sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);
 220 +
 221 +       irq_set_handler_data(irq, domain);
 222 +       irq_set_chained_handler(irq, sunxi_sc_nmi_handle_irq);
 223 +
 224 +       return 0;
 225 +
 226 +fail_irqd_remove:
 227 +       irq_domain_remove(domain);
 228 +
 229 +       return ret;
 230 +}
 231 +
 232 +static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
 233 +                                       struct device_node *parent)
 234 +{
 235 +       return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
 236 +}
 237 +IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
 238 +
 239 +static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
 240 +                                       struct device_node *parent)
 241 +{
 242 +       return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
 243 +}
 244 +IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
 245 --
 246 2.0.3
 247