1 From 49270be12ed66b6aff84292f63c16ed77a62e8a6 Mon Sep 17 00:00:00 2001
2 From: Olliver Schinagl <oliver@schinagl.nl>
3 Date: Sat, 18 Jan 2014 15:00:45 +0100
4 Subject: [PATCH] ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to
7 This patch adds support for the ahci sata controler found on Allwinner A10
8 and A20 SoCs to the ahci_platform driver.
10 Orignally written by Olliver Schinagl using the approach of having a platform
11 device which probe method creates a new child platform device which gets
12 driven by ahci_platform.c, as done by ahci_imx.c .
14 Refactored by Hans de Goede to add most of the non sunxi specific functionality
15 to ahci_platform.c and use a platform_data pointer from of_device_id for the
18 Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
19 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
21 .../devicetree/bindings/ata/ahci-platform.txt | 15 +-
22 drivers/ata/Kconfig | 9 +
23 drivers/ata/Makefile | 1 +
24 drivers/ata/ahci_sunxi.c | 249 +++++++++++++++++++++
25 4 files changed, 271 insertions(+), 3 deletions(-)
26 create mode 100644 drivers/ata/ahci_sunxi.c
28 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
29 +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
30 @@ -4,7 +4,9 @@ SATA nodes are defined to describe on-ch
31 Each SATA controller should have its own node.
34 -- compatible : compatible list, contains "snps,spear-ahci"
35 +- compatible : compatible list, one of "snps,spear-ahci",
36 + "snps,exynos5440-ahci", "ibm,476gtr-ahci", or
37 + "allwinner,sun4i-a10-ahci"
38 - interrupts : <interrupt mapping for SATA IRQ>
39 - reg : <registers mapping>
41 @@ -13,10 +15,17 @@ Optional properties:
42 - clocks : a list of phandle + clock specifier pairs
43 - target-supply : regulator for SATA target power
48 compatible = "snps,spear-ahci";
49 reg = <0xffe08000 0x1000>;
54 + ahci: sata@01c18000 {
55 + compatible = "allwinner,sun4i-a10-ahci";
56 + reg = <0x01c18000 0x1000>;
58 + clocks = <&pll6 0>, <&ahb_gates 25>;
59 + target-supply = <®_ahci_5v>;
61 --- a/drivers/ata/Kconfig
62 +++ b/drivers/ata/Kconfig
63 @@ -106,6 +106,15 @@ config AHCI_IMX
68 + tristate "Allwinner sunxi AHCI SATA support"
69 + depends on ARCH_SUNXI && SATA_AHCI_PLATFORM
71 + This option enables support for the Allwinner sunxi SoC's
77 tristate "Freescale 3.0Gbps SATA support"
79 --- a/drivers/ata/Makefile
80 +++ b/drivers/ata/Makefile
81 @@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
82 obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
83 obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
84 obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
85 +obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o
88 obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
90 +++ b/drivers/ata/ahci_sunxi.c
93 + * Allwinner sunxi AHCI SATA platform driver
94 + * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
95 + * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
97 + * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
98 + * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
99 + * Daniel Wang <danielwang@allwinnertech.com>
101 + * This program is free software; you can redistribute it and/or modify it
102 + * under the terms and conditions of the GNU General Public License,
103 + * version 2, as published by the Free Software Foundation.
105 + * This program is distributed in the hope it will be useful, but WITHOUT
106 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
107 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
111 +#include <linux/ahci_platform.h>
112 +#include <linux/clk.h>
113 +#include <linux/errno.h>
114 +#include <linux/kernel.h>
115 +#include <linux/module.h>
116 +#include <linux/of_device.h>
117 +#include <linux/platform_device.h>
118 +#include <linux/regulator/consumer.h>
121 +#define AHCI_BISTAFR 0x00a0
122 +#define AHCI_BISTCR 0x00a4
123 +#define AHCI_BISTFCTR 0x00a8
124 +#define AHCI_BISTSR 0x00ac
125 +#define AHCI_BISTDECR 0x00b0
126 +#define AHCI_DIAGNR0 0x00b4
127 +#define AHCI_DIAGNR1 0x00b8
128 +#define AHCI_OOBR 0x00bc
129 +#define AHCI_PHYCS0R 0x00c0
130 +#define AHCI_PHYCS1R 0x00c4
131 +#define AHCI_PHYCS2R 0x00c8
132 +#define AHCI_TIMER1MS 0x00e0
133 +#define AHCI_GPARAM1R 0x00e8
134 +#define AHCI_GPARAM2R 0x00ec
135 +#define AHCI_PPARAMR 0x00f0
136 +#define AHCI_TESTR 0x00f4
137 +#define AHCI_VERSIONR 0x00f8
138 +#define AHCI_IDR 0x00fc
139 +#define AHCI_RWCR 0x00fc
140 +#define AHCI_P0DMACR 0x0170
141 +#define AHCI_P0PHYCR 0x0178
142 +#define AHCI_P0PHYSR 0x017c
144 +static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
148 + reg_val = readl(reg);
149 + reg_val &= ~(clr_val);
150 + writel(reg_val, reg);
153 +static void sunxi_setbits(void __iomem *reg, u32 set_val)
157 + reg_val = readl(reg);
158 + reg_val |= set_val;
159 + writel(reg_val, reg);
162 +static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
166 + reg_val = readl(reg);
167 + reg_val &= ~(clr_val);
168 + reg_val |= set_val;
169 + writel(reg_val, reg);
172 +static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
174 + return (readl(reg) >> shift) & mask;
177 +static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
182 + /* This magic is from the original code */
183 + writel(0, reg_base + AHCI_RWCR);
186 + sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
187 + sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
189 + (0x5 << 24) | BIT(23) | BIT(18));
190 + sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
191 + (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
192 + (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
193 + sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
194 + sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
195 + sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
196 + (0x7 << 20), (0x3 << 20));
197 + sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
198 + (0x1f << 5), (0x19 << 5));
201 + sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
203 + timeout = 250; /* Power up takes aprox 50 us */
205 + reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
206 + if (reg_val == 0x02)
209 + if (--timeout == 0) {
210 + dev_err(dev, "PHY power up failed.\n");
216 + sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
218 + timeout = 100; /* Calibration takes aprox 10 us */
220 + reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
221 + if (reg_val == 0x00)
224 + if (--timeout == 0) {
225 + dev_err(dev, "PHY calibration failed.\n");
233 + writel(0x7, reg_base + AHCI_RWCR);
238 +static void ahci_sunxi_start_engine(struct ata_port *ap)
240 + void __iomem *port_mmio = ahci_port_base(ap);
241 + struct ahci_host_priv *hpriv = ap->host->private_data;
243 + /* Setup DMA before DMA start */
244 + sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
247 + sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
250 +static const struct ata_port_info ahci_sunxi_port_info = {
251 + AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
252 + AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
253 + .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
254 + .pio_mask = ATA_PIO4,
255 + .udma_mask = ATA_UDMA6,
256 + .port_ops = &ahci_platform_ops,
259 +static int ahci_sunxi_probe(struct platform_device *pdev)
261 + struct device *dev = &pdev->dev;
262 + struct ahci_host_priv *hpriv;
265 + hpriv = ahci_platform_get_resources(pdev);
267 + return PTR_ERR(hpriv);
269 + hpriv->start_engine = ahci_sunxi_start_engine;
271 + rc = ahci_platform_enable_resources(hpriv);
275 + rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
277 + goto disable_resources;
279 + rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 0, 0);
281 + goto disable_resources;
286 + ahci_platform_disable_resources(hpriv);
290 +#ifdef CONFIG_PM_SLEEP
291 +int ahci_sunxi_resume(struct device *dev)
293 + struct ata_host *host = dev_get_drvdata(dev);
294 + struct ahci_host_priv *hpriv = host->private_data;
297 + rc = ahci_platform_enable_resources(hpriv);
301 + rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
303 + goto disable_resources;
305 + rc = ahci_platform_resume_host(dev);
307 + goto disable_resources;
312 + ahci_platform_disable_resources(hpriv);
317 +static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
318 + ahci_sunxi_resume);
320 +static const struct of_device_id ahci_sunxi_of_match[] = {
321 + { .compatible = "allwinner,sun4i-a10-ahci", },
324 +MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
326 +static struct platform_driver ahci_sunxi_driver = {
327 + .probe = ahci_sunxi_probe,
328 + .remove = ata_platform_remove_one,
330 + .name = "ahci-sunxi",
331 + .owner = THIS_MODULE,
332 + .of_match_table = ahci_sunxi_of_match,
333 + .pm = &ahci_sunxi_pm_ops,
336 +module_platform_driver(ahci_sunxi_driver);
338 +MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
339 +MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
340 +MODULE_LICENSE("GPL");