target/linux/sunxi/patches-3.14/188-clk-sunxi-implement-mmc-phasectrl.patch

   1 From 36268d704307282109ec246f65cac2a42c825629 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
   3 Date: Fri, 20 Sep 2013 20:29:17 -0300
   4 Subject: [PATCH] clk: sunxi: Implement MMC phase control
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 HdG: add header exporting clk_sunxi_mmc_phase_control
  10
  11 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  12 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
  13 ---
  14  drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
  15  include/linux/clk/sunxi.h     | 22 ++++++++++++++++++++++
  16  2 files changed, 57 insertions(+)
  17  create mode 100644 include/linux/clk/sunxi.h
  18
  19 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
  20 index 23baad9..9afd8dd 100644
  21 --- a/drivers/clk/sunxi/clk-sunxi.c
  22 +++ b/drivers/clk/sunxi/clk-sunxi.c
  23 @@ -507,6 +507,41 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
  24
  25
  26  /**
  27 + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
  28 + */
  29 +
  30 +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
  31 +{
  32 +       #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
  33 +       #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
  34 +
  35 +       struct clk_composite *composite = to_clk_composite(hw);
  36 +       struct clk_hw *rate_hw = composite->rate_hw;
  37 +       struct clk_factors *factors = to_clk_factors(rate_hw);
  38 +       unsigned long flags = 0;
  39 +       u32 reg;
  40 +
  41 +       if (factors->lock)
  42 +               spin_lock_irqsave(factors->lock, flags);
  43 +
  44 +       reg = readl(factors->reg);
  45 +
  46 +       /* set sample clock phase control */
  47 +       reg &= ~(0x7 << 20);
  48 +       reg |= ((sample & 0x7) << 20);
  49 +
  50 +       /* set output clock phase control */
  51 +       reg &= ~(0x7 << 8);
  52 +       reg |= ((output & 0x7) << 8);
  53 +
  54 +       writel(reg, factors->reg);
  55 +
  56 +       if (factors->lock)
  57 +               spin_unlock_irqrestore(factors->lock, flags);
  58 +}
  59 +
  60 +
  61 +/**
  62   * sunxi_factors_clk_setup() - Setup function for factor clocks
  63   */
  64
  65 diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
  66 new file mode 100644
  67 index 0000000..1ef5c89
  68 --- /dev/null
  69 +++ b/include/linux/clk/sunxi.h
  70 @@ -0,0 +1,22 @@
  71 +/*
  72 + * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
  73 + *
  74 + * This program is free software; you can redistribute it and/or modify
  75 + * it under the terms of the GNU General Public License as published by
  76 + * the Free Software Foundation; either version 2 of the License, or
  77 + * (at your option) any later version.
  78 + *
  79 + * This program is distributed in the hope that it will be useful,
  80 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  81 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  82 + * GNU General Public License for more details.
  83 + */
  84 +
  85 +#ifndef __LINUX_CLK_SUNXI_H_
  86 +#define __LINUX_CLK_SUNXI_H_
  87 +
  88 +#include <linux/clk.h>
  89 +
  90 +void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
  91 +
  92 +#endif
  93 --
  94 2.0.3
  95