target/linux/sunxi/patches-3.14/186-clk-sunxi-add-new-clock-compats.patch

   1 From 45ff9697ed1668e82ca3902b32309e157464e745 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Thu, 6 Feb 2014 09:55:57 +0100
   4 Subject: [PATCH] clk: sunxi: Add new clock compatibles
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 The Allwinner A10 compatibles were following a slightly different compatible
  10 patterns than the rest of the SoCs for historical reasons. Add compatibles
  11 matching the other pattern to the clock driver for consistency, and keep the
  12 older one for backward compatibility.
  13
  14 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  15 Signed-off-by: Emilio López <emilio@elopez.com.ar>
  16 ---
  17  Documentation/devicetree/bindings/clock/sunxi.txt | 36 +++++++++++------------
  18  drivers/clk/sunxi/clk-sunxi.c                     | 30 +++++++++----------
  19  2 files changed, 33 insertions(+), 33 deletions(-)
  20
  21 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
  22 index 256a908..a5160d8 100644
  23 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
  24 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
  25 @@ -6,37 +6,37 @@ This binding uses the common clock binding[1].
  26
  27  Required properties:
  28  - compatible : shall be one of the following:
  29 -       "allwinner,sun4i-osc-clk" - for a gatable oscillator
  30 -       "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
  31 +       "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
  32 +       "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
  33         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
  34 -       "allwinner,sun4i-pll5-clk" - for the PLL5 clock
  35 -       "allwinner,sun4i-pll6-clk" - for the PLL6 clock
  36 +       "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
  37 +       "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
  38         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
  39 -       "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
  40 -       "allwinner,sun4i-axi-clk" - for the AXI clock
  41 -       "allwinner,sun4i-axi-gates-clk" - for the AXI gates
  42 -       "allwinner,sun4i-ahb-clk" - for the AHB clock
  43 -       "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
  44 +       "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
  45 +       "allwinner,sun4i-a10-axi-clk" - for the AXI clock
  46 +       "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
  47 +       "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
  48 +       "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
  49         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
  50         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
  51         "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
  52         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
  53         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
  54 -       "allwinner,sun4i-apb0-clk" - for the APB0 clock
  55 -       "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
  56 +       "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
  57 +       "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
  58         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
  59         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
  60         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
  61 -       "allwinner,sun4i-apb1-clk" - for the APB1 clock
  62 -       "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
  63 -       "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
  64 +       "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
  65 +       "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
  66 +       "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
  67         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
  68         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
  69         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
  70         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
  71         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
  72         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
  73 -       "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
  74 +       "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
  75         "allwinner,sun7i-a20-out-clk" - for the external output clocks
  76         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
  77         "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
  78 @@ -69,7 +69,7 @@ For example:
  79
  80  osc24M: clk@01c20050 {
  81         #clock-cells = <0>;
  82 -       compatible = "allwinner,sun4i-osc-clk";
  83 +       compatible = "allwinner,sun4i-a10-osc-clk";
  84         reg = <0x01c20050 0x4>;
  85         clocks = <&osc24M_fixed>;
  86         clock-output-names = "osc24M";
  87 @@ -77,7 +77,7 @@ osc24M: clk@01c20050 {
  88
  89  pll1: clk@01c20000 {
  90         #clock-cells = <0>;
  91 -       compatible = "allwinner,sun4i-pll1-clk";
  92 +       compatible = "allwinner,sun4i-a10-pll1-clk";
  93         reg = <0x01c20000 0x4>;
  94         clocks = <&osc24M>;
  95         clock-output-names = "pll1";
  96 @@ -93,7 +93,7 @@ pll5: clk@01c20020 {
  97
  98  cpu: cpu@01c20054 {
  99         #clock-cells = <0>;
 100 -       compatible = "allwinner,sun4i-cpu-clk";
 101 +       compatible = "allwinner,sun4i-a10-cpu-clk";
 102         reg = <0x01c20054 0x4>;
 103         clocks = <&osc32k>, <&osc24M>, <&pll1>;
 104         clock-output-names = "cpu";
 105 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
 106 index 335c987..23baad9 100644
 107 --- a/drivers/clk/sunxi/clk-sunxi.c
 108 +++ b/drivers/clk/sunxi/clk-sunxi.c
 109 @@ -80,7 +80,7 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
 110  err_free_fixed:
 111         kfree(fixed);
 112  }
 113 -CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup);
 114 +CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
 115
 116
 117
 118 @@ -1207,52 +1207,52 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
 119
 120  /* Matches for factors clocks */
 121  static const struct of_device_id clk_factors_match[] __initconst = {
 122 -       {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
 123 +       {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
 124         {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
 125         {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
 126 -       {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
 127 -       {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
 128 +       {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
 129 +       {.compatible = "allwinner,sun4i-a10-mod0-clk", .data = &sun4i_mod0_data,},
 130         {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
 131         {}
 132  };
 133
 134  /* Matches for divider clocks */
 135  static const struct of_device_id clk_div_match[] __initconst = {
 136 -       {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,},
 137 -       {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,},
 138 -       {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,},
 139 +       {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
 140 +       {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
 141 +       {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
 142         {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
 143         {}
 144  };
 145
 146  /* Matches for divided outputs */
 147  static const struct of_device_id clk_divs_match[] __initconst = {
 148 -       {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
 149 -       {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
 150 +       {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
 151 +       {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
 152         {}
 153  };
 154
 155  /* Matches for mux clocks */
 156  static const struct of_device_id clk_mux_match[] __initconst = {
 157 -       {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
 158 -       {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
 159 +       {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
 160 +       {.compatible = "allwinner,sun4i-a10-apb1-mux-clk", .data = &sun4i_apb1_mux_data,},
 161         {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
 162         {}
 163  };
 164
 165  /* Matches for gate clocks */
 166  static const struct of_device_id clk_gates_match[] __initconst = {
 167 -       {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
 168 -       {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
 169 +       {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
 170 +       {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
 171         {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
 172         {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
 173         {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
 174         {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
 175 -       {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 176 +       {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
 177         {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
 178         {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
 179         {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
 180 -       {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
 181 +       {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
 182         {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
 183         {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
 184         {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
 185 --
 186 2.0.3
 187