1 From c225f78660cd61914f25dd00499c7ae71d1d6919 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Wed, 5 Feb 2014 14:05:03 +0100
4 Subject: [PATCH] clk: sunxi: Add support for PLL6 on the A31
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 The A31 has a slightly different PLL6 clock. Add support for this new clock in
12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
15 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
16 drivers/clk/sunxi/clk-sunxi.c | 45 +++++++++++++++++++++++
17 2 files changed, 46 insertions(+)
19 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
20 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
21 @@ -11,6 +11,7 @@ Required properties:
22 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
23 "allwinner,sun4i-pll5-clk" - for the PLL5 clock
24 "allwinner,sun4i-pll6-clk" - for the PLL6 clock
25 + "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
26 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
27 "allwinner,sun4i-axi-clk" - for the AXI clock
28 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
29 --- a/drivers/clk/sunxi/clk-sunxi.c
30 +++ b/drivers/clk/sunxi/clk-sunxi.c
31 @@ -252,7 +252,38 @@ static void sun4i_get_pll5_factors(u32 *
32 *n = DIV_ROUND_UP(div, (*k+1));
36 + * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
37 + * PLL6 rate is calculated as follows
38 + * rate = parent_rate * n * (k + 1) / 2
39 + * parent_rate is always 24Mhz
42 +static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
43 + u8 *n, u8 *k, u8 *m, u8 *p)
48 + * We always have 24MHz / 2, so we can just say that our
49 + * parent clock is 12MHz.
51 + parent_rate = parent_rate / 2;
53 + /* Normalize value to a parent_rate multiple (24M / 2) */
54 + div = *freq / parent_rate;
55 + *freq = parent_rate * div;
57 + /* we were called to round the frequency, we can now return */
65 + *n = DIV_ROUND_UP(div, (*k+1));
69 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
70 @@ -420,6 +451,13 @@ static struct clk_factors_config sun4i_p
74 +static struct clk_factors_config sun6i_a31_pll6_config = {
81 static struct clk_factors_config sun4i_apb1_config = {
84 @@ -469,6 +507,12 @@ static const struct factors_data sun4i_p
88 +static const struct factors_data sun6i_a31_pll6_data __initconst = {
90 + .table = &sun6i_a31_pll6_config,
91 + .getter = sun6i_a31_get_pll6_factors,
94 static const struct factors_data sun4i_apb1_data __initconst = {
95 .table = &sun4i_apb1_config,
96 .getter = sun4i_get_apb1_factors,
97 @@ -1069,6 +1113,7 @@ free_clkdata:
98 static const struct of_device_id clk_factors_match[] __initconst = {
99 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
100 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
101 + {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
102 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
103 {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
104 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},