1 From 0bf618fda3ad24649add0bf943d16a9b4f5c3463 Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Mon, 3 Feb 2014 09:51:37 +0800
4 Subject: [PATCH] clk: sunxi: add clock-output-names dt property support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 sunxi clock drivers use dt node name as clock name, but clock
10 nodes should be named clk@X, so the names would be the same.
11 Let the drivers read clock names from dt clock-output-names
14 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
15 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
16 Acked-by: Mike Turquette <mturquette@linaro.org>
17 Signed-off-by: Emilio López <emilio@elopez.com.ar>
19 drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
20 1 file changed, 6 insertions(+)
22 --- a/drivers/clk/sunxi/clk-sunxi.c
23 +++ b/drivers/clk/sunxi/clk-sunxi.c
24 @@ -51,6 +51,8 @@ static void __init sun4i_osc_clk_setup(s
28 + of_property_read_string(node, "clock-output-names", &clk_name);
30 /* set up gate and fixed rate properties */
31 gate->reg = of_iomap(node, 0);
32 gate->bit_idx = SUNXI_OSC24M_GATE;
33 @@ -601,6 +603,8 @@ static void __init sunxi_mux_clk_setup(s
34 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
37 + of_property_read_string(node, "clock-output-names", &clk_name);
39 clk = clk_register_mux(NULL, clk_name, parents, i,
40 CLK_SET_RATE_NO_REPARENT, reg,
41 data->shift, SUNXI_MUX_GATE_WIDTH,
42 @@ -660,6 +664,8 @@ static void __init sunxi_divider_clk_set
44 clk_parent = of_clk_get_parent_name(node, 0);
46 + of_property_read_string(node, "clock-output-names", &clk_name);
48 clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
49 reg, data->shift, data->width,
50 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,