target/linux/sunxi/patches-3.14/146-1-spi-add-a31-spi.patch

   1 From 86cb7c7ab176112f8b0031dc7c8d19103ba52277 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Wed, 5 Feb 2014 14:05:05 +0100
   4 Subject: [PATCH] spi: sunxi: Add Allwinner A31 SPI controller driver
   5
   6 The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
   7 SoCs.
   8
   9 It supports DMA, but the driver only does PIO for now, and DMA will be
  10 supported eventually.
  11
  12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  13 ---
  14  .../devicetree/bindings/spi/spi-sun6i.txt          |  24 +
  15  drivers/spi/Kconfig                                |   6 +
  16  drivers/spi/Makefile                               |   1 +
  17  drivers/spi/spi-sun6i.c                            | 483 +++++++++++++++++++++
  18  4 files changed, 514 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt
  20  create mode 100644 drivers/spi/spi-sun6i.c
  21
  22 --- /dev/null
  23 +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
  24 @@ -0,0 +1,24 @@
  25 +Allwinner A31 SPI controller
  26 +
  27 +Required properties:
  28 +- compatible: Should be "allwinner,sun6i-a31-spi".
  29 +- reg: Should contain register location and length.
  30 +- interrupts: Should contain interrupt.
  31 +- clocks: phandle to the clocks feeding the SPI controller. Two are
  32 +          needed:
  33 +  - "ahb": the gated AHB parent clock
  34 +  - "mod": the parent module clock
  35 +- clock-names: Must contain the clock names described just above
  36 +- resets: phandle to the reset controller asserting this device in
  37 +          reset
  38 +
  39 +Example:
  40 +
  41 +spi1: spi@01c69000 {
  42 +       compatible = "allwinner,sun6i-a31-spi";
  43 +       reg = <0x01c69000 0x1000>;
  44 +       interrupts = <0 66 4>;
  45 +       clocks = <&ahb1_gates 21>, <&spi1_clk>;
  46 +       clock-names = "ahb", "mod";
  47 +       resets = <&ahb1_rst 21>;
  48 +};
  49 --- a/drivers/spi/Kconfig
  50 +++ b/drivers/spi/Kconfig
  51 @@ -455,6 +455,12 @@ config SPI_SIRF
  52         help
  53           SPI driver for CSR SiRFprimaII SoCs
  54
  55 +config SPI_SUN6I
  56 +       tristate "Allwinner A31 SPI controller"
  57 +       depends on ARCH_SUNXI || COMPILE_TEST
  58 +       help
  59 +         This enables using the SPI controller on the Allwinner A31 SoCs.
  60 +
  61  config SPI_MXS
  62         tristate "Freescale MXS SPI controller"
  63         depends on ARCH_MXS
  64 --- a/drivers/spi/Makefile
  65 +++ b/drivers/spi/Makefile
  66 @@ -71,6 +71,7 @@ obj-$(CONFIG_SPI_SH_HSPI)             += spi-sh-hsp
  67  obj-$(CONFIG_SPI_SH_MSIOF)             += spi-sh-msiof.o
  68  obj-$(CONFIG_SPI_SH_SCI)               += spi-sh-sci.o
  69  obj-$(CONFIG_SPI_SIRF)         += spi-sirf.o
  70 +obj-$(CONFIG_SPI_SUN6I)                        += spi-sun6i.o
  71  obj-$(CONFIG_SPI_TEGRA114)             += spi-tegra114.o
  72  obj-$(CONFIG_SPI_TEGRA20_SFLASH)       += spi-tegra20-sflash.o
  73  obj-$(CONFIG_SPI_TEGRA20_SLINK)                += spi-tegra20-slink.o
  74 --- /dev/null
  75 +++ b/drivers/spi/spi-sun6i.c
  76 @@ -0,0 +1,483 @@
  77 +/*
  78 + * Copyright (C) 2012 - 2014 Allwinner Tech
  79 + * Pan Nan <pannan@allwinnertech.com>
  80 + *
  81 + * Copyright (C) 2014 Maxime Ripard
  82 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  83 + *
  84 + * This program is free software; you can redistribute it and/or
  85 + * modify it under the terms of the GNU General Public License as
  86 + * published by the Free Software Foundation; either version 2 of
  87 + * the License, or (at your option) any later version.
  88 + */
  89 +
  90 +#include <linux/clk.h>
  91 +#include <linux/delay.h>
  92 +#include <linux/device.h>
  93 +#include <linux/interrupt.h>
  94 +#include <linux/io.h>
  95 +#include <linux/module.h>
  96 +#include <linux/platform_device.h>
  97 +#include <linux/pm_runtime.h>
  98 +#include <linux/reset.h>
  99 +#include <linux/workqueue.h>
 100 +
 101 +#include <linux/spi/spi.h>
 102 +
 103 +#define SUN6I_FIFO_DEPTH               128
 104 +
 105 +#define SUN6I_GBL_CTL_REG              0x04
 106 +#define SUN6I_GBL_CTL_BUS_ENABLE               BIT(0)
 107 +#define SUN6I_GBL_CTL_MASTER                   BIT(1)
 108 +#define SUN6I_GBL_CTL_TP                       BIT(7)
 109 +#define SUN6I_GBL_CTL_RST                      BIT(31)
 110 +
 111 +#define SUN6I_TFR_CTL_REG              0x08
 112 +#define SUN6I_TFR_CTL_CPHA                     BIT(0)
 113 +#define SUN6I_TFR_CTL_CPOL                     BIT(1)
 114 +#define SUN6I_TFR_CTL_SPOL                     BIT(2)
 115 +#define SUN6I_TFR_CTL_CS_MASK                  0x3
 116 +#define SUN6I_TFR_CTL_CS(cs)                   (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4)
 117 +#define SUN6I_TFR_CTL_CS_MANUAL                        BIT(6)
 118 +#define SUN6I_TFR_CTL_CS_LEVEL                 BIT(7)
 119 +#define SUN6I_TFR_CTL_DHB                      BIT(8)
 120 +#define SUN6I_TFR_CTL_FBS                      BIT(12)
 121 +#define SUN6I_TFR_CTL_XCH                      BIT(31)
 122 +
 123 +#define SUN6I_INT_CTL_REG              0x10
 124 +#define SUN6I_INT_CTL_RF_OVF                   BIT(8)
 125 +#define SUN6I_INT_CTL_TC                       BIT(12)
 126 +
 127 +#define SUN6I_INT_STA_REG              0x14
 128 +
 129 +#define SUN6I_FIFO_CTL_REG             0x18
 130 +#define SUN6I_FIFO_CTL_RF_RST                  BIT(15)
 131 +#define SUN6I_FIFO_CTL_TF_RST                  BIT(31)
 132 +
 133 +#define SUN6I_FIFO_STA_REG             0x1c
 134 +#define SUN6I_FIFO_STA_RF_CNT_MASK             0x7f
 135 +#define SUN6I_FIFO_STA_RF_CNT_BITS             0
 136 +#define SUN6I_FIFO_STA_TF_CNT_MASK             0x7f
 137 +#define SUN6I_FIFO_STA_TF_CNT_BITS             16
 138 +
 139 +#define SUN6I_CLK_CTL_REG              0x24
 140 +#define SUN6I_CLK_CTL_CDR2_MASK                        0xff
 141 +#define SUN6I_CLK_CTL_CDR2(div)                        (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
 142 +#define SUN6I_CLK_CTL_CDR1_MASK                        0xf
 143 +#define SUN6I_CLK_CTL_CDR1(div)                        (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
 144 +#define SUN6I_CLK_CTL_DRS                      BIT(12)
 145 +
 146 +#define SUN6I_BURST_CNT_REG            0x30
 147 +#define SUN6I_BURST_CNT(cnt)                   ((cnt) & 0xffffff)
 148 +
 149 +#define SUN6I_XMIT_CNT_REG             0x34
 150 +#define SUN6I_XMIT_CNT(cnt)                    ((cnt) & 0xffffff)
 151 +
 152 +#define SUN6I_BURST_CTL_CNT_REG                0x38
 153 +#define SUN6I_BURST_CTL_CNT_STC(cnt)           ((cnt) & 0xffffff)
 154 +
 155 +#define SUN6I_TXDATA_REG               0x200
 156 +#define SUN6I_RXDATA_REG               0x300
 157 +
 158 +struct sun6i_spi {
 159 +       struct spi_master       *master;
 160 +       void __iomem            *base_addr;
 161 +       struct clk              *hclk;
 162 +       struct clk              *mclk;
 163 +       struct reset_control    *rstc;
 164 +
 165 +       struct completion       done;
 166 +
 167 +       const u8                *tx_buf;
 168 +       u8                      *rx_buf;
 169 +       int                     len;
 170 +};
 171 +
 172 +static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
 173 +{
 174 +       return readl(sspi->base_addr + reg);
 175 +}
 176 +
 177 +static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
 178 +{
 179 +       writel(value, sspi->base_addr + reg);
 180 +}
 181 +
 182 +static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
 183 +{
 184 +       u32 reg, cnt;
 185 +       u8 byte;
 186 +
 187 +       /* See how much data is available */
 188 +       reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
 189 +       reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
 190 +       cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
 191 +
 192 +       if (len > cnt)
 193 +               len = cnt;
 194 +
 195 +       while (len--) {
 196 +               byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
 197 +               if (sspi->rx_buf)
 198 +                       *sspi->rx_buf++ = byte;
 199 +       }
 200 +}
 201 +
 202 +static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
 203 +{
 204 +       u8 byte;
 205 +
 206 +       if (len > sspi->len)
 207 +               len = sspi->len;
 208 +
 209 +       while (len--) {
 210 +               byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
 211 +               writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
 212 +               sspi->len--;
 213 +       }
 214 +}
 215 +
 216 +static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
 217 +{
 218 +       struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
 219 +       u32 reg;
 220 +
 221 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 222 +       reg &= ~SUN6I_TFR_CTL_CS_MASK;
 223 +       reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
 224 +
 225 +       if (enable)
 226 +               reg |= SUN6I_TFR_CTL_CS_LEVEL;
 227 +       else
 228 +               reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
 229 +
 230 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 231 +}
 232 +
 233 +
 234 +static int sun6i_spi_transfer_one(struct spi_master *master,
 235 +                                 struct spi_device *spi,
 236 +                                 struct spi_transfer *tfr)
 237 +{
 238 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 239 +       unsigned int mclk_rate, div, timeout;
 240 +       unsigned int tx_len = 0;
 241 +       int ret = 0;
 242 +       u32 reg;
 243 +
 244 +       /* We don't support transfer larger than the FIFO */
 245 +       if (tfr->len > SUN6I_FIFO_DEPTH)
 246 +               return -EINVAL;
 247 +
 248 +       reinit_completion(&sspi->done);
 249 +       sspi->tx_buf = tfr->tx_buf;
 250 +       sspi->rx_buf = tfr->rx_buf;
 251 +       sspi->len = tfr->len;
 252 +
 253 +       /* Clear pending interrupts */
 254 +       sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
 255 +
 256 +       /* Reset FIFO */
 257 +       sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
 258 +                       SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
 259 +
 260 +       /*
 261 +        * Setup the transfer control register: Chip Select,
 262 +        * polarities, etc.
 263 +        */
 264 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 265 +
 266 +       if (spi->mode & SPI_CPOL)
 267 +               reg |= SUN6I_TFR_CTL_CPOL;
 268 +       else
 269 +               reg &= ~SUN6I_TFR_CTL_CPOL;
 270 +
 271 +       if (spi->mode & SPI_CPHA)
 272 +               reg |= SUN6I_TFR_CTL_CPHA;
 273 +       else
 274 +               reg &= ~SUN6I_TFR_CTL_CPHA;
 275 +
 276 +       if (spi->mode & SPI_LSB_FIRST)
 277 +               reg |= SUN6I_TFR_CTL_FBS;
 278 +       else
 279 +               reg &= ~SUN6I_TFR_CTL_FBS;
 280 +
 281 +       /*
 282 +        * If it's a TX only transfer, we don't want to fill the RX
 283 +        * FIFO with bogus data
 284 +        */
 285 +       if (sspi->rx_buf)
 286 +               reg &= ~SUN6I_TFR_CTL_DHB;
 287 +       else
 288 +               reg |= SUN6I_TFR_CTL_DHB;
 289 +
 290 +       /* We want to control the chip select manually */
 291 +       reg |= SUN6I_TFR_CTL_CS_MANUAL;
 292 +
 293 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
 294 +
 295 +       /* Ensure that we have a parent clock fast enough */
 296 +       mclk_rate = clk_get_rate(sspi->mclk);
 297 +       if (mclk_rate < (2 * spi->max_speed_hz)) {
 298 +               clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
 299 +               mclk_rate = clk_get_rate(sspi->mclk);
 300 +       }
 301 +
 302 +       /*
 303 +        * Setup clock divider.
 304 +        *
 305 +        * We have two choices there. Either we can use the clock
 306 +        * divide rate 1, which is calculated thanks to this formula:
 307 +        * SPI_CLK = MOD_CLK / (2 ^ cdr)
 308 +        * Or we can use CDR2, which is calculated with the formula:
 309 +        * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
 310 +        * Wether we use the former or the latter is set through the
 311 +        * DRS bit.
 312 +        *
 313 +        * First try CDR2, and if we can't reach the expected
 314 +        * frequency, fall back to CDR1.
 315 +        */
 316 +       div = mclk_rate / (2 * spi->max_speed_hz);
 317 +       if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
 318 +               if (div > 0)
 319 +                       div--;
 320 +
 321 +               reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
 322 +       } else {
 323 +               div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
 324 +               reg = SUN6I_CLK_CTL_CDR1(div);
 325 +       }
 326 +
 327 +       sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
 328 +
 329 +       /* Setup the transfer now... */
 330 +       if (sspi->tx_buf)
 331 +               tx_len = tfr->len;
 332 +
 333 +       /* Setup the counters */
 334 +       sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
 335 +       sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
 336 +       sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
 337 +                       SUN6I_BURST_CTL_CNT_STC(tx_len));
 338 +
 339 +       /* Fill the TX FIFO */
 340 +       sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
 341 +
 342 +       /* Enable the interrupts */
 343 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
 344 +
 345 +       /* Start the transfer */
 346 +       reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
 347 +       sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
 348 +
 349 +       timeout = wait_for_completion_timeout(&sspi->done,
 350 +                                             msecs_to_jiffies(1000));
 351 +       if (!timeout) {
 352 +               ret = -ETIMEDOUT;
 353 +               goto out;
 354 +       }
 355 +
 356 +       sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
 357 +
 358 +out:
 359 +       sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
 360 +
 361 +       return ret;
 362 +}
 363 +
 364 +static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
 365 +{
 366 +       struct sun6i_spi *sspi = dev_id;
 367 +       u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
 368 +
 369 +       /* Transfer complete */
 370 +       if (status & SUN6I_INT_CTL_TC) {
 371 +               sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
 372 +               complete(&sspi->done);
 373 +               return IRQ_HANDLED;
 374 +       }
 375 +
 376 +       return IRQ_NONE;
 377 +}
 378 +
 379 +static int sun6i_spi_runtime_resume(struct device *dev)
 380 +{
 381 +       struct spi_master *master = dev_get_drvdata(dev);
 382 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 383 +       int ret;
 384 +
 385 +       ret = clk_prepare_enable(sspi->hclk);
 386 +       if (ret) {
 387 +               dev_err(dev, "Couldn't enable AHB clock\n");
 388 +               goto out;
 389 +       }
 390 +
 391 +       ret = clk_prepare_enable(sspi->mclk);
 392 +       if (ret) {
 393 +               dev_err(dev, "Couldn't enable module clock\n");
 394 +               goto err;
 395 +       }
 396 +
 397 +       ret = reset_control_deassert(sspi->rstc);
 398 +       if (ret) {
 399 +               dev_err(dev, "Couldn't deassert the device from reset\n");
 400 +               goto err2;
 401 +       }
 402 +
 403 +       sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 404 +                       SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
 405 +
 406 +       return 0;
 407 +
 408 +err2:
 409 +       clk_disable_unprepare(sspi->mclk);
 410 +err:
 411 +       clk_disable_unprepare(sspi->hclk);
 412 +out:
 413 +       return ret;
 414 +}
 415 +
 416 +static int sun6i_spi_runtime_suspend(struct device *dev)
 417 +{
 418 +       struct spi_master *master = dev_get_drvdata(dev);
 419 +       struct sun6i_spi *sspi = spi_master_get_devdata(master);
 420 +
 421 +       reset_control_assert(sspi->rstc);
 422 +       clk_disable_unprepare(sspi->mclk);
 423 +       clk_disable_unprepare(sspi->hclk);
 424 +
 425 +       return 0;
 426 +}
 427 +
 428 +static int sun6i_spi_probe(struct platform_device *pdev)
 429 +{
 430 +       struct spi_master *master;
 431 +       struct sun6i_spi *sspi;
 432 +       struct resource *res;
 433 +       int ret = 0, irq;
 434 +
 435 +       master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
 436 +       if (!master) {
 437 +               dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
 438 +               return -ENOMEM;
 439 +       }
 440 +
 441 +       platform_set_drvdata(pdev, master);
 442 +       sspi = spi_master_get_devdata(master);
 443 +
 444 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 445 +       sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
 446 +       if (IS_ERR(sspi->base_addr)) {
 447 +               ret = PTR_ERR(sspi->base_addr);
 448 +               goto err_free_master;
 449 +       }
 450 +
 451 +       irq = platform_get_irq(pdev, 0);
 452 +       if (irq < 0) {
 453 +               dev_err(&pdev->dev, "No spi IRQ specified\n");
 454 +               ret = -ENXIO;
 455 +               goto err_free_master;
 456 +       }
 457 +
 458 +       ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
 459 +                              0, "sun6i-spi", sspi);
 460 +       if (ret) {
 461 +               dev_err(&pdev->dev, "Cannot request IRQ\n");
 462 +               goto err_free_master;
 463 +       }
 464 +
 465 +       sspi->master = master;
 466 +       master->set_cs = sun6i_spi_set_cs;
 467 +       master->transfer_one = sun6i_spi_transfer_one;
 468 +       master->num_chipselect = 4;
 469 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 470 +       master->dev.of_node = pdev->dev.of_node;
 471 +       master->auto_runtime_pm = true;
 472 +
 473 +       sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
 474 +       if (IS_ERR(sspi->hclk)) {
 475 +               dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
 476 +               ret = PTR_ERR(sspi->hclk);
 477 +               goto err_free_master;
 478 +       }
 479 +
 480 +       sspi->mclk = devm_clk_get(&pdev->dev, "mod");
 481 +       if (IS_ERR(sspi->mclk)) {
 482 +               dev_err(&pdev->dev, "Unable to acquire module clock\n");
 483 +               ret = PTR_ERR(sspi->mclk);
 484 +               goto err_free_master;
 485 +       }
 486 +
 487 +       init_completion(&sspi->done);
 488 +
 489 +       sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
 490 +       if (IS_ERR(sspi->rstc)) {
 491 +               dev_err(&pdev->dev, "Couldn't get reset controller\n");
 492 +               ret = PTR_ERR(sspi->rstc);
 493 +               goto err_free_master;
 494 +       }
 495 +
 496 +       /*
 497 +        * This wake-up/shutdown pattern is to be able to have the
 498 +        * device woken up, even if runtime_pm is disabled
 499 +        */
 500 +       ret = sun6i_spi_runtime_resume(&pdev->dev);
 501 +       if (ret) {
 502 +               dev_err(&pdev->dev, "Couldn't resume the device\n");
 503 +               goto err_free_master;
 504 +       }
 505 +
 506 +       pm_runtime_set_active(&pdev->dev);
 507 +       pm_runtime_enable(&pdev->dev);
 508 +       pm_runtime_idle(&pdev->dev);
 509 +
 510 +       ret = devm_spi_register_master(&pdev->dev, master);
 511 +       if (ret) {
 512 +               dev_err(&pdev->dev, "cannot register SPI master\n");
 513 +               goto err_pm_disable;
 514 +       }
 515 +
 516 +       return 0;
 517 +
 518 +err_pm_disable:
 519 +       pm_runtime_disable(&pdev->dev);
 520 +       sun6i_spi_runtime_suspend(&pdev->dev);
 521 +err_free_master:
 522 +       spi_master_put(master);
 523 +       return ret;
 524 +}
 525 +
 526 +static int sun6i_spi_remove(struct platform_device *pdev)
 527 +{
 528 +       pm_runtime_disable(&pdev->dev);
 529 +
 530 +       return 0;
 531 +}
 532 +
 533 +static const struct of_device_id sun6i_spi_match[] = {
 534 +       { .compatible = "allwinner,sun6i-a31-spi", },
 535 +       {}
 536 +};
 537 +MODULE_DEVICE_TABLE(of, sun6i_spi_match);
 538 +
 539 +static const struct dev_pm_ops sun6i_spi_pm_ops = {
 540 +       .runtime_resume         = sun6i_spi_runtime_resume,
 541 +       .runtime_suspend        = sun6i_spi_runtime_suspend,
 542 +};
 543 +
 544 +static struct platform_driver sun6i_spi_driver = {
 545 +       .probe  = sun6i_spi_probe,
 546 +       .remove = sun6i_spi_remove,
 547 +       .driver = {
 548 +               .name           = "sun6i-spi",
 549 +               .owner          = THIS_MODULE,
 550 +               .of_match_table = sun6i_spi_match,
 551 +               .pm             = &sun6i_spi_pm_ops,
 552 +       },
 553 +};
 554 +module_platform_driver(sun6i_spi_driver);
 555 +
 556 +MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
 557 +MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 558 +MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
 559 +MODULE_LICENSE("GPL");