1 From 8bd1bb3a670aae791c4b2e9ab13c92768233368a Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Mon, 3 Feb 2014 09:51:43 +0800
4 Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
6 Device tree naming conventions state that node names should match
7 node function. Change fully functioning clock nodes to match and
8 add clock-output-names to all sunxi clock nodes.
10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
14 1 file changed, 14 insertions(+), 5 deletions(-)
16 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
17 index fc07f70..d3f1995 100644
18 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
19 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
21 clock-frequency = <24000000>;
27 compatible = "fixed-clock";
28 clock-frequency = <32768>;
29 + clock-output-names = "osc32k";
32 - pll1: pll1@01c20000 {
33 + pll1: clk@01c20000 {
35 compatible = "allwinner,sun6i-a31-pll1-clk";
36 reg = <0x01c20000 0x4>;
38 + clock-output-names = "pll1";
45 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
46 + clock-output-names = "cpu";
51 compatible = "allwinner,sun4i-axi-clk";
52 reg = <0x01c20050 0x4>;
54 + clock-output-names = "axi";
57 ahb1_mux: ahb1_mux@01c20054 {
59 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
60 reg = <0x01c20054 0x4>;
61 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
62 + clock-output-names = "ahb1_mux";
67 compatible = "allwinner,sun4i-ahb-clk";
68 reg = <0x01c20054 0x4>;
70 + clock-output-names = "ahb1";
73 - ahb1_gates: ahb1_gates@01c20060 {
74 + ahb1_gates: clk@01c20060 {
76 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
77 reg = <0x01c20060 0x8>;
79 compatible = "allwinner,sun4i-apb0-clk";
80 reg = <0x01c20054 0x4>;
82 + clock-output-names = "apb1";
85 - apb1_gates: apb1_gates@01c20060 {
86 + apb1_gates: clk@01c20068 {
88 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
89 reg = <0x01c20068 0x4>;
91 compatible = "allwinner,sun4i-apb1-mux-clk";
92 reg = <0x01c20058 0x4>;
93 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
94 + clock-output-names = "apb2_mux";
99 compatible = "allwinner,sun6i-a31-apb2-div-clk";
100 reg = <0x01c20058 0x4>;
101 clocks = <&apb2_mux>;
102 + clock-output-names = "apb2";
105 - apb2_gates: apb2_gates@01c2006c {
106 + apb2_gates: clk@01c2006c {
108 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
109 reg = <0x01c2006c 0x4>;