target/linux/sunxi/patches-3.14/111-dt-sun4i-rename-clocknodes.patch

   1 From 35b7dfc295f4d6079572a22a225c7444134e1f72 Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Mon, 3 Feb 2014 09:51:41 +0800
   4 Subject: [PATCH] ARM: dts: sun4i: rename clock node names to clk@N
   5
   6 Device tree naming conventions state that node names should match
   7 node function. Change fully functioning clock nodes to match and
   8 add clock-output-names to all sunxi clock nodes.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun4i-a10.dtsi | 30 ++++++++++++++++++++----------
  14  1 file changed, 20 insertions(+), 10 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  17 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  18 @@ -58,34 +58,38 @@
  19                         clock-frequency = <0>;
  20                 };
  21
  22 -               osc24M: osc24M@01c20050 {
  23 +               osc24M: clk@01c20050 {
  24                         #clock-cells = <0>;
  25                         compatible = "allwinner,sun4i-osc-clk";
  26                         reg = <0x01c20050 0x4>;
  27                         clock-frequency = <24000000>;
  28 +                       clock-output-names = "osc24M";
  29                 };
  30
  31 -               osc32k: osc32k {
  32 +               osc32k: clk@0 {
  33                         #clock-cells = <0>;
  34                         compatible = "fixed-clock";
  35                         clock-frequency = <32768>;
  36 +                       clock-output-names = "osc32k";
  37                 };
  38
  39 -               pll1: pll1@01c20000 {
  40 +               pll1: clk@01c20000 {
  41                         #clock-cells = <0>;
  42                         compatible = "allwinner,sun4i-pll1-clk";
  43                         reg = <0x01c20000 0x4>;
  44                         clocks = <&osc24M>;
  45 +                       clock-output-names = "pll1";
  46                 };
  47
  48 -               pll4: pll4@01c20018 {
  49 +               pll4: clk@01c20018 {
  50                         #clock-cells = <0>;
  51                         compatible = "allwinner,sun4i-pll1-clk";
  52                         reg = <0x01c20018 0x4>;
  53                         clocks = <&osc24M>;
  54 +                       clock-output-names = "pll4";
  55                 };
  56
  57 -               pll5: pll5@01c20020 {
  58 +               pll5: clk@01c20020 {
  59                         #clock-cells = <1>;
  60                         compatible = "allwinner,sun4i-pll5-clk";
  61                         reg = <0x01c20020 0x4>;
  62 @@ -93,7 +97,7 @@
  63                         clock-output-names = "pll5_ddr", "pll5_other";
  64                 };
  65
  66 -               pll6: pll6@01c20028 {
  67 +               pll6: clk@01c20028 {
  68                         #clock-cells = <1>;
  69                         compatible = "allwinner,sun4i-pll6-clk";
  70                         reg = <0x01c20028 0x4>;
  71 @@ -107,6 +111,7 @@
  72                         compatible = "allwinner,sun4i-cpu-clk";
  73                         reg = <0x01c20054 0x4>;
  74                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  75 +                       clock-output-names = "cpu";
  76                 };
  77
  78                 axi: axi@01c20054 {
  79 @@ -114,9 +119,10 @@
  80                         compatible = "allwinner,sun4i-axi-clk";
  81                         reg = <0x01c20054 0x4>;
  82                         clocks = <&cpu>;
  83 +                       clock-output-names = "axi";
  84                 };
  85
  86 -               axi_gates: axi_gates@01c2005c {
  87 +               axi_gates: clk@01c2005c {
  88                         #clock-cells = <1>;
  89                         compatible = "allwinner,sun4i-axi-gates-clk";
  90                         reg = <0x01c2005c 0x4>;
  91 @@ -129,9 +135,10 @@
  92                         compatible = "allwinner,sun4i-ahb-clk";
  93                         reg = <0x01c20054 0x4>;
  94                         clocks = <&axi>;
  95 +                       clock-output-names = "ahb";
  96                 };
  97
  98 -               ahb_gates: ahb_gates@01c20060 {
  99 +               ahb_gates: clk@01c20060 {
 100                         #clock-cells = <1>;
 101                         compatible = "allwinner,sun4i-ahb-gates-clk";
 102                         reg = <0x01c20060 0x8>;
 103 @@ -154,9 +161,10 @@
 104                         compatible = "allwinner,sun4i-apb0-clk";
 105                         reg = <0x01c20054 0x4>;
 106                         clocks = <&ahb>;
 107 +                       clock-output-names = "apb0";
 108                 };
 109
 110 -               apb0_gates: apb0_gates@01c20068 {
 111 +               apb0_gates: clk@01c20068 {
 112                         #clock-cells = <1>;
 113                         compatible = "allwinner,sun4i-apb0-gates-clk";
 114                         reg = <0x01c20068 0x4>;
 115 @@ -171,6 +179,7 @@
 116                         compatible = "allwinner,sun4i-apb1-mux-clk";
 117                         reg = <0x01c20058 0x4>;
 118                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 119 +                       clock-output-names = "apb1_mux";
 120                 };
 121
 122                 apb1: apb1@01c20058 {
 123 @@ -178,9 +187,10 @@
 124                         compatible = "allwinner,sun4i-apb1-clk";
 125                         reg = <0x01c20058 0x4>;
 126                         clocks = <&apb1_mux>;
 127 +                       clock-output-names = "apb1";
 128                 };
 129
 130 -               apb1_gates: apb1_gates@01c2006c {
 131 +               apb1_gates: clk@01c2006c {
 132                         #clock-cells = <1>;
 133                         compatible = "allwinner,sun4i-apb1-gates-clk";
 134                         reg = <0x01c2006c 0x4>;