1 From f76e72a20510fa17934c82bed5e23f7c4a4f2931 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Sat, 22 Feb 2014 22:35:56 +0100
4 Subject: [PATCH] ARM: dt: sun5i: Add A10s SPI controller nodes
6 The A10s has 3 SPI controllers compatible with the one found in the A10. Add
9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
11 arch/arm/boot/dts/sun5i-a10s.dtsi | 33 +++++++++++++++++++++++++++++++++
12 1 file changed, 33 insertions(+)
14 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
15 index e5064dc..2dedb7c 100644
16 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
17 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
22 + spi0: spi@01c05000 {
23 + compatible = "allwinner,sun4i-a10-spi";
24 + reg = <0x01c05000 0x1000>;
26 + clocks = <&ahb_gates 20>, <&spi0_clk>;
27 + clock-names = "ahb", "mod";
28 + status = "disabled";
29 + #address-cells = <1>;
33 + spi1: spi@01c06000 {
34 + compatible = "allwinner,sun4i-a10-spi";
35 + reg = <0x01c06000 0x1000>;
37 + clocks = <&ahb_gates 21>, <&spi1_clk>;
38 + clock-names = "ahb", "mod";
39 + status = "disabled";
40 + #address-cells = <1>;
44 emac: ethernet@01c0b000 {
45 compatible = "allwinner,sun4i-a10-emac";
46 reg = <0x01c0b000 0x1000>;
51 + spi2: spi@01c17000 {
52 + compatible = "allwinner,sun4i-a10-spi";
53 + reg = <0x01c17000 0x1000>;
55 + clocks = <&ahb_gates 22>, <&spi2_clk>;
56 + clock-names = "ahb", "mod";
57 + status = "disabled";
58 + #address-cells = <1>;
62 intc: interrupt-controller@01c20400 {
63 compatible = "allwinner,sun4i-ic";
64 reg = <0x01c20400 0x400>;