1 From ac74dd1167924c412498a651edda63df49941f10 Mon Sep 17 00:00:00 2001
2 From: Hans de Goede <hdegoede@redhat.com>
3 Date: Sat, 4 Jan 2014 23:56:17 +0100
4 Subject: [PATCH] ARM: sunxi: Add driver for sunxi usb phy
6 The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed
7 through a single set of registers. Besides this there are also some other
8 phy related bits which need poking, which are per phy, but shared between the
9 ohci and ehci controllers, so these are also controlled from this new phy
12 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
14 .../devicetree/bindings/phy/sun4i-usb-phy.txt | 26 ++
15 drivers/phy/Kconfig | 11 +
16 drivers/phy/Makefile | 1 +
17 drivers/phy/phy-sun4i-usb.c | 329 +++++++++++++++++++++
18 4 files changed, 367 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
20 create mode 100644 drivers/phy/phy-sun4i-usb.c
22 diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
24 index 0000000..a82361b
26 +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
28 +Allwinner sun4i USB PHY
29 +-----------------------
32 +- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
33 + "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
34 +- reg : a list of offset + length pairs
35 +- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
36 +- #phy-cells : from the generic phy bindings, must be 1
37 +- clocks : phandle + clock specifier for the phy clock
38 +- clock-names : "usb_phy"
39 +- resets : a list of phandle + reset specifier pairs
40 +- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
43 + usbphy: phy@0x01c13400 {
45 + compatible = "allwinner,sun4i-a10-usb-phy";
46 + /* phy base regs, phy1 pmu reg, phy2 pmu reg */
47 + reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
48 + reg-names = "phy_ctrl", "pmu1", "pmu2";
49 + clocks = <&usb_clk 8>;
50 + clock-names = "usb_phy";
51 + resets = <&usb_clk 1>, <&usb_clk 2>;
52 + reset-names = "usb1_reset", "usb2_reset";
54 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
55 index 4ef8755..6e336b4 100644
56 --- a/drivers/phy/Kconfig
57 +++ b/drivers/phy/Kconfig
58 @@ -64,4 +64,15 @@ config BCM_KONA_USB2_PHY
60 Enable this to support the Broadcom Kona USB 2.0 PHY.
63 + tristate "Allwinner sunxi SoC USB PHY driver"
64 + depends on ARCH_SUNXI
67 + Enable this to support the transceiver that is part of Allwinner
70 + This driver controls the entire USB PHY block, both the USB OTG
71 + parts, as well as the 2 regular USB 2 host PHYs.
74 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
75 index b57c253..9d4f8bb 100644
76 --- a/drivers/phy/Makefile
77 +++ b/drivers/phy/Makefile
78 @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
79 obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
80 obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
81 obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
82 +obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
83 diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
85 index 0000000..31c4611
87 +++ b/drivers/phy/phy-sun4i-usb.c
90 + * Allwinner sun4i USB phy driver
92 + * Copyright (C) 2014 Hans de Goede <hdegoede@redhat.com>
94 + * Based on code from
95 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
97 + * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
98 + * Copyright (C) 2013 Samsung Electronics Co., Ltd.
99 + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
101 + * This program is free software; you can redistribute it and/or modify
102 + * it under the terms of the GNU General Public License as published by
103 + * the Free Software Foundation; either version 2 of the License, or
104 + * (at your option) any later version.
106 + * This program is distributed in the hope that it will be useful,
107 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
108 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
109 + * GNU General Public License for more details.
112 +#include <linux/clk.h>
113 +#include <linux/io.h>
114 +#include <linux/kernel.h>
115 +#include <linux/module.h>
116 +#include <linux/mutex.h>
117 +#include <linux/of.h>
118 +#include <linux/of_address.h>
119 +#include <linux/phy/phy.h>
120 +#include <linux/platform_device.h>
121 +#include <linux/regulator/consumer.h>
122 +#include <linux/reset.h>
124 +#define REG_ISCR 0x00
125 +#define REG_PHYCTL 0x04
126 +#define REG_PHYBIST 0x08
127 +#define REG_PHYTUNE 0x0c
129 +#define SUNXI_AHB_ICHR8_EN BIT(10)
130 +#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
131 +#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
132 +#define SUNXI_ULPI_BYPASS_EN BIT(0)
134 +/* Common Control Bits for Both PHYs */
135 +#define PHY_PLL_BW 0x03
136 +#define PHY_RES45_CAL_EN 0x0c
138 +/* Private Control Bits for Each PHY */
139 +#define PHY_TX_AMPLITUDE_TUNE 0x20
140 +#define PHY_TX_SLEWRATE_TUNE 0x22
141 +#define PHY_VBUSVALID_TH_SEL 0x25
142 +#define PHY_PULLUP_RES_SEL 0x27
143 +#define PHY_OTG_FUNC_EN 0x28
144 +#define PHY_VBUS_DET_EN 0x29
145 +#define PHY_DISCON_TH_SEL 0x2a
149 +struct sun4i_usb_phy_data {
151 + void __iomem *base;
152 + struct mutex mutex;
155 + struct sun4i_usb_phy {
158 + struct regulator *vbus;
159 + struct reset_control *reset;
164 +#define to_sun4i_usb_phy_data(phy) \
165 + container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
167 +static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
170 + struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
171 + u32 temp, usbc_bit = BIT(phy->index * 2);
174 + mutex_lock(&phy_data->mutex);
176 + for (i = 0; i < len; i++) {
177 + temp = readl(phy_data->base + REG_PHYCTL);
179 + /* clear the address portion */
180 + temp &= ~(0xff << 8);
182 + /* set the address */
183 + temp |= ((addr + i) << 8);
184 + writel(temp, phy_data->base + REG_PHYCTL);
186 + /* set the data bit and clear usbc bit*/
187 + temp = readb(phy_data->base + REG_PHYCTL);
193 + writeb(temp, phy_data->base + REG_PHYCTL);
195 + /* pulse usbc_bit */
196 + temp = readb(phy_data->base + REG_PHYCTL);
198 + writeb(temp, phy_data->base + REG_PHYCTL);
200 + temp = readb(phy_data->base + REG_PHYCTL);
202 + writeb(temp, phy_data->base + REG_PHYCTL);
206 + mutex_unlock(&phy_data->mutex);
209 +static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
211 + u32 bits, reg_value;
216 + bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
217 + SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
219 + reg_value = readl(phy->pmu);
224 + reg_value &= ~bits;
226 + writel(reg_value, phy->pmu);
229 +static int sun4i_usb_phy_init(struct phy *_phy)
231 + struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
232 + struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
235 + ret = clk_prepare_enable(data->clk);
239 + ret = reset_control_deassert(phy->reset);
241 + clk_disable_unprepare(data->clk);
245 + /* Adjust PHY's magnitude and rate */
246 + sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
248 + /* Disconnect threshold adjustment */
249 + sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2);
251 + sun4i_usb_phy_passby(phy, 1);
256 +static int sun4i_usb_phy_exit(struct phy *_phy)
258 + struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
259 + struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
261 + sun4i_usb_phy_passby(phy, 0);
262 + reset_control_assert(phy->reset);
263 + clk_disable_unprepare(data->clk);
268 +static int sun4i_usb_phy_power_on(struct phy *_phy)
270 + struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
274 + ret = regulator_enable(phy->vbus);
279 +static int sun4i_usb_phy_power_off(struct phy *_phy)
281 + struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
284 + regulator_disable(phy->vbus);
289 +static struct phy_ops sun4i_usb_phy_ops = {
290 + .init = sun4i_usb_phy_init,
291 + .exit = sun4i_usb_phy_exit,
292 + .power_on = sun4i_usb_phy_power_on,
293 + .power_off = sun4i_usb_phy_power_off,
294 + .owner = THIS_MODULE,
297 +static struct phy *sun4i_usb_phy_xlate(struct device *dev,
298 + struct of_phandle_args *args)
300 + struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
302 + if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys))
303 + return ERR_PTR(-ENODEV);
305 + return data->phys[args->args[0]].phy;
308 +static int sun4i_usb_phy_probe(struct platform_device *pdev)
310 + struct sun4i_usb_phy_data *data;
311 + struct device *dev = &pdev->dev;
312 + struct device_node *np = dev->of_node;
313 + void __iomem *pmu = NULL;
314 + struct phy_provider *phy_provider;
315 + struct reset_control *reset;
316 + struct regulator *vbus;
317 + struct resource *res;
322 + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
326 + mutex_init(&data->mutex);
328 + if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy"))
329 + data->num_phys = 2;
331 + data->num_phys = 3;
333 + if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy"))
334 + data->disc_thresh = 3;
336 + data->disc_thresh = 2;
338 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl");
339 + data->base = devm_ioremap_resource(dev, res);
340 + if (IS_ERR(data->base))
341 + return PTR_ERR(data->base);
343 + data->clk = devm_clk_get(dev, "usb_phy");
344 + if (IS_ERR(data->clk)) {
345 + dev_err(dev, "could not get usb_phy clock\n");
346 + return PTR_ERR(data->clk);
349 + /* Skip 0, 0 is the phy for otg which is not yet supported. */
350 + for (i = 1; i < data->num_phys; i++) {
351 + snprintf(name, sizeof(name), "usb%d_vbus", i);
352 + vbus = devm_regulator_get_optional(dev, name);
353 + if (IS_ERR(vbus)) {
354 + if (PTR_ERR(vbus) == -EPROBE_DEFER)
355 + return -EPROBE_DEFER;
359 + snprintf(name, sizeof(name), "usb%d_reset", i);
360 + reset = devm_reset_control_get(dev, name);
361 + if (IS_ERR(reset)) {
362 + dev_err(dev, "failed to get reset %s\n", name);
363 + return PTR_ERR(phy);
366 + if (i) { /* No pmu for usbc0 */
367 + snprintf(name, sizeof(name), "pmu%d", i);
368 + res = platform_get_resource_byname(pdev,
369 + IORESOURCE_MEM, name);
370 + pmu = devm_ioremap_resource(dev, res);
372 + return PTR_ERR(pmu);
375 + phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL);
377 + dev_err(dev, "failed to create PHY %d\n", i);
378 + return PTR_ERR(phy);
381 + data->phys[i].phy = phy;
382 + data->phys[i].pmu = pmu;
383 + data->phys[i].vbus = vbus;
384 + data->phys[i].reset = reset;
385 + data->phys[i].index = i;
386 + phy_set_drvdata(phy, &data->phys[i]);
389 + dev_set_drvdata(dev, data);
390 + phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
391 + if (IS_ERR(phy_provider))
392 + return PTR_ERR(phy_provider);
397 +static const struct of_device_id sun4i_usb_phy_of_match[] = {
398 + { .compatible = "allwinner,sun4i-a10-usb-phy" },
399 + { .compatible = "allwinner,sun5i-a13-usb-phy" },
400 + { .compatible = "allwinner,sun7i-a20-usb-phy" },
403 +MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
405 +static struct platform_driver sun4i_usb_phy_driver = {
406 + .probe = sun4i_usb_phy_probe,
408 + .of_match_table = sun4i_usb_phy_of_match,
409 + .name = "sun4i-usb-phy",
410 + .owner = THIS_MODULE,
413 +module_platform_driver(sun4i_usb_phy_driver);
415 +MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
416 +MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
417 +MODULE_LICENSE("GPL v2");