1 From d7904e075e3378bec09333b6a3247b3146b3dd91 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:43 -0300
4 Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds all the mod0 clocks available on A20 to its device
10 tree. This list was created by looking at AW's code release.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
15 arch/arm/boot/dts/sun7i-a20.dtsi | 120 +++++++++++++++++++++++++++++++++++++++
16 1 file changed, 120 insertions(+)
18 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
19 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
21 "apb1_uart2", "apb1_uart3", "apb1_uart4",
22 "apb1_uart5", "apb1_uart6", "apb1_uart7";
25 + nand_clk: clk@01c20080 {
27 + compatible = "allwinner,sun4i-mod0-clk";
28 + reg = <0x01c20080 0x4>;
29 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
30 + clock-output-names = "nand";
33 + ms_clk: clk@01c20084 {
35 + compatible = "allwinner,sun4i-mod0-clk";
36 + reg = <0x01c20084 0x4>;
37 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
38 + clock-output-names = "ms";
41 + mmc0_clk: clk@01c20088 {
43 + compatible = "allwinner,sun4i-mod0-clk";
44 + reg = <0x01c20088 0x4>;
45 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
46 + clock-output-names = "mmc0";
49 + mmc1_clk: clk@01c2008c {
51 + compatible = "allwinner,sun4i-mod0-clk";
52 + reg = <0x01c2008c 0x4>;
53 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
54 + clock-output-names = "mmc1";
57 + mmc2_clk: clk@01c20090 {
59 + compatible = "allwinner,sun4i-mod0-clk";
60 + reg = <0x01c20090 0x4>;
61 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
62 + clock-output-names = "mmc2";
65 + mmc3_clk: clk@01c20094 {
67 + compatible = "allwinner,sun4i-mod0-clk";
68 + reg = <0x01c20094 0x4>;
69 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
70 + clock-output-names = "mmc3";
73 + ts_clk: clk@01c20098 {
75 + compatible = "allwinner,sun4i-mod0-clk";
76 + reg = <0x01c20098 0x4>;
77 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
78 + clock-output-names = "ts";
81 + ss_clk: clk@01c2009c {
83 + compatible = "allwinner,sun4i-mod0-clk";
84 + reg = <0x01c2009c 0x4>;
85 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
86 + clock-output-names = "ss";
89 + spi0_clk: clk@01c200a0 {
91 + compatible = "allwinner,sun4i-mod0-clk";
92 + reg = <0x01c200a0 0x4>;
93 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
94 + clock-output-names = "spi0";
97 + spi1_clk: clk@01c200a4 {
99 + compatible = "allwinner,sun4i-mod0-clk";
100 + reg = <0x01c200a4 0x4>;
101 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
102 + clock-output-names = "spi1";
105 + spi2_clk: clk@01c200a8 {
106 + #clock-cells = <0>;
107 + compatible = "allwinner,sun4i-mod0-clk";
108 + reg = <0x01c200a8 0x4>;
109 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
110 + clock-output-names = "spi2";
113 + pata_clk: clk@01c200ac {
114 + #clock-cells = <0>;
115 + compatible = "allwinner,sun4i-mod0-clk";
116 + reg = <0x01c200ac 0x4>;
117 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
118 + clock-output-names = "pata";
121 + ir0_clk: clk@01c200b0 {
122 + #clock-cells = <0>;
123 + compatible = "allwinner,sun4i-mod0-clk";
124 + reg = <0x01c200b0 0x4>;
125 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
126 + clock-output-names = "ir0";
129 + ir1_clk: clk@01c200b4 {
130 + #clock-cells = <0>;
131 + compatible = "allwinner,sun4i-mod0-clk";
132 + reg = <0x01c200b4 0x4>;
133 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
134 + clock-output-names = "ir1";
137 + spi3_clk: clk@01c200d4 {
138 + #clock-cells = <0>;
139 + compatible = "allwinner,sun4i-mod0-clk";
140 + reg = <0x01c200d4 0x4>;
141 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
142 + clock-output-names = "spi3";