1 From 6d3ca59232090bff1b5e1abfd3417a3859e47425 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Mon, 23 Dec 2013 00:32:38 -0300
4 Subject: [PATCH] ARM: sunxi: add PLL5 and PLL6 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
15 arch/arm/boot/dts/sun4i-a10.dtsi | 19 +++++++++++++++++--
16 arch/arm/boot/dts/sun5i-a10s.dtsi | 19 +++++++++++++++++--
17 arch/arm/boot/dts/sun5i-a13.dtsi | 19 +++++++++++++++++--
18 arch/arm/boot/dts/sun7i-a20.dtsi | 28 ++++++++++++++++------------
19 4 files changed, 67 insertions(+), 18 deletions(-)
21 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
22 index 1d6346c..07564e9e 100644
23 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
24 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
29 + pll5: pll5@01c20020 {
31 + compatible = "allwinner,sun4i-pll5-clk";
32 + reg = <0x01c20020 0x4>;
34 + clock-output-names = "pll5_ddr", "pll5_other";
37 + pll6: pll6@01c20028 {
39 + compatible = "allwinner,sun4i-pll6-clk";
40 + reg = <0x01c20028 0x4>;
42 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
49 "apb0_ir1", "apb0_keypad";
52 - /* dummy is pll62 */
53 apb1_mux: apb1_mux@01c20058 {
55 compatible = "allwinner,sun4i-apb1-mux-clk";
56 reg = <0x01c20058 0x4>;
57 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
58 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
62 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
63 index 64d6d75..ca19362 100644
64 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
65 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
70 + pll5: pll5@01c20020 {
72 + compatible = "allwinner,sun4i-pll5-clk";
73 + reg = <0x01c20020 0x4>;
75 + clock-output-names = "pll5_ddr", "pll5_other";
78 + pll6: pll6@01c20028 {
80 + compatible = "allwinner,sun4i-pll6-clk";
81 + reg = <0x01c20028 0x4>;
83 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
90 "apb0_ir", "apb0_keypad";
93 - /* dummy is pll62 */
94 apb1_mux: apb1_mux@01c20058 {
96 compatible = "allwinner,sun4i-apb1-mux-clk";
97 reg = <0x01c20058 0x4>;
98 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
99 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
102 apb1: apb1@01c20058 {
103 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
104 index 2c355c8..9ac706a 100644
105 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
106 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
111 + pll5: pll5@01c20020 {
112 + #clock-cells = <1>;
113 + compatible = "allwinner,sun4i-pll5-clk";
114 + reg = <0x01c20020 0x4>;
115 + clocks = <&osc24M>;
116 + clock-output-names = "pll5_ddr", "pll5_other";
119 + pll6: pll6@01c20028 {
120 + #clock-cells = <1>;
121 + compatible = "allwinner,sun4i-pll6-clk";
122 + reg = <0x01c20028 0x4>;
123 + clocks = <&osc24M>;
124 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
130 @@ -132,12 +148,11 @@
131 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
134 - /* dummy is pll6 */
135 apb1_mux: apb1_mux@01c20058 {
137 compatible = "allwinner,sun4i-apb1-mux-clk";
138 reg = <0x01c20058 0x4>;
139 - clocks = <&osc24M>, <&dummy>, <&osc32k>;
140 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
143 apb1: apb1@01c20058 {
144 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
145 index 18144f0..9176ed0 100644
146 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
147 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
153 - * This is a dummy clock, to be used as placeholder on
154 - * other mux clocks when a specific parent clock is not
155 - * yet implemented. It should be dropped when the driver
159 - #clock-cells = <0>;
160 - compatible = "fixed-clock";
161 - clock-frequency = <0>;
162 + pll5: pll5@01c20020 {
163 + #clock-cells = <1>;
164 + compatible = "allwinner,sun4i-pll5-clk";
165 + reg = <0x01c20020 0x4>;
166 + clocks = <&osc24M>;
167 + clock-output-names = "pll5_ddr", "pll5_other";
170 + pll6: pll6@01c20028 {
171 + #clock-cells = <1>;
172 + compatible = "allwinner,sun4i-pll6-clk";
173 + reg = <0x01c20028 0x4>;
174 + clocks = <&osc24M>;
175 + clock-output-names = "pll6_sata", "pll6_other", "pll6";
180 compatible = "allwinner,sun4i-cpu-clk";
181 reg = <0x01c20054 0x4>;
182 - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
183 + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
189 compatible = "allwinner,sun4i-apb1-mux-clk";
190 reg = <0x01c20058 0x4>;
191 - clocks = <&osc24M>, <&pll6>, <&osc32k>;
192 + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
195 apb1: apb1@01c20058 {