1 From 0ae543fe8ae8b9ea7166c39b00e977506eccdf4b Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Wed, 4 Sep 2013 21:21:16 -0300
4 Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds all the mod0 clocks available on A10 and A13. The list
10 has been constructed by looking at the Allwinner code release for A10S
13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
16 arch/arm/boot/dts/sun5i-a10s.dtsi | 77 +++++++++++++++++++++++++++++++++++++++
17 arch/arm/boot/dts/sun5i-a13.dtsi | 77 +++++++++++++++++++++++++++++++++++++++
18 2 files changed, 154 insertions(+)
20 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
21 index 86e06e4..82b5ce6 100644
22 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
23 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
25 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
26 "apb1_uart2", "apb1_uart3";
29 + nand: nand@01c20080 {
31 + compatible = "allwinner,sun4i-mod0-clk";
32 + reg = <0x01c20080 0x4>;
33 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
38 + compatible = "allwinner,sun4i-mod0-clk";
39 + reg = <0x01c20084 0x4>;
40 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
43 + mmc0: mmc0@01c20088 {
45 + compatible = "allwinner,sun4i-mod0-clk";
46 + reg = <0x01c20088 0x4>;
47 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
50 + mmc1: mmc1@01c2008c {
52 + compatible = "allwinner,sun4i-mod0-clk";
53 + reg = <0x01c2008c 0x4>;
54 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
57 + mmc2: mmc2@01c20090 {
59 + compatible = "allwinner,sun4i-mod0-clk";
60 + reg = <0x01c20090 0x4>;
61 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
66 + compatible = "allwinner,sun4i-mod0-clk";
67 + reg = <0x01c20098 0x4>;
68 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
73 + compatible = "allwinner,sun4i-mod0-clk";
74 + reg = <0x01c2009c 0x4>;
75 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
78 + spi0: spi0@01c200a0 {
80 + compatible = "allwinner,sun4i-mod0-clk";
81 + reg = <0x01c200a0 0x4>;
82 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
85 + spi1: spi1@01c200a4 {
87 + compatible = "allwinner,sun4i-mod0-clk";
88 + reg = <0x01c200a4 0x4>;
89 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
92 + spi2: spi2@01c200a8 {
94 + compatible = "allwinner,sun4i-mod0-clk";
95 + reg = <0x01c200a8 0x4>;
96 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
100 + #clock-cells = <0>;
101 + compatible = "allwinner,sun4i-mod0-clk";
102 + reg = <0x01c200b0 0x4>;
103 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
108 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
109 index cded3c7..938e6d3 100644
110 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
111 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
113 clock-output-names = "apb1_i2c0", "apb1_i2c1",
114 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
117 + nand: nand@01c20080 {
118 + #clock-cells = <0>;
119 + compatible = "allwinner,sun4i-mod0-clk";
120 + reg = <0x01c20080 0x4>;
121 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
125 + #clock-cells = <0>;
126 + compatible = "allwinner,sun4i-mod0-clk";
127 + reg = <0x01c20084 0x4>;
128 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
131 + mmc0: mmc0@01c20088 {
132 + #clock-cells = <0>;
133 + compatible = "allwinner,sun4i-mod0-clk";
134 + reg = <0x01c20088 0x4>;
135 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
138 + mmc1: mmc1@01c2008c {
139 + #clock-cells = <0>;
140 + compatible = "allwinner,sun4i-mod0-clk";
141 + reg = <0x01c2008c 0x4>;
142 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
145 + mmc2: mmc2@01c20090 {
146 + #clock-cells = <0>;
147 + compatible = "allwinner,sun4i-mod0-clk";
148 + reg = <0x01c20090 0x4>;
149 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
153 + #clock-cells = <0>;
154 + compatible = "allwinner,sun4i-mod0-clk";
155 + reg = <0x01c20098 0x4>;
156 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
160 + #clock-cells = <0>;
161 + compatible = "allwinner,sun4i-mod0-clk";
162 + reg = <0x01c2009c 0x4>;
163 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
166 + spi0: spi0@01c200a0 {
167 + #clock-cells = <0>;
168 + compatible = "allwinner,sun4i-mod0-clk";
169 + reg = <0x01c200a0 0x4>;
170 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
173 + spi1: spi1@01c200a4 {
174 + #clock-cells = <0>;
175 + compatible = "allwinner,sun4i-mod0-clk";
176 + reg = <0x01c200a4 0x4>;
177 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
180 + spi2: spi2@01c200a8 {
181 + #clock-cells = <0>;
182 + compatible = "allwinner,sun4i-mod0-clk";
183 + reg = <0x01c200a8 0x4>;
184 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 + ir0: ir0@01c200b0 {
188 + #clock-cells = <0>;
189 + compatible = "allwinner,sun4i-mod0-clk";
190 + reg = <0x01c200b0 0x4>;
191 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;