1 From 8cf7164b32f2ce228b0c8116fd712484f67c65b5 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Wed, 4 Sep 2013 21:28:49 -0300
4 Subject: [PATCH] ARM: sun7i: dt: mod0 clocks
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit adds all the mod0 clocks available on A20 to its device
10 tree. This list was created by looking at AW's code release.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
13 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
15 arch/arm/boot/dts/sun7i-a20.dtsi | 105 +++++++++++++++++++++++++++++++++++++++
16 1 file changed, 105 insertions(+)
18 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
19 index 0af287e..0596e82 100644
20 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
21 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
23 "apb1_uart2", "apb1_uart3", "apb1_uart4",
24 "apb1_uart5", "apb1_uart6", "apb1_uart7";
27 + nand: nand@01c20080 {
29 + compatible = "allwinner,sun4i-mod0-clk";
30 + reg = <0x01c20080 0x4>;
31 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
36 + compatible = "allwinner,sun4i-mod0-clk";
37 + reg = <0x01c20084 0x4>;
38 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
41 + mmc0: mmc0@01c20088 {
43 + compatible = "allwinner,sun4i-mod0-clk";
44 + reg = <0x01c20088 0x4>;
45 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
48 + mmc1: mmc1@01c2008c {
50 + compatible = "allwinner,sun4i-mod0-clk";
51 + reg = <0x01c2008c 0x4>;
52 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
55 + mmc2: mmc2@01c20090 {
57 + compatible = "allwinner,sun4i-mod0-clk";
58 + reg = <0x01c20090 0x4>;
59 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
62 + mmc3: mmc3@01c20094 {
64 + compatible = "allwinner,sun4i-mod0-clk";
65 + reg = <0x01c20094 0x4>;
66 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
71 + compatible = "allwinner,sun4i-mod0-clk";
72 + reg = <0x01c20098 0x4>;
73 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
78 + compatible = "allwinner,sun4i-mod0-clk";
79 + reg = <0x01c2009c 0x4>;
80 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
83 + spi0: spi0@01c200a0 {
85 + compatible = "allwinner,sun4i-mod0-clk";
86 + reg = <0x01c200a0 0x4>;
87 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
90 + spi1: spi1@01c200a4 {
92 + compatible = "allwinner,sun4i-mod0-clk";
93 + reg = <0x01c200a4 0x4>;
94 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
97 + spi2: spi2@01c200a8 {
99 + compatible = "allwinner,sun4i-mod0-clk";
100 + reg = <0x01c200a8 0x4>;
101 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
104 + pata: pata@01c200ac {
105 + #clock-cells = <0>;
106 + compatible = "allwinner,sun4i-mod0-clk";
107 + reg = <0x01c200ac 0x4>;
108 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
111 + ir0: ir0@01c200b0 {
112 + #clock-cells = <0>;
113 + compatible = "allwinner,sun4i-mod0-clk";
114 + reg = <0x01c200b0 0x4>;
115 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
118 + ir1: ir1@01c200b4 {
119 + #clock-cells = <0>;
120 + compatible = "allwinner,sun4i-mod0-clk";
121 + reg = <0x01c200b4 0x4>;
122 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
125 + spi3: spi3@01c200d4 {
126 + #clock-cells = <0>;
127 + compatible = "allwinner,sun4i-mod0-clk";
128 + reg = <0x01c200d4 0x4>;
129 + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;