1 From 3473e6acea4bd01ba2b334628970390207f9f4fd Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Tue, 21 May 2013 21:25:05 -0300
4 Subject: [PATCH] clk: sunxi: mod0 support
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit implements support for the "module 0" type of clocks, as
10 used by MMC, IR, NAND, SATA and other components.
12 Signed-off-by: Emilio López <emilio@elopez.com.ar>
14 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
15 drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
16 2 files changed, 58 insertions(+)
18 diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
19 index 773f3ae..ff3f61c 100644
20 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
21 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
22 @@ -35,6 +35,7 @@ Required properties:
23 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
24 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
25 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
26 + "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
28 Required properties for all clocks:
29 - reg : shall be the control register address for the clock.
30 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
31 index 6947ba9..96c01b2 100644
32 --- a/drivers/clk/sunxi/clk-sunxi.c
33 +++ b/drivers/clk/sunxi/clk-sunxi.c
34 @@ -287,6 +287,47 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
38 + * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
39 + * MMC rate is calculated as follows
40 + * rate = (parent_rate >> p) / (m + 1);
43 +static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
44 + u8 *n, u8 *k, u8 *m, u8 *p)
46 + u8 div, calcm, calcp;
48 + /* These clocks can only divide, so we will never be able to achieve
49 + * frequencies higher than the parent frequency */
50 + if (*freq > parent_rate)
51 + *freq = parent_rate;
53 + div = parent_rate / *freq;
57 + else if (div / 2 < 16)
59 + else if (div / 4 < 16)
64 + calcm = DIV_ROUND_UP(div, 1 << calcp);
66 + *freq = (parent_rate >> calcp) / calcm;
68 + /* we were called to round the frequency, we can now return */
79 * sunxi_factors_clk_setup() - Setup function for factor clocks
82 @@ -333,6 +374,14 @@ struct factors_data {
86 +/* user manual says "n" but it's really "p" */
87 +static struct clk_factors_config sun4i_mod0_config = {
94 static const struct factors_data sun4i_pll1_data __initconst = {
96 .table = &sun4i_pll1_config,
97 @@ -356,6 +405,13 @@ struct factors_data {
98 .getter = sun4i_get_apb1_factors,
101 +static const struct factors_data sun4i_mod0_data __initconst = {
104 + .table = &sun4i_mod0_config,
105 + .getter = sun4i_get_mod0_factors,
108 static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
109 const struct factors_data *data)
111 @@ -779,6 +835,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
112 {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
113 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
114 {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
115 + {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},