1 From 337d479970b0c8493ee3e8b8d89fb80ee39333a6 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Sun, 5 May 2013 21:26:23 -0300
4 Subject: [PATCH] clk: sunxi: register factors clocks behind composite
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This commit reworks factors clock registration to be done behind a
10 composite clock. This allows us to additionally add a gate, mux or
11 divisors, as it will be needed by some future PLLs.
13 Signed-off-by: Emilio López <emilio@elopez.com.ar>
15 drivers/clk/sunxi/clk-factors.c | 63 +--------------------------------------
16 drivers/clk/sunxi/clk-factors.h | 16 +++++-----
17 drivers/clk/sunxi/clk-sunxi.c | 66 ++++++++++++++++++++++++++++++++++++++---
18 3 files changed, 72 insertions(+), 73 deletions(-)
20 diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
21 index 88523f9..6e3926c 100644
22 --- a/drivers/clk/sunxi/clk-factors.c
23 +++ b/drivers/clk/sunxi/clk-factors.c
25 * parent - fixed parent. No clk_set_parent support
31 - struct clk_factors_config *config;
32 - void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
36 #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
38 #define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos))
39 @@ -120,61 +112,8 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
43 -static const struct clk_ops clk_factors_ops = {
44 +const struct clk_ops clk_factors_ops = {
45 .recalc_rate = clk_factors_recalc_rate,
46 .round_rate = clk_factors_round_rate,
47 .set_rate = clk_factors_set_rate,
51 - * clk_register_factors - register a factors clock with
52 - * the clock framework
53 - * @dev: device registering this clock
54 - * @name: name of this clock
55 - * @parent_name: name of clock's parent
56 - * @flags: framework-specific flags
57 - * @reg: register address to adjust factors
58 - * @config: shift and width of factors n, k, m and p
59 - * @get_factors: function to calculate the factors for a given frequency
60 - * @lock: shared register lock for this clock
62 -struct clk *clk_register_factors(struct device *dev, const char *name,
63 - const char *parent_name,
64 - unsigned long flags, void __iomem *reg,
65 - struct clk_factors_config *config,
66 - void (*get_factors)(u32 *rate, u32 parent,
67 - u8 *n, u8 *k, u8 *m, u8 *p),
70 - struct clk_factors *factors;
72 - struct clk_init_data init;
74 - /* allocate the factors */
75 - factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
77 - pr_err("%s: could not allocate factors clk\n", __func__);
78 - return ERR_PTR(-ENOMEM);
82 - init.ops = &clk_factors_ops;
84 - init.parent_names = (parent_name ? &parent_name : NULL);
85 - init.num_parents = (parent_name ? 1 : 0);
87 - /* struct clk_factors assignments */
89 - factors->config = config;
90 - factors->lock = lock;
91 - factors->hw.init = &init;
92 - factors->get_factors = get_factors;
94 - /* register the clock */
95 - clk = clk_register(dev, &factors->hw);
102 diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
103 index f49851c..02e1a43 100644
104 --- a/drivers/clk/sunxi/clk-factors.h
105 +++ b/drivers/clk/sunxi/clk-factors.h
106 @@ -17,11 +17,13 @@ struct clk_factors_config {
110 -struct clk *clk_register_factors(struct device *dev, const char *name,
111 - const char *parent_name,
112 - unsigned long flags, void __iomem *reg,
113 - struct clk_factors_config *config,
114 - void (*get_factors) (u32 *rate, u32 parent_rate,
115 - u8 *n, u8 *k, u8 *m, u8 *p),
117 +struct clk_factors {
120 + struct clk_factors_config *config;
121 + void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
125 +extern const struct clk_ops clk_factors_ops;
127 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
128 index 34ee69f..6aed57f 100644
129 --- a/drivers/clk/sunxi/clk-sunxi.c
130 +++ b/drivers/clk/sunxi/clk-sunxi.c
131 @@ -256,7 +256,11 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
132 * sunxi_factors_clk_setup() - Setup function for factor clocks
135 +#define SUNXI_FACTORS_MUX_MASK 0x3
137 struct factors_data {
140 struct clk_factors_config *table;
141 void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
143 @@ -307,16 +311,70 @@ static void __init sunxi_factors_clk_setup(struct device_node *node,
144 struct factors_data *data)
147 + struct clk_factors *factors;
148 + struct clk_gate *gate;
149 + struct clk_mux *mux;
150 + struct clk_hw *gate_hw = NULL;
151 + struct clk_hw *mux_hw = NULL;
152 const char *clk_name = node->name;
153 - const char *parent;
154 + const char *parents[5];
158 reg = of_iomap(node, 0);
160 - parent = of_clk_get_parent_name(node, 0);
161 + /* if we have a mux, we will have >1 parents */
162 + while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
165 + factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
169 + /* Add a gate if this factor clock can be gated */
170 + if (data->enable) {
171 + gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
177 + /* set up gate properties */
179 + gate->bit_idx = data->enable;
180 + gate->lock = &clk_lock;
181 + gate_hw = &gate->hw;
184 - clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
185 - data->table, data->getter, &clk_lock);
186 + /* Add a mux if this factor clock can be muxed */
188 + mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
195 + /* set up gate properties */
197 + mux->shift = data->mux;
198 + mux->mask = SUNXI_FACTORS_MUX_MASK;
199 + mux->lock = &clk_lock;
203 + /* set up factors properties */
204 + factors->reg = reg;
205 + factors->config = data->table;
206 + factors->get_factors = data->getter;
207 + factors->lock = &clk_lock;
209 + clk = clk_register_composite(NULL, clk_name,
211 + mux_hw, &clk_mux_ops,
212 + &factors->hw, &clk_factors_ops,
213 + gate_hw, &clk_gate_ops,
214 + i ? 0 : CLK_IS_ROOT);
217 of_clk_add_provider(node, of_clk_src_simple_get, clk);