target/linux/storm/patches/1020-mtd.patch

   1 --- a/drivers/mtd/chips/Kconfig
   2 +++ b/drivers/mtd/chips/Kconfig
   3 @@ -220,6 +220,13 @@
   4           This option enables basic support for ROM chips accessed through
   5           a bus mapping driver.
   6
   7 +config MTD_SERIAL
   8 +       tristate "Support for Serial chips in bus mapping"
   9 +       depends on MTD
  10 +       help
  11 +         This option enables basic support for Serial chips accessed through
  12 +         a bus mapping driver.
  13 +
  14  config MTD_ABSENT
  15         tristate "Support for absent chips in bus mapping"
  16         help
  17 --- a/drivers/mtd/chips/cfi_cmdset_0002.c
  18 +++ b/drivers/mtd/chips/cfi_cmdset_0002.c
  19 @@ -39,10 +39,15 @@
  20  #include <linux/mtd/cfi.h>
  21  #include <linux/mtd/xip.h>
  22
  23 +//****** Storlink SoC ******
  24  #define AMD_BOOTLOC_BUG
  25 -#define FORCE_WORD_WRITE 0
  26 -
  27 -#define MAX_WORD_RETRIES 3
  28 +//#define FORCE_WORD_WRITE 0
  29 +#define FORCE_WORD_WRITE 1
  30 +#define FORCE_FAST_PROG 0
  31 +
  32 +//#define MAX_WORD_RETRIES 3
  33 +#define MAX_WORD_RETRIES 3 // CONFIG_MTD_CFI_AMDSTD_RETRY
  34 +//**************************
  35
  36  #define MANUFACTURER_AMD       0x0001
  37  #define MANUFACTURER_ATMEL     0x001F
  38 @@ -322,6 +327,13 @@
  39  #endif
  40
  41                 bootloc = extp->TopBottom;
  42 +//****** Storlink SoC ******
  43 +               if(bootloc == 5)
  44 +               {
  45 +                       bootloc = 3;
  46 +                       extp->TopBottom = 3;
  47 +               }
  48 +//**************************
  49                 if ((bootloc != 2) && (bootloc != 3)) {
  50                         printk(KERN_WARNING "%s: CFI does not contain boot "
  51                                "bank location. Assuming top.\n", map->name);
  52 @@ -340,6 +352,9 @@
  53                                 cfi->cfiq->EraseRegionInfo[j] = swap;
  54                         }
  55                 }
  56 +#ifdef CONFIG_MTD_MAP_BANK_WIDTH_1
  57 +               cfi->device_type = CFI_DEVICETYPE_X8;
  58 +#endif
  59                 /* Set the default CFI lock/unlock addresses */
  60                 cfi->addr_unlock1 = 0x555;
  61                 cfi->addr_unlock2 = 0x2aa;
  62 @@ -461,6 +476,7 @@
  63         map_word d, t;
  64
  65         d = map_read(map, addr);
  66 +       udelay(20);     //Storlink SoC
  67         t = map_read(map, addr);
  68
  69         return map_word_equal(map, d, t);
  70 @@ -626,7 +642,9 @@
  71         default:
  72                 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
  73         }
  74 +//****** Storlink SoC ******
  75         wake_up(&chip->wq);
  76 +//**************************
  77  }
  78
  79  #ifdef CONFIG_MTD_XIP
  80 @@ -940,7 +958,9 @@
  81         cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
  82         cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
  83
  84 +//****** Storlink SoC ******
  85         wake_up(&chip->wq);
  86 +//**************************
  87         spin_unlock(chip->mutex);
  88
  89         return 0;
  90 @@ -1005,7 +1025,10 @@
  91          */
  92         unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
  93         int ret = 0;
  94 -       map_word oldd;
  95 +//****** Storlink SoC ******
  96 +//     map_word oldd;
  97 +       map_word oldd, tmp;
  98 +//**************************
  99         int retry_cnt = 0;
 100
 101         adr += chip->start;
 102 @@ -1037,9 +1060,15 @@
 103         ENABLE_VPP(map);
 104         xip_disable(map, chip, adr);
 105   retry:
 106 +//****** Storlink SoC ******
 107 +#if FORCE_FAST_PROG  /* Unlock bypass */
 108 +       cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 109 +#else
 110         cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 111         cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
 112         cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 113 +#endif
 114 +//**************************
 115         map_write(map, datum, adr);
 116         chip->state = FL_WRITING;
 117
 118 @@ -1072,7 +1101,13 @@
 119                 }
 120
 121                 if (chip_ready(map, adr))
 122 -                       break;
 123 +               {
 124 +                       tmp = map_read(map, adr);
 125 +                       if(map_word_equal(map, tmp, datum))
 126 +//                             goto op_done;
 127 +                break;
 128 +
 129 +               }
 130
 131                 /* Latency issues. Drop the lock, wait a while and retry */
 132                 UDELAY(map, chip, adr, 1);
 133 @@ -1084,8 +1119,17 @@
 134                 /* FIXME - should have reset delay before continuing */
 135
 136                 if (++retry_cnt <= MAX_WORD_RETRIES)
 137 +               {
 138 +//****** Storlink SoC ******
 139 +#if FORCE_FAST_PROG
 140 +                       cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 141 +                       cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
 142 +                       cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 143 +               //udelay(1);
 144 +#endif
 145 +                       udelay(1);
 146                         goto retry;
 147 -
 148 +               }
 149                 ret = -EIO;
 150         }
 151         xip_enable(map, chip, adr);
 152 @@ -1171,7 +1215,14 @@
 153                                 return 0;
 154                 }
 155         }
 156 -
 157 +//****** Storlink SoC ******
 158 +       map_write( map, CMD(0xF0), chipstart );
 159 +#if FORCE_FAST_PROG
 160 +               cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 161 +               cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
 162 +               cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 163 +#endif
 164 +//**************************
 165         /* We are now aligned, write as much as possible */
 166         while(len >= map_bankwidth(map)) {
 167                 map_word datum;
 168 @@ -1181,7 +1232,15 @@
 169                 ret = do_write_oneword(map, &cfi->chips[chipnum],
 170                                        ofs, datum);
 171                 if (ret)
 172 +               {
 173 +//****** Storlink SoC ******
 174 +#if FORCE_FAST_PROG
 175 +                       /* Get out of unlock bypass mode */
 176 +                       cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
 177 +                       cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
 178 +#endif
 179                         return ret;
 180 +               }
 181
 182                 ofs += map_bankwidth(map);
 183                 buf += map_bankwidth(map);
 184 @@ -1189,19 +1248,38 @@
 185                 len -= map_bankwidth(map);
 186
 187                 if (ofs >> cfi->chipshift) {
 188 +//****** Storlink SoC ******
 189 +#if FORCE_FAST_PROG
 190 +                       /* Get out of unlock bypass mode */
 191 +                       cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
 192 +                       cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
 193 +#endif
 194                         chipnum ++;
 195                         ofs = 0;
 196                         if (chipnum == cfi->numchips)
 197                                 return 0;
 198                         chipstart = cfi->chips[chipnum].start;
 199 +#if FORCE_FAST_PROG
 200 +                       /* Go into unlock bypass mode for next set of chips */
 201 +                       cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 202 +                       cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
 203 +                       cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 204 +#endif
 205                 }
 206         }
 207
 208 +#if FORCE_FAST_PROG
 209 +       /* Get out of unlock bypass mode */
 210 +       cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
 211 +       cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
 212 +#endif
 213 +
 214         /* Write the trailing bytes if any */
 215         if (len & (map_bankwidth(map)-1)) {
 216                 map_word tmp_buf;
 217
 218   retry1:
 219 +
 220                 spin_lock(cfi->chips[chipnum].mutex);
 221
 222                 if (cfi->chips[chipnum].state != FL_READY) {
 223 @@ -1221,7 +1299,11 @@
 224  #endif
 225                         goto retry1;
 226                 }
 227 -
 228 +#if FORCE_FAST_PROG
 229 +               cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 230 +               cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, cfi->device_type, NULL);
 231 +               cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, cfi->device_type, NULL);
 232 +#endif
 233                 tmp_buf = map_read(map, ofs + chipstart);
 234
 235                 spin_unlock(cfi->chips[chipnum].mutex);
 236 @@ -1231,11 +1313,23 @@
 237                 ret = do_write_oneword(map, &cfi->chips[chipnum],
 238                                 ofs, tmp_buf);
 239                 if (ret)
 240 +               {
 241 +#if FORCE_FAST_PROG
 242 +       /* Get out of unlock bypass mode */
 243 +       cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
 244 +       cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
 245 +#endif
 246                         return ret;
 247 -
 248 +               }
 249 +#if FORCE_FAST_PROG
 250 +       /* Get out of unlock bypass mode */
 251 +       cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
 252 +       cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
 253 +#endif
 254                 (*retlen) += len;
 255         }
 256
 257 +       map_write( map, CMD(0xF0), chipstart );
 258         return 0;
 259  }
 260
 261 @@ -1275,6 +1369,7 @@
 262         ENABLE_VPP(map);
 263         xip_disable(map, chip, cmd_adr);
 264
 265 +       map_write( map, CMD(0xF0), chip->start );       //Storlink
 266         cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 267         cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
 268         //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
 269 @@ -1535,6 +1630,9 @@
 270         DECLARE_WAITQUEUE(wait, current);
 271         int ret = 0;
 272
 273 +#ifdef CONFIG_SL2312_SHARE_PIN
 274 +       mtd_lock();                             // sl2312 share pin lock
 275 +#endif
 276         adr += chip->start;
 277
 278         spin_lock(chip->mutex);
 279 @@ -1613,6 +1711,9 @@
 280         chip->state = FL_READY;
 281         put_chip(map, chip, adr);
 282         spin_unlock(chip->mutex);
 283 +#ifdef CONFIG_SL2312_SHARE_PIN
 284 +       mtd_unlock();                           // sl2312 share pin lock
 285 +#endif
 286         return ret;
 287  }
 288
 289 --- /dev/null
 290 +++ b/drivers/mtd/chips/map_serial.c
 291 @@ -0,0 +1,188 @@
 292 +/*
 293 + * Common code to handle map devices which are simple ROM
 294 + * (C) 2000 Red Hat. GPL'd.
 295 + * $Id: map_serial.c,v 1.3 2006/06/05 02:34:54 middle Exp $
 296 + */
 297 +
 298 +#include <linux/version.h>
 299 +#include <linux/module.h>
 300 +#include <linux/types.h>
 301 +#include <linux/kernel.h>
 302 +#include <asm/io.h>
 303 +
 304 +#include <asm/byteorder.h>
 305 +#include <linux/errno.h>
 306 +#include <linux/slab.h>
 307 +
 308 +#include <asm/hardware.h>
 309 +#include <linux/mtd/map.h>
 310 +#include <linux/mtd/mtd.h>
 311 +#include <linux/init.h> //add
 312 +#include <asm/arch/sl2312.h>
 313 +#include <asm/arch/flash.h>
 314 +
 315 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr);
 316 +static int mapserial_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
 317 +static int mapserial_write (struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
 318 +static void mapserial_nop (struct mtd_info *);
 319 +struct mtd_info *map_serial_probe(struct map_info *map);
 320 +
 321 +extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
 322 +
 323 +static struct mtd_chip_driver mapserial_chipdrv = {
 324 +       probe: map_serial_probe,
 325 +       name: "map_serial",
 326 +       module: THIS_MODULE
 327 +};
 328 +
 329 +struct mtd_info *map_serial_probe(struct map_info *map)
 330 +{
 331 +       struct mtd_info *mtd;
 332 +
 333 +       mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
 334 +       if (!mtd)
 335 +               return NULL;
 336 +
 337 +       memset(mtd, 0, sizeof(*mtd));
 338 +
 339 +       map->fldrv = &mapserial_chipdrv;
 340 +       mtd->priv = map;
 341 +       mtd->name = map->name;
 342 +       mtd->type = MTD_OTHER;
 343 +       mtd->erase = mapserial_erase;
 344 +       mtd->size = map->size;
 345 +       mtd->read = mapserial_read;
 346 +       mtd->write = mapserial_write;
 347 +       mtd->sync = mapserial_nop;
 348 +       mtd->flags = (MTD_WRITEABLE|MTD_ERASEABLE);
 349 +//     mtd->erasesize = 512; // page size;
 350 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
 351 +       mtd->erasesize = M25P80_SECTOR_SIZE; // block size;
 352 +#else
 353 +       mtd->erasesize = 0x1000; // block size;
 354 +#endif
 355 +
 356 +       __module_get(THIS_MODULE);
 357 +       //MOD_INC_USE_COUNT;
 358 +       return mtd;
 359 +}
 360 +
 361 +#define        FLASH_ACCESS_OFFSET                             0x00000010
 362 +#define        FLASH_ADDRESS_OFFSET                            0x00000014
 363 +#define        FLASH_WRITE_DATA_OFFSET                         0x00000018
 364 +#define        FLASH_READ_DATA_OFFSET                          0x00000018
 365 +
 366 +static __u32 readflash_ctrl_reg(__u32 ofs)
 367 +{
 368 +    __u32 *base;
 369 +
 370 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
 371 +    return __raw_readl(base);
 372 +}
 373 +
 374 +static void writeflash_ctrl_reg(__u32 data, __u32 ofs)
 375 +{
 376 +    __u32 *base;
 377 +
 378 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
 379 +    __raw_writel(data, base);
 380 +}
 381 +
 382 +static int mapserial_erase_block(struct map_info *map,unsigned int block)
 383 +{
 384 +
 385 +       __u32 address;
 386 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
 387 +
 388 +       if(!m25p80_sector_erase(block, 0))
 389 +               return (MTD_ERASE_DONE);
 390 +#else
 391 +      __u32 opcode;
 392 +      __u32 count=0;
 393 +//      __u8  status;
 394 +
 395 + //     printk("mapserial_erase_block : erase block %d \n",block);
 396 +//      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd;
 397 +      opcode = 0x80000000 | 0x0200 | 0x50;
 398 +      address = (block << 13);
 399 +      writeflash_ctrl_reg(address,FLASH_ADDRESS_OFFSET);
 400 +      writeflash_ctrl_reg(opcode,FLASH_ACCESS_OFFSET);
 401 +      opcode=readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
 402 +      while(opcode&0x80000000)
 403 +      {
 404 +          opcode = readflash_ctrl_reg(FLASH_ACCESS_OFFSET);
 405 +          count++;
 406 +          if (count > 10000)
 407 +          {
 408 +            return (MTD_ERASE_FAILED);
 409 +          }
 410 +      }
 411 +      return (MTD_ERASE_DONE);
 412 +#endif
 413 +}
 414 +
 415 +static int mapserial_erase(struct mtd_info *mtd, struct erase_info *instr)
 416 +{
 417 +       struct map_info *map = (struct map_info *)mtd->priv;
 418 +    unsigned int    addr;
 419 +    int             len;
 420 +    unsigned int    block;
 421 +    unsigned int    ret=0;
 422 +
 423 +       addr = instr->addr;
 424 +       len = instr->len;
 425 +    while (len > 0)
 426 +    {
 427 +        block = addr / mtd->erasesize;
 428 +#ifdef CONFIG_MTD_SL2312_SERIAL_ST
 429 +        ret = mapserial_erase_block(map,addr);
 430 +#else
 431 +               ret = mapserial_erase_block(map,block);
 432 +#endif
 433 +        addr = addr + mtd->erasesize;
 434 +        len = len - mtd->erasesize;
 435 +    }
 436 +    return (ret);
 437 +}
 438 +
 439 +static int mapserial_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
 440 +{
 441 +       struct map_info *map = (struct map_info *)mtd->priv;
 442 +//        printk("mapserial_read : \n");
 443 +       map->copy_from(map, buf, from, len);
 444 +       *retlen = len;
 445 +       return 0;
 446 +}
 447 +
 448 +static void mapserial_nop(struct mtd_info *mtd)
 449 +{
 450 +       /* Nothing to see here */
 451 +}
 452 +
 453 +static int mapserial_write (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf)
 454 +{
 455 +       struct map_info *map = (struct map_info *)mtd->priv;
 456 +//     printk("mapserial_write : buf %x to %x len %x \n",(int)buf, (int)to, (int)len);
 457 +       //map->copy_to(map, buf, to, len);
 458 +       map->copy_to(map, to, buf, len);
 459 +       *retlen = len;
 460 +       return 0;
 461 +}
 462 +
 463 +int __init map_serial_init(void)
 464 +{
 465 +       register_mtd_chip_driver(&mapserial_chipdrv);
 466 +       return 0;
 467 +}
 468 +
 469 +static void __exit map_serial_exit(void)
 470 +{
 471 +       unregister_mtd_chip_driver(&mapserial_chipdrv);
 472 +}
 473 +
 474 +module_init(map_serial_init);
 475 +module_exit(map_serial_exit);
 476 +
 477 +MODULE_LICENSE("GPL");
 478 +MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 479 +MODULE_DESCRIPTION("MTD chip driver for ROM chips");
 480 --- a/drivers/mtd/maps/Kconfig
 481 +++ b/drivers/mtd/maps/Kconfig
 482 @@ -614,5 +614,30 @@
 483
 484           This selection automatically selects the map_ram driver.
 485
 486 +#***************************************************************************************
 487 +# Storlink parallel/Serial Flash configuration
 488 +#***************************************************************************************
 489 +config MTD_SL2312_CFI
 490 +        tristate "CFI Flash device mapped on SL2312"
 491 +        depends on MTD_CFI
 492 +        help
 493 +          Map driver for SL2312 demo board.
 494 +
 495 +config MTD_SL2312_SERIAL_ATMEL
 496 +        tristate "ATMEL Serial Flash device mapped on SL2312"
 497 +        depends on MTD_PARTITIONS && ARCH_SL2312
 498 +        help
 499 +          Map driver for SL2312 demo board.
 500 +
 501 +config MTD_SL2312_SERIAL_ST
 502 +        tristate "ST Serial Flash device mapped on SL2312"
 503 +        depends on MTD_PARTITIONS && ARCH_SL2312
 504 +        help
 505 +          Map driver for SL2312 demo board.
 506 +
 507 +config SL2312_SHARE_PIN
 508 +        tristate "Parallel Flash share pin on SL2312 ASIC"
 509 +        depends on SL3516_ASIC
 510 +
 511  endmenu
 512
 513 --- /dev/null
 514 +++ b/drivers/mtd/maps/sl2312-flash-atmel.c
 515 @@ -0,0 +1,554 @@
 516 +/*
 517 + * $Id: sl2312-flash-atmel.c,v 1.2 2006/06/05 02:35:57 middle Exp $
 518 + *
 519 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
 520 + *
 521 + * (C) 2001 Red Hat, Inc.
 522 + *
 523 + * GPL'd
 524 + */
 525 +
 526 +#include <linux/module.h>
 527 +#include <linux/types.h>
 528 +#include <linux/kernel.h>
 529 +
 530 +#include <asm/io.h>
 531 +#include <linux/mtd/mtd.h>
 532 +#include <linux/mtd/map.h>
 533 +#include <linux/mtd/partitions.h>
 534 +#include <asm/hardware.h>
 535 +
 536 +#include <asm/arch/sl2312.h>
 537 +#include <asm/arch/flash.h>
 538 +#include <linux/init.h> //add
 539 +
 540 +
 541 +#define  g_page_addr  AT45DB321_PAGE_SHIFT    //321 : shift 10  ; 642 : shift 11
 542 +#define  g_chipen     SERIAL_FLASH_CHIP0_EN   //atmel
 543 +
 544 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
 545 +
 546 +void address_to_page(__u32 address, __u16 *page, __u16 *offset)
 547 +{
 548 +    *page = address / SPAGE_SIZE;
 549 +    *offset = address % SPAGE_SIZE;
 550 +}
 551 +
 552 +static __u32 read_flash_ctrl_reg(__u32 ofs)
 553 +{
 554 +    __u32 *base;
 555 +
 556 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
 557 +    return __raw_readl(base);
 558 +}
 559 +
 560 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
 561 +{
 562 +    __u32 *base;
 563 +
 564 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
 565 +    __raw_writel(data, base);
 566 +}
 567 +
 568 +void atmel_read_status(__u8 cmd, __u8 *data)
 569 +{
 570 +      __u32 opcode;
 571 +      __u32 value;
 572 +
 573 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | cmd | g_chipen;
 574 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 575 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 576 +      while(opcode&0x80000000)
 577 +      {
 578 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 579 +          flash_delay();
 580 +          schedule();
 581 +      }
 582 +
 583 +      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
 584 +      *data = value & 0xff;
 585 +}
 586 +
 587 +void main_memory_page_read(__u8 cmd, __u16 page, __u16 offset, __u8 *data)
 588 +{
 589 +      __u32 opcode;
 590 +      __u32 address;
 591 +      __u32 value;
 592 +
 593 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA | cmd | g_chipen;
 594 +      address = (page << g_page_addr) + offset;
 595 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 596 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 597 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 598 +      while(opcode&0x80000000)
 599 +      {
 600 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 601 +          flash_delay();
 602 +          schedule();
 603 +      }
 604 +
 605 +      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
 606 +      *data = value & 0xff;
 607 +}
 608 +
 609 +void buffer_to_main_memory(__u8 cmd, __u16 page)
 610 +{
 611 +      __u32 opcode;
 612 +      __u32 address;
 613 +      __u8  status;
 614 +
 615 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
 616 +      address = (page << g_page_addr);
 617 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 618 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 619 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 620 +      while(opcode&0x80000000)
 621 +      {
 622 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 623 +          flash_delay();
 624 +          schedule();
 625 +      }
 626 +      atmel_read_status(READ_STATUS_SPI, &status);
 627 +      while(!(status&0x80))
 628 +      {
 629 +          atmel_read_status(READ_STATUS_SPI, &status);
 630 +          flash_delay();
 631 +          schedule();
 632 +      }
 633 +
 634 +}
 635 +
 636 +
 637 +void atmel_flash_read_page(__u32 address, __u8 *buffer, __u32 len)
 638 +{
 639 +    __u8  byte;
 640 +    __u16 page, offset;
 641 +    __u16 i;
 642 +
 643 +    address_to_page(address, &page, &offset);
 644 +
 645 +     for(i=0; i<len; i++,offset++)
 646 +    {
 647 +        main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
 648 +        buffer [i]= byte;
 649 +    }
 650 +}
 651 +
 652 +void atmel_flash_program_page(__u32 address, __u8 *buffer, __u32 len)
 653 +{
 654 +    __u8  pattern;
 655 +    __u16 page, offset;
 656 +    __u32 i;
 657 +
 658 +    address_to_page(address, &page, &offset);
 659 + //   printk("atmel_flash_program_page: offset %x len %x page %x \n", offset, len, page);
 660 +
 661 +    if(offset)
 662 +           main_memory_to_buffer(MAIN_MEMORY_TO_BUFFER1,page);
 663 +
 664 +    for(i=0; i<len; i++,offset++)
 665 +    {
 666 +        pattern = buffer[i];
 667 +        atmel_buffer_write(BUFFER1_WRITE,offset,pattern);
 668 +    }
 669 +
 670 +  //  printk("atmel_flash_program_page: offset %x \n", offset);
 671 +    buffer_to_main_memory(BUFFER1_TO_MAIN_MEMORY, page);
 672 +  //  printk("atmel_flash_program_page: buffer_to_main_memory %x page\n", page);
 673 +
 674 +}
 675 +
 676 +
 677 +void main_memory_to_buffer(__u8 cmd, __u16 page)
 678 +{
 679 +      __u32 opcode;
 680 +      __u32 address;
 681 +      __u8  status;
 682 +
 683 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
 684 +      address = (page << g_page_addr);
 685 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 686 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 687 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 688 +      while(opcode&0x80000000)
 689 +      {
 690 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 691 +          flash_delay();
 692 +          schedule();
 693 +      }
 694 +      atmel_read_status(READ_STATUS_SPI, &status);
 695 +      while(!(status&0x80))
 696 +      {
 697 +          atmel_read_status(READ_STATUS_SPI, &status);
 698 +          flash_delay();
 699 +          schedule();
 700 +      }
 701 +
 702 +}
 703 +
 704 +void main_memory_page_program(__u8 cmd, __u16 page, __u16 offset, __u8 data)
 705 +{
 706 +      __u32 opcode;
 707 +      __u32 address;
 708 +      __u8  status;
 709 +
 710 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd | g_chipen;
 711 +      address = (page << g_page_addr) + offset;
 712 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 713 +      write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
 714 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 715 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 716 +      while(opcode&0x80000000)
 717 +      {
 718 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 719 +          flash_delay();
 720 +          schedule();
 721 +      }
 722 +      atmel_read_status(READ_STATUS_SPI, &status);
 723 +      while(!(status&0x80))
 724 +      {
 725 +          atmel_read_status(READ_STATUS_SPI, &status);
 726 +          flash_delay();
 727 +          schedule();
 728 +      }
 729 +}
 730 +
 731 +void atmel_buffer_write(__u8 cmd, __u16 offset, __u8 data)
 732 +{
 733 +      __u32 opcode;
 734 +      __u32 address;
 735 +
 736 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | cmd  | g_chipen;
 737 +      address = offset;
 738 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 739 +      write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, data);
 740 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 741 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 742 +      while(opcode&0x80000000)
 743 +      {
 744 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 745 +          flash_delay();
 746 +          schedule();
 747 +      }
 748 +
 749 +}
 750 +
 751 +void atmel_erase_page(__u8 cmd, __u16 page)
 752 +{
 753 +      __u32 opcode;
 754 +      __u32 address;
 755 +      __u8  status;
 756 +
 757 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
 758 +      address = (page << g_page_addr);
 759 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 760 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 761 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 762 +      while(opcode&0x80000000)
 763 +      {
 764 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 765 +          flash_delay();
 766 +          schedule();
 767 +      }
 768 +      atmel_read_status(READ_STATUS_SPI, &status);
 769 +      while(!(status&0x80))
 770 +      {
 771 +          atmel_read_status(READ_STATUS_SPI, &status);
 772 +          flash_delay();
 773 +          schedule();
 774 +      }
 775 +
 776 +}
 777 +
 778 +void atmel_erase_block(__u8 cmd, __u16 block)
 779 +{
 780 +      __u32 opcode;
 781 +      __u32 address;
 782 +      __u8  status;
 783 +
 784 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | cmd | g_chipen;
 785 +      address = (block << 13);
 786 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
 787 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
 788 +      opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 789 +      while(opcode&0x80000000)
 790 +      {
 791 +          opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
 792 +          flash_delay();
 793 +          schedule();
 794 +      }
 795 +      atmel_read_status(READ_STATUS_SPI, &status);
 796 +      while(!(status&0x80))
 797 +      {
 798 +          atmel_read_status(READ_STATUS_SPI, &status);
 799 +          flash_delay();
 800 +          schedule();
 801 +      }
 802 +
 803 +}
 804 +
 805 +void flash_delay(void)
 806 +{
 807 +      int i;
 808 +
 809 +      for(i=0; i<50; i++)
 810 +           i=i;
 811 +}
 812 +
 813 +
 814 +
 815 +
 816 +__u32 sl2312_read32(struct map_info *map, unsigned long ofs)
 817 +{
 818 +
 819 +#if 0
 820 +    __u16 page, offset;
 821 +    __u32 pattern;
 822 +    __u8  byte, i;
 823 +
 824 +     pattern = 0;
 825 +     address_to_page(ofs, &page, &offset);
 826 +     for(i=0; i<4; i++, offset++)
 827 +    {
 828 +        pattern = pattern << 8;
 829 +        main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
 830 +//printk("sl2312_read32:: address = %08x  data = %c \n",ofs,byte);
 831 +        pattern += byte;
 832 +    }
 833 +    return pattern;
 834 +#else
 835 +      return read_flash_ctrl_reg(ofs);
 836 +#endif
 837 +
 838 +}
 839 +
 840 +__u8 sl2312_read8(struct map_info *map, unsigned long ofs)
 841 +{
 842 +    __u16 page, offset;
 843 +    __u8  byte;
 844 +
 845 +     address_to_page(ofs, &page, &offset);
 846 +     main_memory_page_read(MAIN_MEMORY_PAGE_READ_SPI , page, offset, &byte);
 847 +        //printk("sl2312_read8:: address = %08x  data = %c \n",ofs,byte);
 848 +     return byte;
 849 +
 850 +}
 851 +
 852 +void sl2312_write32(struct map_info *map, __u32 d, unsigned long ofs)
 853 +{
 854 +#if 0
 855 +    __u16 page, offset;
 856 +    __u8  byte, i;
 857 +
 858 +     address_to_page(ofs, &page, &offset);
 859 +     for(i=0; i<4; i++, offset++)
 860 +    {
 861 +       byte = d & 0xff;
 862 +        main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, byte);
 863 +        d = d >> 8;
 864 +//printk("sl2312_write32:: address = %08x  data = %c \n",ofs,byte);
 865 +    }
 866 +#else
 867 +      write_flash_ctrl_reg(ofs, d);
 868 +#endif
 869 +}
 870 +
 871 +void sl2312_write8(struct map_info *map, __u8 d, unsigned long ofs)
 872 +{
 873 +     __u16 page, offset;
 874 +
 875 +     address_to_page(ofs, &page, &offset);
 876 +     main_memory_page_program(MAIN_MEMORY_PROGRAM_BUFFER1, page, offset, d);
 877 +//printk("sl2312_write8:: address = %08x  data = %c \n",ofs,d);
 878 +
 879 +}
 880 +
 881 +void sl2312_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
 882 +{
 883 +     __u32 size;
 884 +     __u8  *buffer;
 885 +     __u32 length;//i, j,
 886 +
 887 +     //printk("sl2312_copy_from:: address = %08x  datalen = %d \n",ofs,len);
 888 +
 889 +     length = len;
 890 +     buffer = (__u8 *)buf;
 891 +     while(len)
 892 +     {
 893 +        size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
 894 +        if(size > len)
 895 +            size = len;
 896 +        atmel_flash_read_page(ofs, buffer, size);
 897 +        buffer+=size;
 898 +        ofs+=size;
 899 +        len -= size;
 900 +     }
 901 +
 902 +#if 0
 903 +        buffer = (__u8 *)buf;
 904 +        for(i=0; i<length; i+=16)
 905 +       {
 906 +          for(j=0; j<16; j++,buffer++)
 907 +         {
 908 +            if((i*16+j)<length)
 909 +              printk("%x  ",(int)*buffer);
 910 +        }
 911 +          printk("\n");
 912 +       }
 913 +
 914 +       printk("\n");
 915 +#endif
 916 +
 917 +}
 918 +
 919 +
 920 +void sl2312_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
 921 +{
 922 +     __u32 size;
 923 +     __u8  *buffer;
 924 +
 925 +     buffer = (__u8 *)buf;
 926 +     //printk("sl2312_copy_to:offset %x len %x \n", ofs, len);
 927 +//     printk("sl2312_copy_to:buf is %x \n", (int)buf);
 928 +
 929 +     while(len)
 930 +     {
 931 +        size = SPAGE_SIZE - (ofs%SPAGE_SIZE);
 932 +        if(size > len)
 933 +            size = len;
 934 +        atmel_flash_program_page(ofs, buffer, size);
 935 +        buffer+=size;
 936 +        ofs+=size;
 937 +       len-=size;
 938 +    }
 939 +
 940 +
 941 +}
 942 +
 943 +
 944 +static struct mtd_info *serial_mtd;
 945 +
 946 +static struct mtd_partition *parsed_parts;
 947 +
 948 +static struct map_info sl2312_serial_map = {
 949 +//     name: "SL2312 serial flash",
 950 +//     size: 4194304, //0x400000,
 951 +//             //buswidth: 4,
 952 +//     bankwidth: 4,
 953 +//     phys:            SL2312_FLASH_BASE,
 954 +//#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
 955 +//     //read32: sl2312_read32,
 956 +//     //read8: sl2312_read8,
 957 +//     copy_from: sl2312_copy_from,
 958 +//     //write8: sl2312_write8,
 959 +//     //write32: sl2312_write32,
 960 +//     read: sl2312_read32,
 961 +//     write: sl2312_write32,
 962 +//     copy_to: sl2312_copy_to
 963 +//#endif
 964 +       .name = "SL2312 serial flash",
 965 +       .size = 4194304, //0x400000,
 966 +               //buswidth: 4,
 967 +       .bankwidth = 4,
 968 +       .phys =          SL2312_FLASH_BASE,
 969 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
 970 +       //read32: sl2312_read32,
 971 +       //read8: sl2312_read8,
 972 +       .copy_from = sl2312_copy_from,
 973 +       //write8: sl2312_write8,
 974 +       //write32: sl2312_write32,
 975 +       .read = sl2312_read32,
 976 +       .write = sl2312_write32,
 977 +       .copy_to = sl2312_copy_to
 978 +#endif
 979 +};
 980 +
 981 +
 982 +
 983 +static struct mtd_partition sl2312_partitions[] = {
 984 +
 985 +
 986 +       ///* boot code */
 987 +       //{ name: "bootloader", offset: 0x00000000, size: 0x20000, },
 988 +       ///* kernel image */
 989 +       //{ name: "kerel image", offset: 0x000020000, size: 0x2E0000 },
 990 +       ///* All else is writable (e.g. JFFS) */
 991 +       //{ name: "user data", offset: 0x00300000, size: 0x00100000, },
 992 +       /* boot code */
 993 +       { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
 994 +       /* kernel image */
 995 +       { .name = "kerel image", .offset = 0x000020000, .size = 0xE0000 },
 996 +       /* All else is writable (e.g. JFFS) */
 997 +       { .name = "user data", .offset = 0x00100000, .size = 0x00300000, },
 998 +
 999 +
1000 +};
1001 +
1002 +
1003 +
1004 +static int __init init_sl2312_maps(void)
1005 +{
1006 +       int nr_parts = 0;
1007 +       struct mtd_partition *parts;
1008 +
1009 +       serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1010 +       if (!serial_mtd)
1011 +               return NULL;
1012 +
1013 +       memset(serial_mtd, 0, sizeof(struct mtd_info));
1014 +       //sl2312flash_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1015 +    //sl2312_serial_map.map_priv_1 = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)FLASH_VBASE;
1016 +    sl2312_serial_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1017 +    if (!sl2312_serial_map.virt) {
1018 +               printk(" failed to ioremap \n");
1019 +               return -EIO;
1020 +       }
1021 +       serial_mtd = do_map_probe("map_serial", &sl2312_serial_map);
1022 +       if (serial_mtd) {
1023 +               //serial_mtd->module = THIS_MODULE;
1024 +               serial_mtd->owner = THIS_MODULE;
1025 +
1026 +       }
1027 +
1028 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1029 +       nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1030 +       if (nr_parts > 0)
1031 +               printk(KERN_NOTICE "Found RedBoot partition table.\n");
1032 +       else if (nr_parts < 0)
1033 +               printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1034 +#else
1035 +       parsed_parts = sl2312_partitions;
1036 +       parts = sl2312_partitions;
1037 +       nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1038 +       nr_parts = sizeof(sl2312_partitions)/sizeof(*parsed_parts);
1039 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1040 +
1041 +       if (nr_parts > 0)
1042 +           add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1043 +       else
1044 +           add_mtd_device(serial_mtd);
1045 +
1046 +       return 0;
1047 +}
1048 +
1049 +static void __exit cleanup_sl2312_maps(void)
1050 +{
1051 +       if (parsed_parts)
1052 +           del_mtd_partitions(serial_mtd);
1053 +       else
1054 +           del_mtd_device(serial_mtd);
1055 +
1056 +       map_destroy(serial_mtd);
1057 +
1058 +
1059 +}
1060 +
1061 +module_init(init_sl2312_maps);
1062 +module_exit(cleanup_sl2312_maps);
1063 +
1064 +
1065 +
1066 +MODULE_LICENSE("GPL");
1067 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1068 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1069 +
1070 --- /dev/null
1071 +++ b/drivers/mtd/maps/sl2312-flash-cfi.c
1072 @@ -0,0 +1,370 @@
1073 +/*======================================================================
1074 +
1075 +   This program is free software; you can redistribute it and/or modify
1076 +   it under the terms of the GNU General Public License as published by
1077 +   the Free Software Foundation; either version 2 of the License, or
1078 +   (at your option) any later version.
1079 +
1080 +   This program is distributed in the hope that it will be useful,
1081 +   but WITHOUT ANY WARRANTY; without even the implied warranty of
1082 +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1083 +   GNU General Public License for more details.
1084 +
1085 +   You should have received a copy of the GNU General Public License
1086 +   along with this program; if not, write to the Free Software
1087 +   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1088 +======================================================================*/
1089 +
1090 +#include <linux/module.h>
1091 +#include <linux/types.h>
1092 +#include <linux/kernel.h>
1093 +#include <linux/slab.h>
1094 +#include <linux/ioport.h>
1095 +#include <linux/init.h>
1096 +#include <linux/string.h>
1097 +
1098 +#include <linux/mtd/mtd.h>
1099 +#include <linux/mtd/map.h>
1100 +#include <linux/mtd/partitions.h>
1101 +
1102 +#include <asm/hardware.h>
1103 +#include <asm/io.h>
1104 +#include <asm/system.h>
1105 +#include <asm/arch/sl2312.h>
1106 +#include <linux/mtd/kvctl.h>
1107 +#include "sl2312_flashmap.h"
1108 +
1109 +
1110 +//extern int parse_afs_partitions(struct mtd_info *, struct mtd_partition **);
1111 +
1112 +/* the base address of FLASH control register */
1113 +#define FLASH_CONTROL_BASE_ADDR            (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
1114 +#define SL2312_GLOBAL_BASE_ADDR     (IO_ADDRESS(SL2312_GLOBAL_BASE))
1115 +
1116 +/* define read/write register utility */
1117 +#define FLASH_READ_REG(offset)                 (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
1118 +#define FLASH_WRITE_REG(offset,val)    (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
1119 +
1120 +/* the offset of FLASH control register */
1121 +enum EMAC_REGISTER {
1122 +       FLASH_ID        = 0x0000,
1123 +       FLASH_STATUS    = 0x0008,
1124 +       FLASH_TYPE      = 0x000c,
1125 +       FLASH_ACCESS    = 0x0020,
1126 +       FLASH_ADDRESS   = 0x0024,
1127 +       FLASH_DATA              = 0x0028,
1128 +       FLASH_TIMING    = 0x002c,
1129 +};
1130 +
1131 +//#define FLASH_BASE   FLASH_CONTROL_BASE_ADDR
1132 +//#define FLASH_SIZE   0x00800000 //INTEGRATOR_FLASH_SIZE
1133 +
1134 +//#define FLASH_PART_SIZE 8388608
1135 +
1136 +static unsigned int flash_indirect_access = 0;
1137 +
1138 +#ifdef CONFIG_SL2312_SHARE_PIN
1139 +static unsigned int chip_en = 0x00000000;
1140 +
1141 +void sl2312flash_enable_parallel_flash(void)
1142 +{
1143 +    unsigned int    reg_val;
1144 +
1145 +    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1146 +    reg_val = reg_val & 0xfffffffd;
1147 +    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1148 +    return;
1149 +}
1150 +
1151 +void sl2312flash_disable_parallel_flash(void)
1152 +{
1153 +    unsigned int    reg_val;
1154 +
1155 +    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1156 +    reg_val = reg_val | 0x00000002;
1157 +    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1158 +    return;
1159 +}
1160 +#endif
1161 +
1162 +
1163 +static struct map_info sl2312flash_map =
1164 +{
1165 +       name:           "SL2312 CFI Flash",
1166 +       size:       FLASH_SIZE,
1167 +       bankwidth:   2,
1168 +       //bankwidth:   1, //for 8 bits width
1169 +    phys:       SL2312_FLASH_BASE,
1170 +};
1171 +
1172 +static struct mtd_info *mtd;
1173 +#if 0
1174 +static struct mtd_partition sl2312_partitions[] = {
1175 +       /* boot code */
1176 +       {
1177 +               name: "bootloader",
1178 +               offset: 0x00000000,
1179 +               size: 0x20000,
1180 +//             mask_flags: MTD_WRITEABLE,
1181 +       },
1182 +       /* kernel image */
1183 +       {
1184 +               name: "kerel image",
1185 +               offset: 0x00020000,
1186 +               size: 0x2E0000
1187 +       },
1188 +       /* All else is writable (e.g. JFFS) */
1189 +       {
1190 +               name: "user data",
1191 +               offset: 0x00300000,
1192 +               size: 0x00100000,
1193 +       }
1194 +};
1195 +#endif
1196 +
1197 +
1198 +
1199 +static int __init sl2312flash_init(void)
1200 +{
1201 +       struct mtd_partition *parts;
1202 +       int nr_parts = 0;
1203 +       int ret;
1204 +#ifndef CONFIG_SL2312_SHARE_PIN
1205 +    unsigned int    reg_val;
1206 +#endif
1207 +
1208 +    printk("SL2312 MTD Driver Init.......\n");
1209 +
1210 +#ifndef CONFIG_SL2312_SHARE_PIN
1211 +       /* enable flash */
1212 +    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
1213 +    reg_val = reg_val & 0xfffffffd;
1214 +    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
1215 +#else
1216 +    sl2312flash_enable_parallel_flash();      /* enable Parallel FLASH */
1217 +#endif
1218 +    FLASH_WRITE_REG(FLASH_ACCESS,0x00004000); /* parallel flash direct access mode */
1219 +    ret = FLASH_READ_REG(FLASH_ACCESS);
1220 +    if (ret == 0x00004000)
1221 +    {
1222 +        flash_indirect_access = 0;  /* parallel flash direct access */
1223 +    }
1224 +    else
1225 +    {
1226 +        flash_indirect_access = 1;  /* parallel flash indirect access */
1227 +    }
1228 +
1229 +       /*
1230 +        * Also, the CFI layer automatically works out what size
1231 +        * of chips we have, and does the necessary identification
1232 +        * for us automatically.
1233 +        */
1234 +#ifdef CONFIG_GEMINI_IPI
1235 +       sl2312flash_map.virt = FLASH_VBASE;//(unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1236 +#else
1237 +       sl2312flash_map.virt = (unsigned int *)ioremap(SL2312_FLASH_BASE, FLASH_SIZE);
1238 +#endif
1239 +       //printk("sl2312flash_map.virt  = %08x\n",(unsigned int)sl2312flash_map.virt);
1240 +
1241 +//     simple_map_init(&sl2312flash_map);
1242 +
1243 +       mtd = do_map_probe("cfi_probe", &sl2312flash_map);
1244 +       if (!mtd)
1245 +       {
1246 +#ifdef CONFIG_SL2312_SHARE_PIN
1247 +        sl2312flash_disable_parallel_flash();      /* disable Parallel FLASH */
1248 +#endif
1249 +               return -ENXIO;
1250 +       }
1251 +       mtd->owner = THIS_MODULE;
1252 +//    mtd->erase = flash_erase;
1253 +//    mtd->read = flash_read;
1254 +//    mtd->write = flash_write;
1255 +
1256 +    parts = sl2312_partitions;
1257 +       nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
1258 +       ret = add_mtd_partitions(mtd, parts, nr_parts);
1259 +       /*If we got an error, free all resources.*/
1260 +       if (ret < 0) {
1261 +               del_mtd_partitions(mtd);
1262 +               map_destroy(mtd);
1263 +       }
1264 +#ifdef CONFIG_SL2312_SHARE_PIN
1265 +    sl2312flash_disable_parallel_flash();      /* disable Parallel FLASH */
1266 +#endif
1267 +    printk("SL2312 MTD Driver Init Success ......\n");
1268 +       return ret;
1269 +}
1270 +
1271 +static void __exit sl2312flash_exit(void)
1272 +{
1273 +       if (mtd) {
1274 +               del_mtd_partitions(mtd);
1275 +               map_destroy(mtd);
1276 +       }
1277 +
1278 +       if (sl2312flash_map.virt) {
1279 +           iounmap((void *)sl2312flash_map.virt);
1280 +           sl2312flash_map.virt = 0;
1281 +       }
1282 +}
1283 +
1284 +char chrtohex(char c)
1285 +{
1286 +  char val;
1287 +  if ((c >= '0') && (c <= '9'))
1288 +  {
1289 +    val = c - '0';
1290 +    return val;
1291 +  }
1292 +  else if ((c >= 'a') && (c <= 'f'))
1293 +  {
1294 +    val = 10 + (c - 'a');
1295 +    return val;
1296 +  }
1297 +  else if ((c >= 'A') && (c <= 'F'))
1298 +  {
1299 +    val = 10 + (c - 'A');
1300 +    return val;
1301 +  }
1302 +  printk("<1>Error number\n");
1303 +  return 0;
1304 +}
1305 +
1306 +
1307 +int get_vlaninfo(vlaninfo* vlan)
1308 +{
1309 +       vctl_mheader head;
1310 +       vctl_entry entry;
1311 +       struct mtd_info *mymtd=NULL;
1312 +       int i, j, loc = 0;
1313 +       char *payload=0, *tmp1, *tmp2, tmp3[9];
1314 +       size_t retlen;
1315 +
1316 +       #ifdef CONFIG_SL2312_SHARE_PIN
1317 +       sl2312flash_enable_parallel_flash();
1318 +       #endif
1319 +       for(i=0;i<MAX_MTD_DEVICES;i++)
1320 +       {
1321 +               mymtd=get_mtd_device(NULL,i);
1322 +               //    printk("mymtd->name: %s\n", mymtd->name);
1323 +               if(mymtd && !strcmp(mymtd->name,"VCTL"))
1324 +               {
1325 +                       //      printk("%s\n", mymtd->name);
1326 +                       break;
1327 +               }
1328 +       }
1329 +       if( i >= MAX_MTD_DEVICES)
1330 +       {
1331 +               printk("Can't find version control\n");
1332 +               #ifdef CONFIG_SL2312_SHARE_PIN
1333 +               sl2312flash_disable_parallel_flash();
1334 +               #endif
1335 +               return 0;
1336 +       }
1337 +
1338 +       if (!mymtd | !mymtd->read)
1339 +       {
1340 +               printk("<1>Can't read Version Configuration\n");
1341 +               #ifdef CONFIG_SL2312_SHARE_PIN
1342 +               sl2312flash_disable_parallel_flash();
1343 +               #endif
1344 +               return 0;
1345 +       }
1346 +
1347 +       mymtd->read(mymtd, 0, VCTL_HEAD_SIZE, &retlen, (u_char*)&head);
1348 +       //  printk("entry header: %c%c%c%c\n", head.header[0], head.header[1], head.header[2], head.header[3]);
1349 +       //  printk("entry number: %x\n", head.entry_num);
1350 +       if ( strncmp(head.header, "FLFM", 4) )
1351 +       {
1352 +               printk("VCTL is a erase block\n");
1353 +               #ifdef CONFIG_SL2312_SHARE_PIN
1354 +               sl2312flash_disable_parallel_flash();
1355 +               #endif
1356 +               return 0;
1357 +       }
1358 +       loc += retlen;
1359 +       for (i = 0; i < head.entry_num; i++)
1360 +       {
1361 +               mymtd->read(mymtd, loc, VCTL_ENTRY_LEN, &retlen, (u_char*)&entry);
1362 +               //    printk("type: %x\n", entry.type);
1363 +               //    printk("size: %x\n", entry.size);
1364 +               strncpy(tmp3, entry.header, 4);
1365 +               if (entry.type == VCT_VLAN)
1366 +               {
1367 +                       for (j = 0; j < 6 ; j++)
1368 +                       {
1369 +                               vlan[0].mac[j] = 0;
1370 +                               vlan[1].mac[j] = 0;
1371 +                       }
1372 +                       vlan[0].vlanid = 1;
1373 +                       vlan[1].vlanid = 2;
1374 +                       vlan[0].vlanmap = 0x7F;
1375 +                       vlan[1].vlanmap = 0x80;
1376 +
1377 +                       payload = (char *)kmalloc(entry.size - VCTL_ENTRY_LEN, GFP_KERNEL);
1378 +                       loc += VCTL_ENTRY_LEN;
1379 +                       mymtd->read(mymtd, loc, entry.size - VCTL_ENTRY_LEN, &retlen, payload);
1380 +                       //      printk("%s\n", payload);
1381 +                       tmp1 = strstr(payload, "MAC1:");
1382 +                       tmp2 = strstr(payload, "MAC2:");
1383 +                       if(!tmp1||!tmp2){
1384 +                               kfree(payload);
1385 +                               #ifdef CONFIG_SL2312_SHARE_PIN
1386 +                               sl2312flash_disable_parallel_flash();
1387 +                               #endif
1388 +                               printk("Error VCTL format!!\n");
1389 +                               return 0;
1390 +                       }
1391 +                       tmp1 += 7;
1392 +                       tmp2 += 7;
1393 +
1394 +
1395 +                       for (j = 0; j < 6; j++)
1396 +                       {
1397 +                               vlan[0].mac[j] = chrtohex(tmp1[2*j])*16 + chrtohex(tmp1[(2*j)+1]);
1398 +                               vlan[1].mac[j] = chrtohex(tmp2[2*j])*16 + chrtohex(tmp2[(2*j)+1]);
1399 +                       }
1400 +                       tmp1 = strstr(payload, "ID1:");
1401 +                       tmp2 = strstr(payload, "ID2:");
1402 +                       tmp1 += 4;
1403 +                       tmp2 += 4;
1404 +                       vlan[0].vlanid = tmp1[0] - '0';
1405 +                       vlan[1].vlanid = tmp2[0] - '0';
1406 +                       tmp1 = strstr(payload, "MAP1:");
1407 +                       tmp2 = strstr(payload, "MAP2:");
1408 +                       tmp1 += 7;
1409 +                       tmp2 += 7;
1410 +                       vlan[0].vlanmap = chrtohex(tmp1[0]) * 16 + chrtohex(tmp1[1]);
1411 +                       vlan[1].vlanmap = chrtohex(tmp2[0]) * 16 + chrtohex(tmp2[1]);
1412 +                       //  printk("Vlan1 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[0].vlanid, vlan[0].vlanmap, vlan[0].mac[0], vlan[0].mac[1], vlan[0].mac[2], vlan[0].mac[3], vlan[0].mac[4], vlan[0].mac[5]);
1413 +                       //  printk("Vlan2 id:%x map:%02x mac:%x%x%x%x%x%x\n", vlan[1].vlanid, vlan[1].vlanmap, vlan[1].mac[0], vlan[1].mac[1], vlan[1].mac[2], vlan[1].mac[3], vlan[1].mac[4], vlan[1].mac[5]);
1414 +                       break;
1415 +               }
1416 +               loc += entry.size;
1417 +       }
1418 +       if ( entry.type == VCT_VLAN )
1419 +       {
1420 +               #ifdef CONFIG_SL2312_SHARE_PIN
1421 +               sl2312flash_disable_parallel_flash();
1422 +               #endif
1423 +               kfree(payload);
1424 +               return 1;
1425 +       }
1426 +       if (i >= head.entry_num)
1427 +       printk("Can't find vlan information\n");
1428 +       #ifdef CONFIG_SL2312_SHARE_PIN
1429 +       sl2312flash_disable_parallel_flash();
1430 +       #endif
1431 +       return 0;
1432 +}
1433 +
1434 +EXPORT_SYMBOL(get_vlaninfo);
1435 +
1436 +
1437 +module_init(sl2312flash_init);
1438 +module_exit(sl2312flash_exit);
1439 +
1440 +MODULE_AUTHOR("Storlink Ltd");
1441 +MODULE_DESCRIPTION("CFI map driver");
1442 +MODULE_LICENSE("GPL");
1443 --- /dev/null
1444 +++ b/drivers/mtd/maps/sl2312-flash-m25p80.c
1445 @@ -0,0 +1,498 @@
1446 +/*
1447 + * $Id: sl2312-flash-m25p80.c,v 1.2 2006/06/02 08:46:02 middle Exp $
1448 + *
1449 + * Flash and EPROM on Hitachi Solution Engine and similar boards.
1450 + *
1451 + * (C) 2001 Red Hat, Inc.
1452 + *
1453 + * GPL'd
1454 + */
1455 +
1456 +#include <linux/module.h>
1457 +#include <linux/types.h>
1458 +#include <linux/kernel.h>
1459 +
1460 +#include <asm/io.h>
1461 +#include <linux/mtd/mtd.h>
1462 +#include <linux/mtd/map.h>
1463 +#include <linux/mtd/partitions.h>
1464 +#include <asm/hardware.h>
1465 +
1466 +#include <asm/arch/sl2312.h>
1467 +#include <asm/arch/flash.h>
1468 +#include <linux/init.h> //add
1469 +#define  g_chipen     SERIAL_FLASH_CHIP0_EN   //ST
1470 +
1471 +//static int m25p80_page_program(__u32 address, __u8 data, __u32 schip_en);
1472 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en);
1473 +extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
1474 +
1475 +
1476 +static __u32 read_flash_ctrl_reg(__u32 ofs)
1477 +{
1478 +    __u32 *base;
1479 +
1480 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1481 +    return __raw_readl(base);
1482 +}
1483 +
1484 +static void write_flash_ctrl_reg(__u32 ofs,__u32 data)
1485 +{
1486 +    __u32 *base;
1487 +
1488 +    base = (__u32 *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE + ofs));
1489 +    __raw_writel(data, base);
1490 +}
1491 +
1492 +static void m25p80_read(__u32 address, __u8 *data, __u32 schip_en)
1493 +{
1494 +      __u32 opcode,status;
1495 +      __u32 value;
1496 +
1497 +      //opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ;
1498 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_READ;
1499 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1500 +
1501 +       opcode|=g_chipen;
1502 +
1503 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1504 +      status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1505 +      while(status&0x80000000)
1506 +      {
1507 +          status=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1508 +          flash_delay();
1509 +          schedule();
1510 +      }
1511 +
1512 +      value=read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1513 +      *data = value & 0xff;
1514 +}
1515 +
1516 +static int m25p80_page_program(__u32 address, __u8 *data, __u32 schip_en)
1517 +{
1518 +      __u32 opcode;
1519 +      __u32  status;
1520 +         __u32 tmp;
1521 +         int res = FLASH_ERR_OK;
1522 +         //volatile FLASH_DATA_T* data_ptr = (volatile FLASH_DATA_T*) data;
1523 +         opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1524 +
1525 +             opcode|=g_chipen;
1526 +
1527 +          write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1528 +          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1529 +                       while(tmp&0x80000000)
1530 +                       {
1531 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1532 +                           flash_delay();
1533 +                           schedule();
1534 +                       }
1535 +          //middle delay_ms(130);
1536 +          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1537 +          if((status&0x02)==0x02)
1538 +         {
1539 +              //middle delay_ms(100);
1540 +               m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1541 +          }
1542 +
1543 +
1544 +      m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1545 +      ////middle delay_ms(10);
1546 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA | M25P80_PAGE_PROGRAM;
1547 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1548 +      write_flash_ctrl_reg(FLASH_WRITE_DATA_OFFSET, *data);
1549 +
1550 +      //status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1551 +      //while(status!=data)
1552 +      //{
1553 +      //    status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1554 +      //    //middle delay_ms(10);
1555 +      //}
1556 +
1557 +       opcode|=g_chipen;
1558 +
1559 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1560 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1561 +                       while(tmp&0x80000000)
1562 +                       {
1563 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1564 +                           flash_delay();
1565 +                           schedule();
1566 +                       }
1567 +      //opcode=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1568 +
1569 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1570 +
1571 +       opcode|=g_chipen;
1572 +
1573 +
1574 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1575 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1576 +                       while(tmp&0x80000000)
1577 +                       {
1578 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1579 +                           flash_delay();
1580 +                           schedule();
1581 +                       }
1582 +      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1583 +      //while(status&0xfd)
1584 +      while(status&0x01)
1585 +      {
1586 +         //if((status&0x9c)!=0)
1587 +         //    printf("  m25p80_page_program   Protect Status = %x\n",status);
1588 +         write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1589 +         tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1590 +                       while(tmp&0x80000000)
1591 +                       {
1592 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1593 +                           flash_delay();
1594 +                           schedule();
1595 +                       }
1596 +          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1597 +          flash_delay();
1598 +          schedule();
1599 +          //middle delay_ms(50);
1600 +      }
1601 +      //printf("status = %x, data = %x\n",status,data);
1602 +      if((status&0x02)==0x02)
1603 +      {
1604 +         //middle delay_ms(100);
1605 +          m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1606 +      }
1607 +    //};//while (len > 0)
1608 +    return res;
1609 +}
1610 +
1611 +void m25p80_copy_from(struct map_info *map, void *buf, unsigned long ofs, ssize_t len)
1612 +{
1613 +//     __u32 size;
1614 +     __u8  *buffer;
1615 +     __u32 length;//i, j,
1616 +
1617 +       length = len;
1618 +     buffer = (__u8 *)buf;
1619 +     while(len)
1620 +     {
1621 +        m25p80_read(ofs, buffer, g_chipen);
1622 +        buffer++;
1623 +        ofs++;
1624 +        len --;
1625 +     } ;
1626 +
1627 +}
1628 +
1629 +__u32 m25p80_read32(struct map_info *map, unsigned long ofs)
1630 +{
1631 +
1632 +      return read_flash_ctrl_reg(ofs);
1633 +
1634 +
1635 +}
1636 +
1637 +void m25p80_write32(struct map_info *map, __u32 d, unsigned long ofs)
1638 +{
1639 +
1640 +      write_flash_ctrl_reg(ofs, d);
1641 +
1642 +}
1643 +
1644 +void m25p80_copy_to(struct map_info *map, unsigned long ofs, void *buf, ssize_t len)
1645 +{
1646 +     __u32 size, i, ret;
1647 +
1648 +     while(len > 0)
1649 +     {
1650 +        if(len >= M25P80_PAGE_SIZE)
1651 +                       size = M25P80_PAGE_SIZE;
1652 +               else
1653 +                       size = len;
1654 +
1655 +        for(i=0;i<size;i++)
1656 +           {
1657 +               ret = m25p80_page_program( (ofs+i),  (buf+i),  g_chipen);
1658 +           }
1659 +        buf+=M25P80_PAGE_SIZE;
1660 +        ofs+=M25P80_PAGE_SIZE;
1661 +               len-=M25P80_PAGE_SIZE;
1662 +
1663 +    };
1664 +
1665 +
1666 +}
1667 +
1668 +static struct mtd_info *serial_mtd;
1669 +
1670 +static struct mtd_partition *parsed_parts;
1671 +
1672 +static struct map_info m25p80_map = {
1673 +
1674 +       .name = "SL2312 serial flash m25p80",
1675 +       .size = 1048576, //0x100000,
1676 +               //buswidth: 4,
1677 +       .bankwidth = 4,
1678 +       .phys =          SL2312_FLASH_BASE,
1679 +#ifdef CONFIG_MTD_COMPLEX_MAPPINGS
1680 +       .copy_from = m25p80_copy_from,
1681 +       .read = m25p80_read32,
1682 +       .write = m25p80_write32,
1683 +       .copy_to = m25p80_copy_to
1684 +#endif
1685 +};
1686 +
1687 +
1688 +
1689 +static struct mtd_partition m25p80_partitions[] = {
1690 +
1691 +       /* boot code */
1692 +       { .name = "bootloader", .offset = 0x00000000, .size = 0x20000, },
1693 +       /* kernel image */
1694 +       { .name = "kerel image", .offset = 0x000020000, .size = 0xC0000 },
1695 +       /* All else is writable (e.g. JFFS) */
1696 +       { .name = "user data", .offset = 0x000E0000, .size = 0x00010000, },
1697 +
1698 +
1699 +};
1700 +
1701 +void flash_delay()
1702 +{
1703 +       int i,j;
1704 +       for(i=0;i<0x100;i++)
1705 +               j=i*3+5;
1706 +}
1707 +
1708 +int m25p80_sector_erase(__u32 address, __u32 schip_en)
1709 +{
1710 +      __u32 opcode;
1711 +      __u32  status;
1712 +      __u32 tmp;
1713 +      int res = FLASH_ERR_OK;
1714 +       //printf("\n-->m25p80_sector_erase");
1715 +       if(address >= FLASH_START)
1716 +               address-=FLASH_START;
1717 +
1718 +      m25p80_write_cmd(M25P80_WRITE_ENABLE, schip_en);
1719 +      //printf("\n     m25p80_sector_erase : after we-en");
1720 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_SHIFT_ADDRESS | M25P80_SECTOR_ERASE;
1721 +      write_flash_ctrl_reg(FLASH_ADDRESS_OFFSET, address);
1722 +      #ifdef MIDWAY_DIAG
1723 +       opcode|=schip_en;
1724 +      #endif
1725 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1726 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1727 +                       while(tmp&0x80000000)
1728 +                       {
1729 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1730 +                           flash_delay();
1731 +                           schedule();
1732 +                       }
1733 +
1734 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1735 +      #ifdef MIDWAY_DIAG
1736 +       opcode|=schip_en;
1737 +      #endif
1738 +
1739 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1740 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1741 +                       while(tmp&0x80000000)
1742 +                       {
1743 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1744 +                           flash_delay();
1745 +                           schedule();
1746 +                       }
1747 +      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1748 +      //while(status&0xfd)
1749 +      while(status&0x01)
1750 +      {
1751 +         //if((status&0x9c)!=0)
1752 +         //    printf("  m25p80_sector_erase   Protect Status = %x\n",status);
1753 +         write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1754 +         tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1755 +                       while(tmp&0x80000000)
1756 +                       {
1757 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1758 +                           flash_delay();
1759 +                           schedule();
1760 +                       }
1761 +          status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1762 +          flash_delay();
1763 +          schedule();
1764 +          //middle delay_ms(50);
1765 +      }
1766 +      if((status&0x02)==0x02)
1767 +      {
1768 +         //middle delay_ms(100);
1769 +          m25p80_write_cmd(M25P80_WRITE_DISABLE, schip_en);
1770 +      }
1771 +      //printf("\n<--m25p80_sector_erase");
1772 +      return res;
1773 +}
1774 +
1775 +static void m25p80_write_cmd(__u8 cmd, __u32 schip_en)
1776 +{
1777 +      __u32 opcode,tmp;
1778 +      __u32  status;
1779 +
1780 +
1781 +
1782 +
1783 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE | cmd;
1784 +
1785 +       opcode|=g_chipen;
1786 +
1787 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1788 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1789 +      while(tmp&0x80000000)
1790 +      {
1791 +          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1792 +          flash_delay();
1793 +          schedule();
1794 +      }
1795 +      //////
1796 +      opcode = 0x80000000 | FLASH_ACCESS_ACTION_OPCODE_DATA | M25P80_READ_STATUS;
1797 +
1798 +       opcode|=g_chipen;
1799 +
1800 +      write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1801 +      tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1802 +      while(tmp&0x80000000)
1803 +      {
1804 +          tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1805 +          flash_delay();
1806 +          schedule();
1807 +      }
1808 +      //middle delay_ms(130);
1809 +      status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1810 +      //printf("\ncmd =%x  status = %x",cmd,status);
1811 +      if(cmd==M25P80_WRITE_ENABLE)
1812 +      {
1813 +       //printf("\n**-->enable**  status = %x",status);
1814 +       //middle delay_ms(100);
1815 +          while((status&0x03) != 2)
1816 +          {
1817 +               //if((status&0x9c)!=0)
1818 +               //    printf("  M25P80_WRITE_ENABLE   Protect Status = %x\n",status);
1819 +
1820 +                 write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1821 +                 tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1822 +                       while(tmp&0x80000000)
1823 +                       {
1824 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1825 +                           //flash_delay();
1826 +                       }
1827 +              status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1828 +              //printf("\n**enable**  status = %x",status);
1829 +              flash_delay();
1830 +              schedule();
1831 +              //middle delay_ms(100);
1832 +          }
1833 +      }
1834 +      else if(cmd==M25P80_WRITE_DISABLE)
1835 +      {
1836 +          //while((status&0x03) == 2)
1837 +          //   printf("\n**disable**  status = %x",status);
1838 +          //middle delay_ms(100);
1839 +          while((status&0x03) != 0)
1840 +          {
1841 +              //m25p80_write_status((status&0xfd),schip_en);
1842 +              write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1843 +              tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1844 +               while(tmp&0x80000000)
1845 +               {
1846 +                   tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1847 +                   flash_delay();
1848 +                   schedule();
1849 +               }
1850 +              status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1851 +              //printf("\n**disable**  status = %x",status);
1852 +              flash_delay();
1853 +              schedule();
1854 +              //middle delay_ms(50);
1855 +          }
1856 +      }
1857 +      else
1858 +      {
1859 +          //while((status&0x01) !=0)
1860 +          while((status&0x01) !=0)
1861 +          {
1862 +                 write_flash_ctrl_reg(FLASH_ACCESS_OFFSET, opcode);
1863 +                 tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1864 +                       while(tmp&0x80000000)
1865 +                       {
1866 +                           tmp=read_flash_ctrl_reg(FLASH_ACCESS_OFFSET);
1867 +                           flash_delay();
1868 +                           schedule();
1869 +                       }
1870 +              status = read_flash_ctrl_reg(FLASH_READ_DATA_OFFSET);
1871 +              flash_delay();
1872 +              schedule();
1873 +              //middle delay_ms(50);
1874 +          }
1875 +      }
1876 +      //////
1877 +
1878 +      //printf("\n<--  status = %x",status);
1879 +}
1880 +
1881 +static int __init init_sl2312_m25p80(void)
1882 +{
1883 +       int nr_parts = 0;
1884 +       struct mtd_partition *parts;
1885 +
1886 +       serial_mtd = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
1887 +       if (!serial_mtd)
1888 +               return NULL;
1889 +
1890 +       memset(serial_mtd, 0, sizeof(struct mtd_info));
1891 +       m25p80_map.virt = (unsigned long)ioremap(SL2312_FLASH_BASE, SFLASH_SIZE);//(unsigned long)ioremap(FLASH_START, SFLASH_SIZE);
1892 +    if (!m25p80_map.virt) {
1893 +               printk(" failed to ioremap \n");
1894 +               return -EIO;
1895 +       }
1896 +       serial_mtd = do_map_probe("map_serial", &m25p80_map);
1897 +       if (serial_mtd) {
1898 +               serial_mtd->owner = THIS_MODULE;
1899 +
1900 +       }
1901 +
1902 +#ifdef CONFIG_MTD_REDBOOT_PARTS
1903 +       nr_parts = parse_redboot_partitions(serial_mtd, &parsed_parts);
1904 +       if (nr_parts > 0)
1905 +               printk(KERN_NOTICE "Found RedBoot partition table.\n");
1906 +       else if (nr_parts < 0)
1907 +               printk(KERN_NOTICE "Error looking for RedBoot partitions.\n");
1908 +#else
1909 +       parsed_parts = m25p80_partitions;
1910 +       parts = m25p80_partitions;
1911 +       nr_parts = sizeof(m25p80_partitions)/sizeof(*parts);
1912 +       nr_parts = sizeof(m25p80_partitions)/sizeof(*parsed_parts);
1913 +#endif /* CONFIG_MTD_REDBOOT_PARTS */
1914 +
1915 +       if (nr_parts > 0)
1916 +           add_mtd_partitions(serial_mtd, parsed_parts, nr_parts);
1917 +       else
1918 +           add_mtd_device(serial_mtd);
1919 +
1920 +       return 0;
1921 +}
1922 +
1923 +static void __exit cleanup_sl2312_m25p80(void)
1924 +{
1925 +       if (parsed_parts)
1926 +           del_mtd_partitions(serial_mtd);
1927 +       else
1928 +           del_mtd_device(serial_mtd);
1929 +
1930 +       map_destroy(serial_mtd);
1931 +
1932 +
1933 +}
1934 +
1935 +module_init(init_sl2312_m25p80);
1936 +module_exit(cleanup_sl2312_m25p80);
1937 +
1938 +
1939 +
1940 +MODULE_LICENSE("GPL");
1941 +MODULE_AUTHOR("Plus Chen <plus@storlink.com.tw>");
1942 +MODULE_DESCRIPTION("MTD map driver for Storlink Sword boards");
1943 +
1944 --- /dev/null
1945 +++ b/drivers/mtd/maps/sl2312_flashmap.h
1946 @@ -0,0 +1,21 @@
1947 +/*
1948 + * Please note that the name are used in mkflash script. Therefore
1949 + * don't change them.  If you want to add different partitions, you
1950 + * will need to modify mkflash script as well so that the end image
1951 + * is what you include here!
1952 + *
1953 + * Also, the 7th item is always the size, so please don't add extra
1954 + * spaces in the name or other items.
1955 + *
1956 + *  - Alan
1957 + */
1958 +
1959 +static struct mtd_partition sl2312_partitions[] = {
1960 +       { name: "RedBoot",       offset: 0x00000000, size: 0x00020000, },
1961 +       { name: "kernel",        offset: 0x00020000, size: 0x00100000, },
1962 +       { name: "rootfs",        offset: 0x00120000, size: 0x00500000, },
1963 +       { name: "rootfs_data",   offset: 0x00620000, size: 0x001A0000, },
1964 +       { name: "VCTL",          offset: 0x007C0000, size: 0x00010000, },
1965 +       { name: "cfg",           offset: 0x007D0000, size: 0x00020000, },
1966 +       { name: "FIS directory", offset: 0x007F0000, size: 0x00010000, }
1967 +};
1968 --- /dev/null
1969 +++ b/drivers/mtd/maps/sl2312_flashmap.h.16MB
1970 @@ -0,0 +1,21 @@
1971 +/*
1972 + * Please note that the name are used in mkflash script. Therefore
1973 + * don't change them.  If you want to add different partitions, you
1974 + * will need to modify mkflash script as well so that the end image
1975 + * is what you include here!
1976 + *
1977 + * Also, the 7th item is always the size, so please don't add extra
1978 + * spaces in the name or other items.
1979 + *
1980 + *  - Alan
1981 + */
1982 +
1983 +static struct mtd_partition sl2312_partitions[] = {
1984 +       { name: "RedBoot",       offset: 0x00000000, size: 0x00020000, },
1985 +       { name: "Kernel",        offset: 0x00020000, size: 0x00300000, },
1986 +       { name: "Ramdisk",       offset: 0x00320000, size: 0x00600000, },
1987 +       { name: "Application",   offset: 0x00920000, size: 0x00600000, },
1988 +       { name: "VCTL",          offset: 0x00F20000, size: 0x00020000, },
1989 +       { name: "CurConf",       offset: 0x00F40000, size: 0x000A0000, },
1990 +       { name: "FIS directory", offset: 0x00FE0000, size: 0x00020000, }
1991 +};
1992 --- /dev/null
1993 +++ b/drivers/mtd/maps/sl2312_flashmap.h.8MB
1994 @@ -0,0 +1,21 @@
1995 +/*
1996 + * Please note that the name are used in mkflash script. Therefore
1997 + * don't change them.  If you want to add different partitions, you
1998 + * will need to modify mkflash script as well so that the end image
1999 + * is what you include here!
2000 + *
2001 + * Also, the 7th item is always the size, so please don't add extra
2002 + * spaces in the name or other items.
2003 + *
2004 + *  - Alan
2005 + */
2006 +
2007 +static struct mtd_partition sl2312_partitions[] = {
2008 +       { name: "RedBoot",       offset: 0x00000000, size: 0x00020000, },
2009 +       { name: "Kernel",        offset: 0x00020000, size: 0x00200000, },
2010 +       { name: "Ramdisk",       offset: 0x00220000, size: 0x00280000, },
2011 +       { name: "Application",   offset: 0x004A0000, size: 0x00300000, },
2012 +       { name: "VCTL",          offset: 0x007A0000, size: 0x00020000, },
2013 +       { name: "CurConf",       offset: 0x007C0000, size: 0x00020000, },
2014 +       { name: "FIS directory", offset: 0x007E0000, size: 0x00020000, }
2015 +};
2016 --- a/drivers/mtd/mtdchar.c
2017 +++ b/drivers/mtd/mtdchar.c
2018 @@ -59,6 +59,77 @@
2019         enum mtd_file_modes mode;
2020  };
2021
2022 +/***********************************************************************
2023 +/*             Storlink SoC -- flash
2024 +/***********************************************************************/
2025 +#ifdef CONFIG_SL2312_SHARE_PIN
2026 +unsigned int share_pin_flag=0;         // bit0:FLASH, bit1:UART, bit2:EMAC, bit3-4:IDE
2027 +unsigned int check_sleep_flag=0;       // bit0:FLASH, bit1:IDE
2028 +static spinlock_t sl2312_flash_lock = SPIN_LOCK_UNLOCKED;
2029 +EXPORT_SYMBOL(share_pin_flag);
2030 +int dbg=0;
2031 +DECLARE_WAIT_QUEUE_HEAD(wq);
2032 +extern struct wait_queue_head_t *flash_wait;
2033 +unsigned int flash_req=0;
2034 +void mtd_lock()
2035 +{
2036 +       struct task_struct *tsk = current;
2037 +       unsigned int value ;
2038 +       unsigned long flags;
2039 +       flash_req = 1;
2040 +       DECLARE_WAITQUEUE(wait, tsk);
2041 +       add_wait_queue(&wq, &wait);
2042 +       for(;;)
2043 +       {
2044 +               set_task_state(tsk, TASK_INTERRUPTIBLE);
2045 +               spin_lock_irqsave(&sl2312_flash_lock,flags);
2046 +               if((share_pin_flag&0x1E)){//||(check_sleep_flag&0x00000002)) {
2047 +                       spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2048 +                       check_sleep_flag |= 0x00000001;
2049 +                       if(dbg)
2050 +                               printk("mtd yield %x %x\n",share_pin_flag,check_sleep_flag);
2051 +                       wake_up_interruptible(&flash_wait);
2052 +                       schedule();
2053 +               }
2054 +               else {
2055 +                       check_sleep_flag &= ~0x01;
2056 +                       share_pin_flag |= 0x00000001 ;                  // set share pin flag
2057 +                       spin_unlock_irqrestore(&sl2312_flash_lock, flags);
2058 +                       value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2059 +                       value = value & (~PFLASH_SHARE_BIT) ;
2060 +                       writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2061 +                       if(dbg)
2062 +                               printk("mtd Go %x %x\n",share_pin_flag,check_sleep_flag);
2063 +                       tsk->state = TASK_RUNNING;
2064 +                       remove_wait_queue(&wq, &wait);
2065 +                       return ;
2066 +               }
2067 +       }
2068 +}
2069 +
2070 +void mtd_unlock()
2071 +{
2072 +       unsigned int value ;
2073 +       unsigned long flags;
2074 +
2075 +       spin_lock_irqsave(&sl2312_flash_lock,flags);            // Disable IRQ
2076 +       value = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2077 +       value = value | PFLASH_SHARE_BIT ;                              // Disable Flash PADs
2078 +       writel(value,IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_MISC_REG)));
2079 +       share_pin_flag &= ~(0x00000001);                        // clear share pin flag
2080 +       check_sleep_flag &= ~0x00000001;
2081 +       spin_unlock_irqrestore(&sl2312_flash_lock, flags);      // Restore IRQ
2082 +       if (check_sleep_flag & 0x00000002)
2083 +       {
2084 +               check_sleep_flag &= ~(0x00000002);
2085 +               wake_up_interruptible(&flash_wait);
2086 +       }
2087 +       DEBUG(MTD_DEBUG_LEVEL0, "Flash Unlock...\n");
2088 +       flash_req = 0;
2089 +}
2090 +#endif
2091 +/***********************************************************************/
2092 +
2093  static loff_t mtd_lseek (struct file *file, loff_t offset, int orig)
2094  {
2095         struct mtd_file_info *mfi = file->private_data;
2096 @@ -162,13 +233,21 @@
2097         int len;
2098         char *kbuf;
2099
2100 +#ifdef CONFIG_SL2312_SHARE_PIN
2101 +       mtd_lock();                             // sl2312 share pin lock
2102 +#endif
2103 +
2104         DEBUG(MTD_DEBUG_LEVEL0,"MTD_read\n");
2105
2106         if (*ppos + count > mtd->size)
2107                 count = mtd->size - *ppos;
2108
2109 -       if (!count)
2110 +       if (!count){
2111 +#ifdef CONFIG_SL2312_SHARE_PIN
2112 +       mtd_unlock();                           // sl2312 share pin lock
2113 +#endif
2114                 return 0;
2115 +       }
2116
2117         /* FIXME: Use kiovec in 2.5 to lock down the user's buffers
2118            and pass them directly to the MTD functions */
2119 @@ -178,8 +257,12 @@
2120         else
2121                 kbuf=kmalloc(count, GFP_KERNEL);
2122
2123 -       if (!kbuf)
2124 +       if (!kbuf) {
2125 +#ifdef CONFIG_SL2312_SHARE_PIN
2126 +       mtd_unlock();                           // sl2312 share pin lock
2127 +#endif
2128                 return -ENOMEM;
2129 +       }
2130
2131         while (count) {
2132
2133 @@ -224,6 +307,9 @@
2134                         *ppos += retlen;
2135                         if (copy_to_user(buf, kbuf, retlen)) {
2136                                 kfree(kbuf);
2137 +#ifdef CONFIG_SL2312_SHARE_PIN
2138 +                               mtd_unlock();                           // sl2312 share pin lock
2139 +#endif
2140                                 return -EFAULT;
2141                         }
2142                         else
2143 @@ -235,13 +321,19 @@
2144                                 count = 0;
2145                 }
2146                 else {
2147 -                       kfree(kbuf);
2148 +                       kfree(kbuf);
2149 +#ifdef CONFIG_SL2312_SHARE_PIN
2150 +                       mtd_unlock();                           // sl2312 share pin lock
2151 +#endif
2152                         return ret;
2153                 }
2154
2155         }
2156
2157         kfree(kbuf);
2158 +#ifdef CONFIG_SL2312_SHARE_PIN
2159 +       mtd_unlock();                           // sl2312 share pin lock
2160 +#endif
2161         return total_retlen;
2162  } /* mtd_read */
2163
2164 @@ -255,24 +347,40 @@
2165         int ret=0;
2166         int len;
2167
2168 +#ifdef CONFIG_SL2312_SHARE_PIN
2169 +       mtd_lock();                             // sl2312 share pin lock
2170 +#endif
2171 +
2172         DEBUG(MTD_DEBUG_LEVEL0,"MTD_write\n");
2173
2174 -       if (*ppos == mtd->size)
2175 +       if (*ppos == mtd->size){
2176 +#ifdef CONFIG_SL2312_SHARE_PIN
2177 +       mtd_unlock();                           // sl2312 share pin lock
2178 +#endif
2179                 return -ENOSPC;
2180 +       }
2181
2182         if (*ppos + count > mtd->size)
2183                 count = mtd->size - *ppos;
2184
2185 -       if (!count)
2186 +       if (!count){
2187 +#ifdef CONFIG_SL2312_SHARE_PIN
2188 +       mtd_unlock();                           // sl2312 share pin lock
2189 +#endif
2190                 return 0;
2191 +       }
2192
2193         if (count > MAX_KMALLOC_SIZE)
2194                 kbuf=kmalloc(MAX_KMALLOC_SIZE, GFP_KERNEL);
2195         else
2196                 kbuf=kmalloc(count, GFP_KERNEL);
2197
2198 -       if (!kbuf)
2199 +       if (!kbuf) {
2200 +#ifdef CONFIG_SL2312_SHARE_PIN
2201 +               mtd_unlock();                           // sl2312 share pin lock
2202 +#endif
2203                 return -ENOMEM;
2204 +       }
2205
2206         while (count) {
2207
2208 @@ -283,6 +391,9 @@
2209
2210                 if (copy_from_user(kbuf, buf, len)) {
2211                         kfree(kbuf);
2212 +#ifdef CONFIG_SL2312_SHARE_PIN
2213 +                       mtd_unlock();                           // sl2312 share pin lock
2214 +#endif
2215                         return -EFAULT;
2216                 }
2217
2218 @@ -323,11 +434,17 @@
2219                 }
2220                 else {
2221                         kfree(kbuf);
2222 +#ifdef CONFIG_SL2312_SHARE_PIN
2223 +                       mtd_unlock();                           // sl2312 share pin lock
2224 +#endif
2225                         return ret;
2226                 }
2227         }
2228
2229         kfree(kbuf);
2230 +#ifdef CONFIG_SL2312_SHARE_PIN
2231 +       mtd_unlock();                           // sl2312 share pin lock
2232 +#endif
2233         return total_retlen;
2234  } /* mtd_write */
2235
2236 @@ -381,36 +498,67 @@
2237         u_long size;
2238         struct mtd_info_user info;
2239
2240 +#ifdef CONFIG_SL2312_SHARE_PIN
2241 +       mtd_lock();                             // sl2312 share pin lock
2242 +#endif
2243 +
2244         DEBUG(MTD_DEBUG_LEVEL0, "MTD_ioctl\n");
2245
2246         size = (cmd & IOCSIZE_MASK) >> IOCSIZE_SHIFT;
2247         if (cmd & IOC_IN) {
2248                 if (!access_ok(VERIFY_READ, argp, size))
2249 +               {
2250 +#ifdef CONFIG_SL2312_SHARE_PIN
2251 +                       mtd_unlock();                           // sl2312 share pin lock
2252 +#endif
2253                         return -EFAULT;
2254 +               }
2255         }
2256         if (cmd & IOC_OUT) {
2257                 if (!access_ok(VERIFY_WRITE, argp, size))
2258 +               {
2259 +#ifdef CONFIG_SL2312_SHARE_PIN
2260 +                       mtd_unlock();                           // sl2312 share pin lock
2261 +#endif
2262                         return -EFAULT;
2263 +               }
2264         }
2265
2266         switch (cmd) {
2267         case MEMGETREGIONCOUNT:
2268                 if (copy_to_user(argp, &(mtd->numeraseregions), sizeof(int)))
2269 +               {
2270 +#ifdef CONFIG_SL2312_SHARE_PIN
2271 +                       mtd_unlock();                           // sl2312 share pin lock
2272 +#endif
2273                         return -EFAULT;
2274 +               }
2275                 break;
2276
2277         case MEMGETREGIONINFO:
2278         {
2279                 struct region_info_user ur;
2280
2281 -               if (copy_from_user(&ur, argp, sizeof(struct region_info_user)))
2282 +               if (copy_from_user(&ur, argp, sizeof(struct region_info_user))) {
2283 +#ifdef CONFIG_SL2312_SHARE_PIN
2284 +                       mtd_unlock();                           // sl2312 share pin lock
2285 +#endif
2286                         return -EFAULT;
2287 +               }
2288
2289 -               if (ur.regionindex >= mtd->numeraseregions)
2290 +               if (ur.regionindex >= mtd->numeraseregions) {
2291 +#ifdef CONFIG_SL2312_SHARE_PIN
2292 +                       mtd_unlock();                           // sl2312 share pin lock
2293 +#endif
2294                         return -EINVAL;
2295 +               }
2296                 if (copy_to_user(argp, &(mtd->eraseregions[ur.regionindex]),
2297 -                               sizeof(struct mtd_erase_region_info)))
2298 +                               sizeof(struct mtd_erase_region_info))) {
2299 +#ifdef CONFIG_SL2312_SHARE_PIN
2300 +                       mtd_unlock();                           // sl2312 share pin lock
2301 +#endif
2302                         return -EFAULT;
2303 +               }
2304                 break;
2305         }
2306
2307 @@ -433,7 +581,12 @@
2308                 struct erase_info *erase;
2309
2310                 if(!(file->f_mode & 2))
2311 +               {
2312 +#ifdef CONFIG_SL2312_SHARE_PIN
2313 +                       mtd_unlock();                           // sl2312 share pin lock
2314 +#endif
2315                         return -EPERM;
2316 +               }
2317
2318                 erase=kzalloc(sizeof(struct erase_info),GFP_KERNEL);
2319                 if (!erase)
2320 @@ -447,6 +600,9 @@
2321                         if (copy_from_user(&erase->addr, argp,
2322                                     sizeof(struct erase_info_user))) {
2323                                 kfree(erase);
2324 +#ifdef CONFIG_SL2312_SHARE_PIN
2325 +                               mtd_unlock();                           // sl2312 share pin lock
2326 +#endif
2327                                 return -EFAULT;
2328                         }
2329                         erase->mtd = mtd;
2330 @@ -484,14 +640,26 @@
2331                 struct mtd_oob_buf buf;
2332                 struct mtd_oob_ops ops;
2333
2334 -               if(!(file->f_mode & 2))
2335 +               if(!(file->f_mode & 2)) {
2336 +#ifdef CONFIG_SL2312_SHARE_PIN
2337 +                       mtd_unlock();                           // sl2312 share pin lock
2338 +#endif
2339                         return -EPERM;
2340 +               }
2341
2342 -               if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2343 +               if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2344 +#ifdef CONFIG_SL2312_SHARE_PIN
2345 +                       mtd_unlock();                           // sl2312 share pin lock
2346 +#endif
2347                         return -EFAULT;
2348 +               }
2349
2350 -               if (buf.length > 4096)
2351 +               if (buf.length > 4096) {
2352 +#ifdef CONFIG_SL2312_SHARE_PIN
2353 +                       mtd_unlock();                           // sl2312 share pin lock
2354 +#endif
2355                         return -EINVAL;
2356 +               }
2357
2358                 if (!mtd->write_oob)
2359                         ret = -EOPNOTSUPP;
2360 @@ -499,8 +667,12 @@
2361                         ret = access_ok(VERIFY_READ, buf.ptr,
2362                                         buf.length) ? 0 : EFAULT;
2363
2364 -               if (ret)
2365 +               if (ret) {
2366 +#ifdef CONFIG_SL2312_SHARE_PIN
2367 +                       mtd_unlock();                           // sl2312 share pin lock
2368 +#endif
2369                         return ret;
2370 +               }
2371
2372                 ops.ooblen = buf.length;
2373                 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2374 @@ -536,19 +708,35 @@
2375                 struct mtd_oob_buf buf;
2376                 struct mtd_oob_ops ops;
2377
2378 -               if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf)))
2379 +               if (copy_from_user(&buf, argp, sizeof(struct mtd_oob_buf))) {
2380 +#ifdef CONFIG_SL2312_SHARE_PIN
2381 +                       mtd_unlock();                           // sl2312 share pin lock
2382 +#endif
2383                         return -EFAULT;
2384 +               }
2385
2386 -               if (buf.length > 4096)
2387 +               if (buf.length > 4096) {
2388 +#ifdef CONFIG_SL2312_SHARE_PIN
2389 +                       mtd_unlock();                           // sl2312 share pin lock
2390 +#endif
2391                         return -EINVAL;
2392 +               }
2393
2394 -               if (!mtd->read_oob)
2395 +               if (!mtd->read_oob) {
2396 +#ifdef CONFIG_SL2312_SHARE_PIN
2397 +                       mtd_unlock();                           // sl2312 share pin lock
2398 +#endif
2399                         ret = -EOPNOTSUPP;
2400 +               }
2401                 else
2402                         ret = access_ok(VERIFY_WRITE, buf.ptr,
2403                                         buf.length) ? 0 : -EFAULT;
2404 -               if (ret)
2405 +               if (ret) {
2406 +#ifdef CONFIG_SL2312_SHARE_PIN
2407 +                       mtd_unlock();                           // sl2312 share pin lock
2408 +#endif
2409                         return ret;
2410 +               }
2411
2412                 ops.ooblen = buf.length;
2413                 ops.ooboffs = buf.start & (mtd->oobsize - 1);
2414 @@ -580,7 +768,12 @@
2415                 struct erase_info_user info;
2416
2417                 if (copy_from_user(&info, argp, sizeof(info)))
2418 +               {
2419 +#ifdef CONFIG_SL2312_SHARE_PIN
2420 +                       mtd_unlock();                           // sl2312 share pin lock
2421 +#endif
2422                         return -EFAULT;
2423 +               }
2424
2425                 if (!mtd->lock)
2426                         ret = -EOPNOTSUPP;
2427 @@ -594,7 +787,12 @@
2428                 struct erase_info_user info;
2429
2430                 if (copy_from_user(&info, argp, sizeof(info)))
2431 +               {
2432 +#ifdef CONFIG_SL2312_SHARE_PIN
2433 +                       mtd_unlock();                           // sl2312 share pin lock
2434 +#endif
2435                         return -EFAULT;
2436 +               }
2437
2438                 if (!mtd->unlock)
2439                         ret = -EOPNOTSUPP;
2440 @@ -629,11 +827,21 @@
2441                 loff_t offs;
2442
2443                 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2444 +               {
2445 +#ifdef CONFIG_SL2312_SHARE_PIN
2446 +                       mtd_unlock();                           // sl2312 share pin lock
2447 +#endif
2448                         return -EFAULT;
2449 +               }
2450                 if (!mtd->block_isbad)
2451                         ret = -EOPNOTSUPP;
2452                 else
2453 +               {
2454 +#ifdef CONFIG_SL2312_SHARE_PIN
2455 +                       mtd_unlock();                           // sl2312 share pin lock
2456 +#endif
2457                         return mtd->block_isbad(mtd, offs);
2458 +               }
2459                 break;
2460         }
2461
2462 @@ -642,11 +850,21 @@
2463                 loff_t offs;
2464
2465                 if (copy_from_user(&offs, argp, sizeof(loff_t)))
2466 +               {
2467 +#ifdef CONFIG_SL2312_SHARE_PIN
2468 +                       mtd_unlock();                           // sl2312 share pin lock
2469 +#endif
2470                         return -EFAULT;
2471 +               }
2472                 if (!mtd->block_markbad)
2473                         ret = -EOPNOTSUPP;
2474                 else
2475 +               {
2476 +#ifdef CONFIG_SL2312_SHARE_PIN
2477 +                       mtd_unlock();                           // sl2312 share pin lock
2478 +#endif
2479                         return mtd->block_markbad(mtd, offs);
2480 +               }
2481                 break;
2482         }
2483
2484 @@ -654,8 +872,12 @@
2485         case OTPSELECT:
2486         {
2487                 int mode;
2488 -               if (copy_from_user(&mode, argp, sizeof(int)))
2489 +               if (copy_from_user(&mode, argp, sizeof(int))) {
2490 +#ifdef CONFIG_SL2312_SHARE_PIN
2491 +                       mtd_unlock();                           // sl2312 share pin lock
2492 +#endif
2493                         return -EFAULT;
2494 +               }
2495
2496                 mfi->mode = MTD_MODE_NORMAL;
2497
2498 @@ -670,7 +892,12 @@
2499         {
2500                 struct otp_info *buf = kmalloc(4096, GFP_KERNEL);
2501                 if (!buf)
2502 +               {
2503 +#ifdef CONFIG_SL2312_SHARE_PIN
2504 +                       mtd_unlock();                           // sl2312 share pin lock
2505 +#endif
2506                         return -ENOMEM;
2507 +               }
2508                 ret = -EOPNOTSUPP;
2509                 switch (mfi->mode) {
2510                 case MTD_MODE_OTP_FACTORY:
2511 @@ -701,12 +928,24 @@
2512         {
2513                 struct otp_info info;
2514
2515 -               if (mfi->mode != MTD_MODE_OTP_USER)
2516 +               if (mfi->mode != MTD_MODE_OTP_USER) {
2517 +#ifdef CONFIG_SL2312_SHARE_PIN
2518 +                       mtd_unlock();                           // sl2312 share pin lock
2519 +#endif
2520                         return -EINVAL;
2521 -               if (copy_from_user(&info, argp, sizeof(info)))
2522 +               }
2523 +               if (copy_from_user(&info, argp, sizeof(info))) {
2524 +#ifdef CONFIG_SL2312_SHARE_PIN
2525 +                       mtd_unlock();                           // sl2312 share pin lock
2526 +#endif
2527                         return -EFAULT;
2528 -               if (!mtd->lock_user_prot_reg)
2529 +               }
2530 +               if (!mtd->lock_user_prot_reg) {
2531 +#ifdef CONFIG_SL2312_SHARE_PIN
2532 +                       mtd_unlock();                           // sl2312 share pin lock
2533 +#endif
2534                         return -EOPNOTSUPP;
2535 +               }
2536                 ret = mtd->lock_user_prot_reg(mtd, info.start, info.length);
2537                 break;
2538         }
2539 @@ -742,8 +981,12 @@
2540                         break;
2541
2542                 case MTD_MODE_RAW:
2543 -                       if (!mtd->read_oob || !mtd->write_oob)
2544 +                       if (!mtd->read_oob || !mtd->write_oob) {
2545 +#ifdef CONFIG_SL2312_SHARE_PIN
2546 +                               mtd_unlock();                           // sl2312 share pin lock
2547 +#endif
2548                                 return -EOPNOTSUPP;
2549 +                       }
2550                         mfi->mode = arg;
2551
2552                 case MTD_MODE_NORMAL:
2553 @@ -766,6 +1009,10 @@
2554                 ret = -ENOTTY;
2555         }
2556
2557 +#ifdef CONFIG_SL2312_SHARE_PIN
2558 +       mtd_unlock();                           // sl2312 share pin lock
2559 +#endif
2560 +
2561         return ret;
2562  } /* memory_ioctl */
2563
2564 --- a/drivers/mtd/nand/Kconfig
2565 +++ b/drivers/mtd/nand/Kconfig
2566 @@ -44,6 +44,13 @@
2567           This enables the driver for the autronix autcpu12 board to
2568           access the SmartMediaCard.
2569
2570 +config MTD_NAND_SL2312
2571 +       tristate "NAND Flash device on Storlink board"
2572 +       depends on ARM && MTD_NAND && ARCH_SL2312
2573 +       help
2574 +         This enables the driver for the Storlink board to
2575 +         access the nand device.
2576 +
2577  config MTD_NAND_EDB7312
2578         tristate "Support for Cirrus Logic EBD7312 evaluation board"
2579         depends on ARCH_EDB7312
2580 --- /dev/null
2581 +++ b/drivers/mtd/nand/sl2312-flash-nand.c
2582 @@ -0,0 +1,2287 @@
2583 +/*
2584 + *  drivers/mtd/sl2312.c
2585 + *
2586 + * $Id: sl2312-flash-nand.c,v 1.5 2006/06/15 07:02:29 middle Exp $
2587 + *
2588 + * Copyright (C) 2001 Toshiba Corporation
2589 + *
2590 + * 2003 (c) MontaVista Software, Inc. This file is licensed under
2591 + * the terms of the GNU General Public License version 2. This program
2592 + * is licensed "as is" without any warranty of any kind, whether express
2593 + * or implied.
2594 + *
2595 + */
2596 +
2597 +#include <linux/slab.h>
2598 +#include <linux/init.h>
2599 +#include <linux/module.h>
2600 +#include <linux/mtd/mtd.h>
2601 +#include <linux/mtd/nand.h>
2602 +#include <linux/mtd/nand_ecc.h>
2603 +#include <linux/mtd/partitions.h>
2604 +#include <linux/delay.h>
2605 +#include <asm/io.h>
2606 +#include <asm/hardware.h>
2607 +#include <asm/arch/sl2312.h>
2608 +#include "sl2312-flash-nand.h"
2609 +
2610 +
2611 +#include <linux/errno.h>
2612 +#include <linux/sched.h>
2613 +#include <linux/types.h>
2614 +#include <linux/mtd/compatmac.h>
2615 +#include <linux/interrupt.h>
2616 +#include <linux/bitops.h>
2617 +
2618 +
2619 +/*
2620 + * NAND low-level MTD interface functions
2621 + */
2622 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len);
2623 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len);
2624 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len);
2625 +
2626 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2627 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2628 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf);
2629 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf);
2630 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
2631 +                          size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel);
2632 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char *buf);
2633 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs,
2634 +                       unsigned long count, loff_t to, size_t * retlen);
2635 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs,
2636 +                       unsigned long count, loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel);
2637 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
2638 +static void sl2312_nand_sync (struct mtd_info *mtd);
2639 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,  struct nand_oobinfo *oobsel);
2640 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt);
2641 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page);
2642 +
2643 +/*
2644 + * MTD structure for sl2312 NDFMC
2645 + */
2646 +static struct mtd_info *sl2312_mtd = NULL;
2647 +static int nand_page=0,nand_col=0;
2648 +
2649 +/* Define default oob placement schemes for large and small page devices */
2650 +static struct nand_oobinfo nand_oob_8 = {
2651 +       .useecc = MTD_NANDECC_AUTOPLACE,
2652 +       .eccbytes = 3,
2653 +       .eccpos = {0, 1, 2},
2654 +       .oobfree = { {3, 2}, {6, 2} }
2655 +};
2656 +
2657 +static struct nand_oobinfo nand_oob_16 = {
2658 +       .useecc = MTD_NANDECC_AUTOPLACE,
2659 +       .eccbytes = 6,
2660 +       .eccpos = {0, 1, 2, 3, 6, 7},
2661 +       .oobfree = { {8, 8} }
2662 +};
2663 +
2664 +static struct nand_oobinfo nand_oob_64 = {
2665 +       .useecc = MTD_NANDECC_AUTOPLACE,
2666 +       .eccbytes = 24,
2667 +       .eccpos = {
2668 +               40, 41, 42, 43, 44, 45, 46, 47,
2669 +               48, 49, 50, 51, 52, 53, 54, 55,
2670 +               56, 57, 58, 59, 60, 61, 62, 63},
2671 +       .oobfree = { {2, 38} }
2672 +};
2673 +
2674 +
2675 +/*
2676 + * Define partitions for flash device
2677 + */
2678 +/* the base address of FLASH control register */
2679 +#define FLASH_CONTROL_BASE_ADDR            (IO_ADDRESS(SL2312_FLASH_CTRL_BASE))
2680 +#define SL2312_GLOBAL_BASE_ADDR     (IO_ADDRESS(SL2312_GLOBAL_BASE))
2681 +//#define SL2312_FLASH_BASE_ADDR      (IO_ADDRESS(SL2312_FLASH_BASE))
2682 +#define SL2312_FLASH_BASE_ADDR       FLASH_VADDR(SL2312_FLASH_BASE)
2683 +static unsigned int CHIP_EN;
2684 +/* define read/write register utility */
2685 +//#define FLASH_READ_REG(offset)                       (__raw_readl(offset+FLASH_CONTROL_BASE_ADDR))
2686 +//#define FLASH_WRITE_REG(offset,val)  (__raw_writel(val,offset+FLASH_CONTROL_BASE_ADDR))
2687 +//#define FLASH_READ_DATA(offset)                      (__raw_readb(offset+SL2312_FLASH_BASE_ADDR))
2688 +//#define FLASH_WRITE_DATA(offset,val)         (__raw_writeb(val,offset+SL2312_FLASH_BASE_ADDR))
2689 +
2690 +unsigned int FLASH_READ_REG(unsigned int addr)
2691 +{
2692 +    unsigned int *base;
2693 +    unsigned int data;
2694 +
2695 +    base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2696 +    data = *base;
2697 +    return (data);
2698 +}
2699 +
2700 +void FLASH_WRITE_REG(unsigned int addr,unsigned int data)
2701 +{
2702 +    unsigned int *base;
2703 +
2704 +    base = (unsigned int *)(FLASH_CONTROL_BASE_ADDR + addr);
2705 +    *base = data;
2706 +    return;
2707 +}
2708 +
2709 +unsigned int FLASH_READ_DATA(unsigned int addr)
2710 +{
2711 +    unsigned char *base;
2712 +    unsigned int data;
2713 +
2714 +    base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2715 +    data = *base;
2716 +    return (data);
2717 +}
2718 +
2719 +void FLASH_WRITE_DATA(unsigned int addr,unsigned int data)
2720 +{
2721 +    unsigned char *base;
2722 +
2723 +    base = (unsigned char *)(SL2312_FLASH_BASE_ADDR + addr);
2724 +    *base = data;
2725 +    return;
2726 +}
2727 +
2728 +/* the offset of FLASH control register */
2729 +enum NFLASH_REGISTER {
2730 +       NFLASH_ID                       = 0x0000,
2731 +       NFLASH_STATUS                   = 0x0008,
2732 +       NFLASH_TYPE                     = 0x000c,
2733 +       NFLASH_ACCESS                   = 0x0030,
2734 +       NFLASH_COUNT                    = 0x0034,
2735 +       NFLASH_CMD_ADDR                 = 0x0038,
2736 +       NFLASH_ADDRESS                  = 0x003C,
2737 +       NFLASH_DATA                             = 0x0040,
2738 +       NFLASH_TIMING                   = 0x004C,
2739 +       NFLASH_ECC_STATUS               = 0x0050,
2740 +       NFLASH_ECC_CONTROL              = 0x0054,
2741 +       NFLASH_ECC_OOB                  = 0x005c,
2742 +       NFLASH_ECC_CODE_GEN0    = 0x0060,
2743 +       NFLASH_ECC_CODE_GEN1    = 0x0064,
2744 +       NFLASH_ECC_CODE_GEN2    = 0x0068,
2745 +       NFLASH_ECC_CODE_GEN3    = 0x006C,
2746 +       NFLASH_FIFO_CONTROL             = 0x0070,
2747 +       NFLASH_FIFO_STATUS              = 0x0074,
2748 +       NFLASH_FIFO_ADDRESS             = 0x0078,
2749 +       NFLASH_FIFO_DATA                = 0x007c,
2750 +};
2751 +
2752 +
2753 +
2754 +//#define FLASH_BASE   FLASH_CONTROL_BASE_ADDR
2755 +//#define FLASH_SIZE   0x00800000 //INTEGRATOR_FLASH_SIZE
2756 +
2757 +//#define FLASH_PART_SIZE 8388608
2758 +
2759 +//static unsigned int flash_indirect_access = 0;
2760 +
2761 +
2762 +#ifdef CONFIG_SL2312_SHARE_PIN
2763 +void sl2312flash_enable_nand_flash(void)
2764 +{
2765 +    unsigned int    reg_val;
2766 +
2767 +    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2768 +    reg_val = reg_val & 0xfffffffb;
2769 +    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2770 +    return;
2771 +}
2772 +
2773 +void sl2312flash_disable_nand_flash(void)
2774 +{
2775 +    unsigned int    reg_val;
2776 +
2777 +    reg_val = readl(SL2312_GLOBAL_BASE_ADDR + 0x30);
2778 +    reg_val = reg_val | 0x00000004;
2779 +    writel(reg_val,SL2312_GLOBAL_BASE_ADDR + 0x30);
2780 +    return;
2781 +}
2782 +#endif
2783 +
2784 +extern struct nand_oobinfo jffs2_oobinfo;
2785 +/*
2786 + * Define partitions for flash devices
2787 + */
2788 +
2789 +static struct mtd_partition sl2312_partitions[] = {
2790 +       { name: "RedBoot", offset: 0x00000000, size: 0x0020000, },
2791 +       { name: "Kernel", offset: 0x00020000, size: 0x00200000, },
2792 +       { name: "Ramdisk", offset: 0x00220000, size: 0x00280000, },
2793 +       { name: "Application", offset: 0x004A0000, size: 0x00320000, },
2794 +       { name: "VCTL", offset: 0x007C0000, size: 0x20000, },
2795 +       { name: "CurConf", offset: 0x007E0000, size: 0x20000, },
2796 +       { name: "FIS directory", offset: 0x007e0000, size: 0x00020000, }
2797 +
2798 +};
2799 +
2800 +
2801 +/*
2802 + *     hardware specific access to control-lines
2803 +*/
2804 +static void sl2312_hwcontrol(struct mtd_info *mtd, int cmd)
2805 +{
2806 +
2807 +       return ;
2808 +}
2809 +
2810 +static int sl2312_nand_scan_bbt(struct mtd_info *mtd)
2811 +{
2812 +       return 0;
2813 +}
2814 +
2815 +/**
2816 + * nand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
2817 + * @mtd:       MTD device structure
2818 + * @ofs:       offset relative to mtd start
2819 + */
2820 +static int sl2312_nand_block_isbad (struct mtd_info *mtd, loff_t ofs)
2821 +{
2822 +       /* Check for invalid offset */
2823 +       if (ofs > mtd->size)
2824 +               return -EINVAL;
2825 +
2826 +       return sl2312_nand_block_checkbad (mtd, ofs, 1, 0);
2827 +}
2828 +
2829 +/**
2830 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
2831 + * @mtd:       MTD device structure
2832 + * @ofs:       offset from device start
2833 + * @getchip:   0, if the chip is already selected
2834 + * @allowbbt:  1, if its allowed to access the bbt area
2835 + *
2836 + * Check, if the block is bad. Either by reading the bad block table or
2837 + * calling of the scan function.
2838 + */
2839 +
2840 +static int sl2312_nand_erase_block(struct mtd_info *mtd, int page)
2841 +{
2842 +       int opcode;
2843 +       /* Send commands to erase a page */
2844 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2845 +
2846 +               if(mtd->oobblock > 528)
2847 +                   FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21);  // 3 address & 2 command
2848 +               else
2849 +                   FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11);  // 2 address & 2 command
2850 +
2851 +               FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
2852 +               FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
2853 +
2854 +
2855 +
2856 +               /* read maker code */
2857 +               opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
2858 +               FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
2859 +
2860 +               while(opcode&0x80000000) //polling flash access 31b
2861 +       {
2862 +           opcode=FLASH_READ_REG(NFLASH_ACCESS);
2863 +           //sl2312_flash_delay();
2864 +           schedule();
2865 +           //cond_resched();
2866 +       }
2867 +}
2868 +
2869 +void sl2312_flash_delay(void)
2870 +{
2871 +      int i;
2872 +
2873 +      for(i=0; i<50; i++)
2874 +           i=i;
2875 +}
2876 +
2877 +static int sl2312_nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
2878 +{
2879 +       struct nand_chip *this = mtd->priv;
2880 +
2881 +       if (!this->bbt)
2882 +               return this->block_bad(mtd, ofs, getchip);
2883 +
2884 +       /* Return info from the table */
2885 +       return nand_isbad_bbt (mtd, ofs, allowbbt);
2886 +}
2887 +
2888 +/**
2889 + * nand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
2890 + * @mtd:       MTD device structure
2891 + * @ofs:       offset relative to mtd start
2892 + */
2893 +static int sl2312_nand_block_markbad (struct mtd_info *mtd, loff_t ofs)
2894 +{
2895 +       struct nand_chip *this = mtd->priv;
2896 +       int ret;
2897 +
2898 +        if ((ret = sl2312_nand_block_isbad(mtd, ofs))) {
2899 +               /* If it was bad already, return success and do nothing. */
2900 +               if (ret > 0)
2901 +                       return 0;
2902 +               return ret;
2903 +        }
2904 +
2905 +       return this->block_markbad(mtd, ofs);
2906 +}
2907 +
2908 +/*
2909 + *     Get chip for selected access
2910 + */
2911 +static inline void sl2312_nand_get_chip (struct nand_chip *this, struct mtd_info *mtd, int new_state, int *erase_state)
2912 +{
2913 +
2914 +       DECLARE_WAITQUEUE (wait, current);
2915 +
2916 +       /*
2917 +        * Grab the lock and see if the device is available
2918 +        * For erasing, we keep the spinlock until the
2919 +        * erase command is written.
2920 +       */
2921 +retry:
2922 +       spin_lock_bh (&this->chip_lock);
2923 +
2924 +       if (this->state == FL_READY) {
2925 +               this->state = new_state;
2926 +               if (new_state != FL_ERASING)
2927 +                       spin_unlock_bh (&this->chip_lock);
2928 +               return;
2929 +       }
2930 +
2931 +       if (this->state == FL_ERASING) {
2932 +               if (new_state != FL_ERASING) {
2933 +                       this->state = new_state;
2934 +                       spin_unlock_bh (&this->chip_lock);
2935 +                       this->select_chip(mtd, 0);      /* select in any case */
2936 +                       this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2937 +                       return;
2938 +               }
2939 +       }
2940 +
2941 +       set_current_state (TASK_UNINTERRUPTIBLE);
2942 +       add_wait_queue (&this->wq, &wait);
2943 +       spin_unlock_bh (&this->chip_lock);
2944 +       schedule ();
2945 +       remove_wait_queue (&this->wq, &wait);
2946 +       goto retry;
2947 +}
2948 +
2949 +/*
2950 +*      read device ready pin
2951 +*/
2952 +static int sl2312_device_ready(struct mtd_info *mtd)
2953 +{
2954 +       int ready;
2955 +
2956 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
2957 +       FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000070); //set only command no address and two data
2958 +
2959 +       FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
2960 +
2961 +
2962 +       ready = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
2963 +       FLASH_WRITE_REG(NFLASH_ACCESS, ready);
2964 +
2965 +       while(ready&0x80000000) //polling flash access 31b
2966 +    {
2967 +        ready=FLASH_READ_REG(NFLASH_ACCESS);
2968 +        //sl2312_flash_delay();
2969 +               schedule();
2970 +    }
2971 +    FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
2972 +       ready=FLASH_READ_REG(NFLASH_DATA)&0xff;
2973 +       return ready;
2974 +}
2975 +void sl2312_enable_hwecc(struct mtd_info *mtd, int mode)
2976 +{
2977 +       /* reset first */
2978 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
2979 +
2980 +}
2981 +
2982 +
2983 +void sl2312_device_setup(void)
2984 +{
2985 +
2986 +}
2987 +static u_char sl2312_nand_read_byte(struct mtd_info *mtd)
2988 +{
2989 +
2990 +        unsigned int    data=0, page=0, col=0, tmp, i;
2991 +
2992 +        printk ("**************************sl2312_nand_read_byte !! \n");
2993 +        //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
2994 +        //col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
2995 +        page = nand_page;
2996 +        col  = nand_col;
2997 +        for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
2998 +        {
2999 +               if(i==col)
3000 +                               data = FLASH_READ_DATA(page*mtd->oobblock +i);
3001 +                       else
3002 +                               tmp = FLASH_READ_DATA(page*mtd->oobblock +i);
3003 +        }
3004 +        return data&0xff;
3005 +}
3006 +
3007 +static void sl2312_nand_write_byte(struct mtd_info *mtd, u_char byte)
3008 +{
3009 +        //struct nand_chip *this = mtd->priv;
3010 +        unsigned int    page=0, col=0, i;
3011 +        u_char *databuf,oobbuf[mtd->oobsize];
3012 +        size_t  retlen;
3013 +        retlen=0;
3014 +               printk ("********************sl2312_nand_write_byte !! \n");
3015 +               page = nand_page;
3016 +        col  = nand_col;
3017 +               databuf = kmalloc (mtd->oobsize+mtd->oobblock,GFP_KERNEL);
3018 +
3019 +               if (!databuf) {
3020 +                       printk ("sl2312_nand_write_byte : Unable to allocate SL2312 NAND MTD device structure.\n");
3021 +
3022 +               }
3023 +
3024 +                for(i=0;i<(mtd->oobblock+mtd->oobsize);i++)
3025 +               databuf[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3026 +
3027 +        databuf[col] = byte;
3028 +        sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3029 +
3030 +}
3031 +
3032 +static void sl2312_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
3033 +{
3034 +       int i, page=0,col=0;
3035 +       struct nand_chip *this = mtd->priv;
3036 +       u_char *databuf, *oobbuf;
3037 +        size_t  retlen;
3038 +        retlen=0;
3039 +
3040 +
3041 +               printk ("***********************sl2312_nand_write_buf !! \n");
3042 +               databuf = &(this->data_buf[0]);
3043 +               oobbuf = &(this->data_buf[mtd->oobblock]);
3044 +               for (i = 0; i < mtd->oobsize; i++)
3045 +                       oobbuf[i] = 0xff;
3046 +
3047 +       if(len < mtd->oobblock)
3048 +       {
3049 +               //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3050 +               //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3051 +               //col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3052 +               page = nand_page;
3053 +        col  = nand_col;
3054 +
3055 +               sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, databuf, oobbuf, NULL);
3056 +
3057 +        for(i=col;i<len;i++)
3058 +               databuf[col+i] = buf[i];
3059 +
3060 +        sl2312_nand_write_ecc (mtd, page, mtd->oobblock, &retlen, databuf, oobbuf, NULL);
3061 +
3062 +       }
3063 +
3064 +}
3065 +
3066 +static void sl2312_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
3067 +{
3068 +       int i, page=0,col=0,addr=0,tmp=0;
3069 +       //struct nand_chip *this = mtd->priv;
3070 +       printk ("********************sl2312_nand_read_buf !! \n");
3071 +       if(len < mtd->oobblock)
3072 +       {
3073 +               //addr = FLASH_READ_REG(NFLASH_ADDRESS);
3074 +               //page = FLASH_READ_REG(NFLASH_ADDRESS)&0xffffff00;
3075 +               //col  = FLASH_READ_REG(NFLASH_ADDRESS)&0x000000ff;
3076 +               page = nand_page;
3077 +        col  = nand_col;
3078 +               for (i=col; i<((mtd->oobblock+mtd->oobsize)-col); i++)
3079 +               {
3080 +                       if(i<len)
3081 +                               buf[i] = FLASH_READ_DATA(addr+i);
3082 +                       else
3083 +                               tmp = FLASH_READ_DATA(addr+i);
3084 +               }
3085 +       }
3086 +}
3087 +
3088 +static int sl2312_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
3089 +{
3090 +       int i;
3091 +       //struct nand_chip *this = mtd->priv;
3092 +       u_char *datatmp, *oobtmp;
3093 +       size_t  retlen;
3094 +       retlen=0;
3095 +
3096 +       datatmp = kmalloc (mtd->oobblock,GFP_KERNEL);
3097 +       oobtmp = kmalloc (mtd->oobsize,GFP_KERNEL);
3098 +
3099 +       if ((!datatmp)||(!oobtmp)) {
3100 +               printk ("sl2312_nand_verify_buf : Unable to allocate SL2312 NAND MTD device structure.\n");
3101 +
3102 +       }
3103 +       //page = nand_page;
3104 +       for(i=0;i<mtd->oobblock;i++)
3105 +               datatmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock +i);
3106 +       /* read oobdata */
3107 +       for (i = 0; i <  mtd->oobsize; i++)
3108 +               oobtmp[i] = FLASH_READ_DATA(nand_page*mtd->oobblock + mtd->oobblock + i);
3109 +
3110 +       if(len==mtd->oobblock)
3111 +       {
3112 +               for (i=0; i<len; i++)
3113 +               {
3114 +                       if (buf[i] != datatmp[i])
3115 +                       {
3116 +                               kfree(datatmp);
3117 +                               kfree(oobtmp);
3118 +                               printk("Data verify error -> page: %x, byte: %x \n",nand_page,i);
3119 +                               return i;
3120 +                       }
3121 +               }
3122 +       }
3123 +       else if(len == mtd->oobsize)
3124 +       {
3125 +               for (i=0; i<len; i++)
3126 +               {
3127 +                       if (buf[i] != oobtmp[i])
3128 +                       {
3129 +                               kfree(datatmp);
3130 +                               kfree(oobtmp);
3131 +                               printk("OOB verify error -> page: %x, byte: %x \n",nand_page,i);
3132 +                               return i;
3133 +                       }
3134 +               }
3135 +       }
3136 +       else
3137 +       {
3138 +               printk (KERN_WARNING "sl2312_nand_verify_buf : verify length not match 0x%08x\n", len);
3139 +               kfree(datatmp);
3140 +               kfree(oobtmp);
3141 +               return -1;
3142 +       }
3143 +
3144 +       kfree(datatmp);
3145 +       kfree(oobtmp);
3146 +       return 0;
3147 +}
3148 +
3149 +/*
3150 + * Send command to NAND device
3151 + */
3152 +static void sl2312_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
3153 +{
3154 +       register struct nand_chip *this = mtd->priv;
3155 +       int opcode;
3156 +
3157 +
3158 +       /*
3159 +        * program and erase have their own busy handlers
3160 +        * status and sequential in needs no delay
3161 +       */
3162 +       switch (command) {
3163 +
3164 +       case NAND_CMD_PAGEPROG:
3165 +       case NAND_CMD_ERASE1:
3166 +       case NAND_CMD_ERASE2:
3167 +       case NAND_CMD_SEQIN:
3168 +       case NAND_CMD_STATUS:
3169 +       case NAND_CMD_READ0:
3170 +
3171 +               /*
3172 +                * Write out the command to the device.
3173 +                */
3174 +               if (column != -1 || page_addr != -1) {
3175 +
3176 +                       /* Serially input address */
3177 +                       if (column != -1)
3178 +                               //FLASH_WRITE_REG(NFLASH_ADDRESS,column);
3179 +                               nand_col=column;
3180 +
3181 +                       opcode = FLASH_READ_REG(NFLASH_ADDRESS);
3182 +
3183 +                       if (page_addr != -1)
3184 +                               //FLASH_WRITE_REG(NFLASH_ADDRESS,opcode|(page_addr<<8));
3185 +                               nand_page = page_addr;
3186 +
3187 +               }
3188 +               return;
3189 +
3190 +       case NAND_CMD_RESET:
3191 +               if (this->dev_ready)
3192 +                       break;
3193 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3194 +               FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff70); //set only command and no other data
3195 +               FLASH_WRITE_REG(NFLASH_CMD_ADDR, NAND_CMD_RESET); //write reset command
3196 +
3197 +               opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3198 +               FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3199 +
3200 +               while(opcode&0x80000000) //polling flash access 31b
3201 +       {
3202 +           opcode=FLASH_READ_REG(NFLASH_ACCESS);
3203 +           //sl2312_flash_delay();
3204 +           schedule();
3205 +       }
3206 +               while ( !(sl2312_device_ready(mtd) & 0x40));
3207 +               {
3208 +                       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3209 +                       //sl2312_flash_delay();
3210 +                       schedule();
3211 +                       return;
3212 +               }
3213 +       /* This applies to read commands */
3214 +       default:
3215 +               /*
3216 +                * If we don't have access to the busy pin, we apply the given
3217 +                * command delay
3218 +               */
3219 +               if (!this->dev_ready) {
3220 +                       udelay (this->chip_delay);
3221 +                       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3222 +                       return;
3223 +               }
3224 +       }
3225 +
3226 +       /* wait until command is processed */
3227 +       while (!this->dev_ready(mtd));
3228 +
3229 +}
3230 +/*Add function*/
3231 +static void nand_read_id(int chip_no, unsigned char *id)
3232 +{
3233 +       unsigned int opcode, i;
3234 +
3235 +       if(chip_no==0)
3236 +               CHIP_EN = NFLASH_CHIP0_EN;
3237 +       else
3238 +               CHIP_EN = NFLASH_CHIP1_EN;
3239 +
3240 +       opcode = FLASH_READ_REG(NFLASH_TYPE);
3241 +
3242 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3243 +       if((opcode&0x00000300)<=0x00000100)
3244 +           FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000100); //set only command & address and two data
3245 +       else
3246 +           FLASH_WRITE_REG(NFLASH_COUNT, 0x7f000300); //set only command & address and 4 data
3247 +
3248 +       FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000090); //write read id command
3249 +       FLASH_WRITE_REG(NFLASH_ADDRESS, 0x00000000); //write address 0x00
3250 +
3251 +       /* read maker code */
3252 +       opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3253 +       FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3254 +       opcode=FLASH_READ_REG(NFLASH_ACCESS);
3255 +               while(opcode&0x80000000) //polling flash access 31b
3256 +       {
3257 +           opcode=FLASH_READ_REG(NFLASH_ACCESS);
3258 +           //sl2312_flash_delay();
3259 +           schedule();
3260 +       }
3261 +
3262 +    opcode = FLASH_READ_REG(NFLASH_DATA);
3263 +    if(DWIDTH==NFLASH_WiDTH16)
3264 +    {
3265 +               id[0] = opcode&0xff;
3266 +               id[1] = (opcode&0xff00)>>8;
3267 +    }
3268 +    else
3269 +    {
3270 +           id[0] = opcode&0xff;
3271 +           opcode = 0x80002000|DWIDTH|CHIP_EN;//|chip0_en; //set start bit & 8bits read command
3272 +                       FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3273 +                       opcode=FLASH_READ_REG(NFLASH_ACCESS);
3274 +                       while(opcode&0x80000000) //polling flash access 31b
3275 +               {
3276 +              opcode=FLASH_READ_REG(NFLASH_ACCESS);
3277 +              //sl2312_flash_delay();
3278 +              schedule();
3279 +               }
3280 +               opcode = FLASH_READ_REG(NFLASH_DATA);
3281 +               id[1] = (opcode&0xff00)>>8;
3282 +
3283 +               opcode=FLASH_READ_REG(NFLASH_TYPE);
3284 +               if((opcode&0x300)>0x100)
3285 +               {
3286 +                   for(i=0;i<2;i++)
3287 +                   {
3288 +                               //data cycle 3 & 4 ->not use
3289 +                               opcode = 0x80002000|DWIDTH|CHIP_EN;//set start bit & 8bits read command
3290 +                                       FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3291 +                                       opcode=FLASH_READ_REG(NFLASH_ACCESS);
3292 +                               while(opcode&0x80000000) //polling flash access 31b
3293 +                               {
3294 +                                  opcode=FLASH_READ_REG(NFLASH_ACCESS);
3295 +                                  //sl2312_flash_delay();
3296 +                                  schedule();
3297 +                               }
3298 +
3299 +                               opcode=FLASH_READ_REG(NFLASH_DATA);
3300 +                               id[2+i] = (opcode&(0xff0000<<i*8))>>(8*(2+i));
3301 +                   }
3302 +               }
3303 +    }
3304 +    FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3305 +}
3306 +
3307 +/*
3308 + * NAND erase a block
3309 + */
3310 +static int sl2312_nand_erase (struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
3311 +{
3312 +       int page, len, status, pages_per_block, ret, chipnr;
3313 +       struct nand_chip *this = mtd->priv;
3314 +
3315 +       DEBUG (MTD_DEBUG_LEVEL3,
3316 +              "nand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
3317 +
3318 +       /* Start address must align on block boundary */
3319 +       if (instr->addr & ((1 << this->phys_erase_shift) - 1)) {
3320 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
3321 +               return -EINVAL;
3322 +       }
3323 +
3324 +       /* Length must align on block boundary */
3325 +       if (instr->len & ((1 << this->phys_erase_shift) - 1)) {
3326 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Length not block aligned\n");
3327 +               return -EINVAL;
3328 +       }
3329 +
3330 +       /* Do not allow erase past end of device */
3331 +       if ((instr->len + instr->addr) > mtd->size) {
3332 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Erase past end of device\n");
3333 +               return -EINVAL;
3334 +       }
3335 +
3336 +       instr->fail_addr = 0xffffffff;
3337 +
3338 +       /* Grab the lock and see if the device is available */
3339 +       sl2312_nand_get_chip (this, mtd, FL_ERASING, NULL);
3340 +
3341 +       /* Shift to get first page */
3342 +       page = (int) (instr->addr >> this->page_shift);
3343 +       chipnr = (int) (instr->addr >> this->chip_shift);
3344 +
3345 +       /* Calculate pages in each block */
3346 +       pages_per_block = 1 << (this->phys_erase_shift - this->page_shift);
3347 +
3348 +       /* Select the NAND device */
3349 +       //this->select_chip(mtd, chipnr);
3350 +       this->select_chip(mtd, 0);
3351 +
3352 +       /* Check the WP bit */
3353 +       /* Check, if it is write protected */
3354 +       status = sl2312_device_ready(mtd);
3355 +       if (!(status & 0x80)) {
3356 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Device is write protected!!!\n");
3357 +               instr->state = MTD_ERASE_FAILED;
3358 +               goto erase_exit;
3359 +       }
3360 +
3361 +       /* Loop through the pages */
3362 +       len = instr->len;
3363 +
3364 +       instr->state = MTD_ERASING;
3365 +
3366 +       while (len) {
3367 +               /* Check if we have a bad block, we do not erase bad blocks ! */
3368 +               if (this->block_bad(mtd, ((loff_t) page) << this->page_shift, 0)) {
3369 +                       printk (KERN_WARNING "nand_erase: attempt to erase a bad block at page 0x%08x\n", page);
3370 +                       //instr->state = MTD_ERASE_FAILED;
3371 +                       //goto erase_exit;
3372 +               }
3373 +
3374 +               /* Invalidate the page cache, if we erase the block which contains
3375 +                  the current cached page */
3376 +               if (page <= this->pagebuf && this->pagebuf < (page + pages_per_block))
3377 +                       this->pagebuf = -1;
3378 +               /////////
3379 +
3380 +               ///* Send commands to erase a page */
3381 +               //FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3382 +           //
3383 +               //if(mtd->oobblock > 528)
3384 +               //    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff21);  // 3 address & 2 command
3385 +               //else
3386 +               //    FLASH_WRITE_REG(NFLASH_COUNT, 0x7f0fff11);  // 2 address & 2 command
3387 +               //
3388 +               //FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x0000d060); // write read id command
3389 +               //FLASH_WRITE_REG(NFLASH_ADDRESS, page); //write address 0x00
3390 +               //
3391 +               //
3392 +               //
3393 +               ///* read maker code */
3394 +               //opcode = 0x80003000|DWIDTH|CHIP_EN; //set start bit & 8bits write command
3395 +               //FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3396 +               //
3397 +               //while(opcode&0x80000000) //polling flash access 31b
3398 +       //{
3399 +        //   opcode=FLASH_READ_REG(NFLASH_ACCESS);
3400 +        //   //sl2312_flash_delay();
3401 +        //   schedule();
3402 +        //   //cond_resched();
3403 +       //}
3404 +       sl2312_nand_erase_block(mtd, page);
3405 +       //////////////
3406 +               status = this->waitfunc (mtd, this, FL_ERASING);
3407 +               /* See if block erase succeeded */
3408 +               if (status & 0x01) {
3409 +                       DEBUG (MTD_DEBUG_LEVEL0, "nand_erase: " "Failed erase, page 0x%08x\n", page);
3410 +                       instr->state = MTD_ERASE_FAILED;
3411 +                       instr->fail_addr = (page << this->page_shift);
3412 +                       goto erase_exit;
3413 +               }
3414 +
3415 +               /* Increment page address and decrement length */
3416 +               len -= (1 << this->phys_erase_shift);
3417 +               page += pages_per_block;
3418 +
3419 +               /* Check, if we cross a chip boundary */
3420 +               if (len && !(page & this->pagemask)) {
3421 +                       chipnr++;
3422 +                       this->select_chip(mtd, 0);
3423 +                       this->select_chip(mtd, 0);
3424 +               }
3425 +               //sl2312_flash_delay();
3426 +           schedule();
3427 +           //cond_resched();
3428 +       }
3429 +       instr->state = MTD_ERASE_DONE;
3430 +
3431 +erase_exit:
3432 +       /* De-select the NAND device */
3433 +       this->select_chip(mtd, 0);
3434 +       spin_unlock_bh (&this->chip_lock);
3435 +
3436 +       ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;;
3437 +       /* Do call back function */
3438 +       if (!ret && instr->callback)
3439 +               instr->callback (instr);
3440 +
3441 +       /* The device is ready */
3442 +       spin_lock_bh (&this->chip_lock);
3443 +       this->state = FL_READY;
3444 +       spin_unlock_bh (&this->chip_lock);
3445 +       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3446 +       /* Return more or less happy */
3447 +       return ret;
3448 +}
3449 +
3450 +static void sl2312_nand_select_chip(struct mtd_info *mtd, int chip)
3451 +{
3452 +       //struct nand_chip *this = mtd->priv;
3453 +
3454 +       switch(chip) {
3455 +       case -1:
3456 +               CHIP_EN = NFLASH_CHIP0_EN;
3457 +               break;
3458 +       case 0:
3459 +               CHIP_EN = NFLASH_CHIP0_EN;
3460 +               break;
3461 +       case 1:
3462 +               CHIP_EN = NFLASH_CHIP1_EN;
3463 +               break;
3464 +       default:
3465 +                       CHIP_EN = NFLASH_CHIP0_EN;
3466 +                       break;
3467 +       }
3468 +}
3469 +
3470 +/**
3471 + * nand_default_block_markbad - [DEFAULT] mark a block bad
3472 + * @mtd:       MTD device structure
3473 + * @ofs:       offset from device start
3474 + *
3475 + * This is the default implementation, which can be overridden by
3476 + * a hardware specific driver.
3477 +*/
3478 +static int sl2312_nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
3479 +{
3480 +       struct nand_chip *this = mtd->priv;
3481 +       u_char buf[2] = {0, 0};
3482 +       size_t  retlen;
3483 +       int block;
3484 +
3485 +       /* Get block number */
3486 +       block = ((int) ofs) >> this->bbt_erase_shift;
3487 +       this->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
3488 +
3489 +       /* Do we have a flash based bad block table ? */
3490 +       if (this->options & NAND_USE_FLASH_BBT)
3491 +               return nand_update_bbt (mtd, ofs);
3492 +
3493 +       /* We write two bytes, so we dont have to mess with 16 bit access */
3494 +       ofs += mtd->oobsize + (this->badblockpos & ~0x01);
3495 +       return sl2312_nand_write_oob (mtd, ofs , 2, &retlen, buf);
3496 +}
3497 +
3498 +/* Appropriate chip should already be selected */
3499 +static int sl2312_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)//(struct mtd_info *mtd, unsigned long page, )
3500 +{
3501 +       u_char *buf, *oobbuf;
3502 +       size_t  retlen;
3503 +       unsigned long page, chipnr;
3504 +       struct nand_chip *this = mtd->priv;
3505 +
3506 +       if (getchip) {
3507 +               page = (int)(ofs >> this->page_shift);
3508 +               chipnr = (int)(ofs >> this->chip_shift);
3509 +
3510 +               /* Grab the lock and see if the device is available */
3511 +               sl2312_nand_get_chip (this, mtd, FL_READING, NULL);
3512 +               /* Select the NAND device */
3513 +               this->select_chip(mtd, chipnr);
3514 +       } else
3515 +               page = (int) ofs;
3516 +
3517 +       buf = kmalloc (mtd->oobblock,GFP_KERNEL);
3518 +       oobbuf = kmalloc (mtd->oobsize,GFP_KERNEL);
3519 +
3520 +       if ((!buf)||(!oobbuf)) {
3521 +               printk ("sl2312_nand_block_bad : Unable to allocate SL2312 NAND MTD device structure.\n");
3522 +
3523 +       }
3524 +
3525 +       sl2312_nand_read_ecc (mtd, page, mtd->oobblock , &retlen, buf, oobbuf, NULL);
3526 +
3527 +
3528 +       if(((mtd->oobblock < 528)&&(oobbuf[5] != 0xff))||((mtd->oobblock > 528)&&(oobbuf[0] != 0xff)))
3529 +       {
3530 +               kfree(buf);
3531 +               kfree(oobbuf);
3532 +               return 1;
3533 +       }
3534 +
3535 +       kfree(buf);
3536 +       kfree(oobbuf);
3537 +       return 0;
3538 +}
3539 +
3540 +/*
3541 +*      Use NAND read ECC
3542 +*/
3543 +static int sl2312_nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3544 +{
3545 +       return sl2312_nand_read_ecc (mtd, from, len, retlen, buf, NULL, NULL);
3546 +}
3547 +
3548 +/*
3549 + * NAND read with ECC
3550 + */
3551 +static int sl2312_nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
3552 +                         size_t * retlen, u_char * buf, u_char * oob_buf, struct nand_oobinfo *oobsel)
3553 +{
3554 +       int j, col, page, opcode, i;
3555 +       int end=0;//, ecc=0;//, end_page=0;
3556 +       int erase_state = 0;
3557 +       int read = 0, oob = 0, ecc_failed = 0;//, ecc_status = 0
3558 +       struct nand_chip *this = mtd->priv;
3559 +       u_char *data_poi, *oob_data = oob_buf;
3560 +       //u_char ecc_calc[6];
3561 +       //u_char ecc_code[6];
3562 +       int     eccmode;
3563 +       int     *oob_config;
3564 +
3565 +
3566 +
3567 +       // use chip default if zero
3568 +       if (oobsel == NULL)
3569 +               oobsel = &mtd->oobinfo;
3570 +
3571 +       eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3572 +       oob_config = oobsel->eccpos;
3573 +
3574 +       DEBUG (MTD_DEBUG_LEVEL3, "nand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3575 +
3576 +       /* Do not allow reads past end of device */
3577 +       if ((from + len) > mtd->size) {
3578 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_read_ecc: Attempt read beyond end of device\n");
3579 +               *retlen = 0;
3580 +               return -EINVAL;
3581 +       }
3582 +
3583 +       /* Grab the lock and see if the device is available */
3584 +       sl2312_nand_get_chip (this, mtd ,FL_READING, &erase_state);
3585 +
3586 +       /* Select the NAND device */
3587 +       this->select_chip(mtd, 0);
3588 +
3589 +       /* First we calculate the starting page */
3590 +       page = from >> this->page_shift;
3591 +
3592 +       //end_page = mtd->oobblock + mtd->oobsize;
3593 +       end = mtd->oobblock;
3594 +       //ecc = mtd->eccsize;
3595 +       /* Get raw starting column */
3596 +       col = (from & (mtd->oobblock - 1));
3597 +
3598 +
3599 +       /* Send the read command */
3600 +       //this->cmdfunc (mtd, NAND_CMD_READ0, 0x00, page);
3601 +
3602 +       /* Loop until all data read */
3603 +       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3604 +       while (read < len) {
3605 +
3606 +               //udelay(1200);
3607 +               /* If we have consequent page reads, apply delay or wait for ready/busy pin */
3608 +               if (read) {
3609 +                       if (!this->dev_ready)
3610 +                               udelay (this->chip_delay);
3611 +                       else
3612 +                               while (!this->dev_ready(mtd));
3613 +               }
3614 +
3615 +               /*
3616 +                * If the read is not page aligned, we have to read into data buffer
3617 +                * due to ecc, else we read into return buffer direct
3618 +                */
3619 +               if (!col && (len - read) >= end)
3620 +                       data_poi = &buf[read];
3621 +               else
3622 +                       data_poi = this->data_buf;
3623 +
3624 +               /* get oob area, if we have no oob buffer from fs-driver */
3625 +               if (!oob_buf) {
3626 +                       oob_data = &this->data_buf[end];
3627 +                       oob = 0;
3628 +               }
3629 +
3630 +               j = 0;
3631 +               switch (eccmode) {
3632 +                       case NAND_ECC_NONE: {   /* No ECC, Read in a page */
3633 +                               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3634 +                               break;
3635 +                       }
3636 +
3637 +                       case NAND_ECC_SOFT:     /* Software ECC 3/256: Read in a page + oob data */
3638 +                               break;
3639 +
3640 +                       case NAND_ECC_HW3_256: /* Hardware ECC 3 byte /256 byte data: Read in first 256 byte, get ecc, */
3641 +                               break;
3642 +
3643 +                       case NAND_ECC_HW3_512:
3644 +                       case NAND_ECC_HW6_512: /* Hardware ECC 3/6 byte / 512 byte data : Read in a page  */
3645 +                               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3646 +                               break;
3647 +
3648 +                       default:
3649 +                               printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3650 +                               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0);
3651 +                               //BUG();
3652 +               }//end switch
3653 +
3654 +                       for(i=0;i<end;i++)
3655 +                       {
3656 +                               //udelay(7);
3657 +                               data_poi[i] = FLASH_READ_DATA(page*mtd->oobblock +i);
3658 +                       }
3659 +                       /* read oobdata */
3660 +                       for (i = 0; i <  mtd->oobsize; i++)
3661 +                       {
3662 +                               //udelay(7);
3663 +                               oob_data[oob + i] = FLASH_READ_DATA(page*mtd->oobblock +end+i);
3664 +                       }
3665 +
3666 +               /* Skip ECC, if not active */
3667 +                       if (eccmode == NAND_ECC_NONE)
3668 +                               goto readdata;
3669 +
3670 +                       // compare ecc and correct data
3671 +
3672 +                               opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3673 +                               while(!(opcode&0x80000000)) //polling flash access 31b
3674 +                       {
3675 +                                  opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3676 +                                  //sl2312_flash_delay();
3677 +                                  schedule();
3678 +                       }
3679 +                       for(j=0;j<(end/512);j++)
3680 +                       {//for 2k page
3681 +
3682 +                                       opcode = 0x00000000|oob_data[mtd->oobsize-3-4*j]<<16|oob_data[mtd->oobsize-2-4*j]<<8|oob_data[mtd->oobsize-1-4*j];
3683 +
3684 +                                       //opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(j*4));
3685 +
3686 +                                       FLASH_WRITE_REG(NFLASH_ECC_OOB, opcode);
3687 +                                       opcode = 0x00000000|(j<<8); //select ECC code generation 0
3688 +                                       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, opcode); //???
3689 +
3690 +                                       opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3691 +                                       if((opcode&0x00000003)==0x03)
3692 +                                       {
3693 +                                               printk (KERN_WARNING "\nPageRead Uncorrectable error !!\n");
3694 +                                               ecc_failed++;
3695 +                                       }
3696 +                                       else if((opcode&0x00000003)==0x01)
3697 +                                       {
3698 +                                               printk (KERN_WARNING "\nPageRead One bit data error !!");
3699 +                                               // correct data
3700 +                                               if((data_poi[(opcode&0xff80)>>7]>>((opcode&0x38)>>3))%1)
3701 +                                                       data_poi[(opcode&0xff80)>>7] &= ~(1<<((opcode&0x38)>>3));
3702 +                                               else
3703 +                                                       data_poi[(opcode&0xff80)>>7] |= (1<<((opcode&0x38)>>3));
3704 +
3705 +                                       }
3706 +                                       else if((opcode&0x00000003)==0x02)
3707 +                                       {
3708 +                                               printk (KERN_WARNING "\nPageRead One bit ECC error !!\n");
3709 +                                       }
3710 +                                       else if((opcode&0x00000003)==0x00)
3711 +                                       {
3712 +
3713 +                                       }
3714 +
3715 +                               }//for 2k page
3716 +readdata:
3717 +               if (col || (len - read) < end) {
3718 +                       for (j = col; j < end && read < len; j++)
3719 +                               buf[read++] = data_poi[j];
3720 +               } else
3721 +                       read += mtd->oobblock;
3722 +               /* For subsequent reads align to page boundary. */
3723 +               col = 0;
3724 +               /* Increment page address */
3725 +               page++;
3726 +               schedule();
3727 +       }
3728 +       /* De-select the NAND device */
3729 +       //this->select_chip(mtd, -1);
3730 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3731 +       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_INDIRECT);
3732 +       /* Wake up anyone waiting on the device */
3733 +       spin_lock_bh (&this->chip_lock);
3734 +       this->state = FL_READY;
3735 +       wake_up (&this->wq);
3736 +       spin_unlock_bh (&this->chip_lock);
3737 +
3738 +       /*
3739 +        * Return success, if no ECC failures, else -EIO
3740 +        * fs driver will take care of that, because
3741 +        * retlen == desired len and result == -EIO
3742 +        */
3743 +       *retlen = read;
3744 +       return ecc_failed ? -EIO : 0;
3745 +}
3746 +
3747 +/*
3748 + * Wait for command done. This applies to erase and program only
3749 + * Erase can take up to 400ms and program up to 20ms according to
3750 + * general NAND and SmartMedia specs
3751 + *
3752 +*/
3753 +static int sl2312_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
3754 +{
3755 +       unsigned long   timeo = jiffies;
3756 +       int     status, opcode;
3757 +
3758 +       if (state == FL_ERASING)
3759 +                timeo += (HZ * 400) / 1000;
3760 +       else
3761 +                timeo += (HZ * 20) / 1000;
3762 +
3763 +       spin_lock_bh (&this->chip_lock);
3764 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000); //set 31b = 0
3765 +       FLASH_WRITE_REG(NFLASH_COUNT, 0x007f000070); //set only command no address and two data
3766 +
3767 +       FLASH_WRITE_REG(NFLASH_CMD_ADDR, 0x00000070); //write read status command
3768 +
3769 +
3770 +       opcode = 0x80002000|DWIDTH|CHIP_EN; //set start bit & 8bits read command
3771 +       FLASH_WRITE_REG(NFLASH_ACCESS, opcode);
3772 +
3773 +       while(opcode&0x80000000) //polling flash access 31b
3774 +    {
3775 +        opcode=FLASH_READ_REG(NFLASH_ACCESS);
3776 +        //sl2312_flash_delay();
3777 +        schedule();
3778 +    }
3779 +
3780 +       while (time_before(jiffies, timeo)) {
3781 +               /* Check, if we were interrupted */
3782 +               if (this->state != state) {
3783 +                       spin_unlock_bh (&this->chip_lock);
3784 +                       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3785 +                       return 0;
3786 +               }
3787 +               if (this->dev_ready) {
3788 +                       if (this->dev_ready(mtd))
3789 +                               break;
3790 +               }
3791 +               if (FLASH_READ_REG(NFLASH_DATA) & 0x40)
3792 +                       break;
3793 +
3794 +               spin_unlock_bh (&this->chip_lock);
3795 +               yield ();
3796 +               spin_lock_bh (&this->chip_lock);
3797 +       }
3798 +       status = FLASH_READ_REG(NFLASH_DATA)&0xff;
3799 +       spin_unlock_bh (&this->chip_lock);
3800 +       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3801 +       return status;
3802 +}
3803 +
3804 +static int sl2312_nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf)
3805 +{
3806 +       int i, col, page, j=0;
3807 +       //int erase_state = 0;
3808 +       struct nand_chip *this = mtd->priv;
3809 +       u_char *databuf, *oobbuf;
3810 +
3811 +       databuf = &this->data_buf[0];
3812 +       oobbuf = &this->data_buf[mtd->oobblock];
3813 +               for (i = 0; i < mtd->oobsize; i++)
3814 +                       oobbuf[i] = 0xff;
3815 +
3816 +       DEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
3817 +
3818 +       /* Shift to get page */
3819 +       page = ((int) from) >> this->page_shift;
3820 +
3821 +       /* Mask to get column */
3822 +       col = from & (mtd->oobsize-1);  //0x0f;
3823 +
3824 +       /* Initialize return length value */
3825 +       *retlen = 0;
3826 +       sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
3827 +       for(i=col,j=0;i<mtd->oobsize||i<(col+len);i++,j++)
3828 +               buf[j] = oobbuf[i];
3829 +
3830 +       *retlen = j ;
3831 +       return 0;
3832 +}
3833 +
3834 +#define NOTALIGNED(x) (x & (mtd->oobblock-1)) != 0
3835 +/*
3836 +*      Use NAND write ECC
3837 +*/
3838 +static int sl2312_nand_write (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
3839 +{
3840 +       return (sl2312_nand_write_ecc (mtd, to, len, retlen, buf, NULL, NULL));
3841 +}
3842 +
3843 +/*
3844 + * NAND write with ECC
3845 + */
3846 +static int sl2312_nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len,
3847 +                          size_t * retlen, const u_char * buf, u_char * eccbuf, struct nand_oobinfo *oobsel)
3848 +{
3849 +       int page, ret = 0, oob = 0, written = 0;
3850 +       struct nand_chip *this = mtd->priv;
3851 +
3852 +       DEBUG (MTD_DEBUG_LEVEL3, "nand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
3853 +
3854 +
3855 +       /* Do not allow write past end of device */
3856 +       if ((to + len) > mtd->size) {
3857 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Attempt to write past end of page\n");
3858 +               return -EINVAL;
3859 +       }
3860 +
3861 +       /* reject writes, which are not page aligned */
3862 +       if (NOTALIGNED (to) || NOTALIGNED(len)) {
3863 +               printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
3864 +               return -EINVAL;
3865 +       }
3866 +
3867 +       // if oobsel is NULL, use chip defaults
3868 +       if (oobsel == NULL)
3869 +               oobsel = &mtd->oobinfo;
3870 +
3871 +       /* Shift to get page */
3872 +       page = ((int) to) >> this->page_shift;
3873 +
3874 +       /* Grab the lock and see if the device is available */
3875 +       sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
3876 +
3877 +       /* Select the NAND device */
3878 +       this->select_chip(mtd, 0);
3879 +
3880 +       /* Check the WP bit */
3881 +       if (!(sl2312_device_ready(mtd) & 0x80)) {
3882 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_ecc: Device is write protected!!!\n");
3883 +               ret = -EIO;
3884 +               goto out;
3885 +       }
3886 +
3887 +       /* Loop until all data is written */
3888 +       while (written < len) {
3889 +               //udelay(100);
3890 +               int cnt = mtd->oobblock;
3891 +               this->data_poi = (u_char*) &buf[written];
3892 +               /* We use the same function for write and writev */
3893 +               if (eccbuf) {
3894 +                       ret = sl2312_nand_write_page (mtd, this, page, &eccbuf[oob], oobsel);
3895 +                       oob += mtd->oobsize;
3896 +               } else
3897 +                       ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
3898 +
3899 +               if (ret)
3900 +                       goto out;
3901 +
3902 +               /* Update written bytes count */
3903 +               written += cnt;
3904 +               /* Increment page address */
3905 +               page++;
3906 +       }
3907 +
3908 +out:
3909 +       /* De-select the NAND device */
3910 +       //this->select_chip(mtd, -1);
3911 +
3912 +       /* Wake up anyone waiting on the device */
3913 +       spin_lock_bh (&this->chip_lock);
3914 +       this->state = FL_READY;
3915 +       wake_up (&this->wq);
3916 +       spin_unlock_bh (&this->chip_lock);
3917 +
3918 +       *retlen = written;
3919 +       return ret;
3920 +}
3921 +
3922 +/*
3923 + *     Nand_page_program function is used for write and writev !
3924 + *     This function will always program a full page of data
3925 + *     If you call it with a non page aligned buffer, you're lost :)
3926 + */
3927 +static int sl2312_nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int page, u_char *oob_buf,  struct nand_oobinfo *oobsel)
3928 +{
3929 +       int     i, j, status, opcode;
3930 +       u_char  ecc_code[16], *oob_data;
3931 +       int     eccmode = oobsel->useecc ? this->eccmode : NAND_ECC_NONE;
3932 +       //int   *oob_config = oobsel->eccpos;
3933 +
3934 +       /* pad oob area, if we have no oob buffer from fs-driver */
3935 +       if (!oob_buf) {
3936 +               oob_data = &this->data_buf[mtd->oobblock];
3937 +               for (i = 0; i < mtd->oobsize; i++)
3938 +                       oob_data[i] = 0xff;
3939 +       } else
3940 +               oob_data = oob_buf;
3941 +
3942 +       /* Send command to begin auto page programming */
3943 +
3944 +       memset(oob_data,0xff,mtd->oobsize);
3945 +       /* Write out complete page of data, take care of eccmode */
3946 +       switch (eccmode) {
3947 +       /* No ecc and software ecc 3/256, write all */
3948 +       case NAND_ECC_NONE:
3949 +               printk (KERN_WARNING "Writing data without ECC to NAND-FLASH is not recommended\n");
3950 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3951 +               break;
3952 +       case NAND_ECC_SOFT:
3953 +               break;
3954 +
3955 +       /* Hardware ecc 3 byte / 256 data, write first half, get ecc, then second, if 512 byte pagesize */
3956 +       case NAND_ECC_HW3_256:
3957 +               break;
3958 +
3959 +       /* Hardware ecc 3 byte / 512 byte data, write full page */
3960 +       case NAND_ECC_HW3_512:
3961 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x80000001); //set 31b = 0
3962 +
3963 +       /* Hardware ecc 6 byte / 512 byte data, write full page */
3964 +       case NAND_ECC_HW6_512:
3965 +               break;
3966 +
3967 +       default:
3968 +               printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
3969 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
3970 +               //BUG();
3971 +       }
3972 +
3973 +       FLASH_WRITE_REG(NFLASH_ACCESS, NFLASH_DIRECT);
3974 +
3975 +       for(i=0;i<mtd->oobblock;i++)
3976 +       {
3977 +               //udelay(5);
3978 +               FLASH_WRITE_DATA((page*mtd->oobblock)+i,this->data_poi[i]);
3979 +       }
3980 +       ///////////////
3981 +       if(eccmode!=NAND_ECC_NONE)
3982 +       {
3983 +               opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3984 +               while(!(opcode&0x80000000)) //polling flash access 31b
3985 +       {
3986 +                  opcode=FLASH_READ_REG(NFLASH_ECC_STATUS);
3987 +                  //sl2312_flash_delay();
3988 +                  schedule();
3989 +       }
3990 +
3991 +
3992 +       for(i=0;i<(mtd->oobblock/512);i++)
3993 +       {
3994 +               opcode=FLASH_READ_REG(NFLASH_ECC_CODE_GEN0+(i*4));
3995 +
3996 +               for(j=3;j>0;j--)
3997 +                     oob_data[(mtd->oobsize-j-(i*4))] = (opcode<<((4-j)*8)) >>24;
3998 +
3999 +               for(j=0;j<4;j++)
4000 +               {
4001 +                       ecc_code[15-i*4] = opcode;
4002 +                       ecc_code[15-i*4-1] = opcode>>8;
4003 +                       ecc_code[15-i*4-2] = opcode>>16;
4004 +               }
4005 +       }
4006 +
4007 +       //disable ecc
4008 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x00000000);
4009 +
4010 +       /* Write out OOB data */
4011 +       for(i=0;i<mtd->oobsize;i++)
4012 +       {
4013 +               //udelay(5);
4014 +                       FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,oob_data[i]);
4015 +               }
4016 +    }
4017 +    else
4018 +    {
4019 +       for(i=0;i<mtd->oobsize;i++)
4020 +       {
4021 +               //udelay(5);
4022 +                       FLASH_WRITE_DATA((page*mtd->oobblock)+mtd->oobblock+i,0xff);
4023 +               }
4024 +    }
4025 +
4026 +
4027 +       /* call wait ready function */
4028 +       status = this->waitfunc (mtd, this, FL_WRITING);
4029 +       FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4030 +       /* See if device thinks it succeeded */
4031 +       if (status & 0x01) {
4032 +               DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write, page 0x%08x, ", __FUNCTION__, page);
4033 +               FLASH_WRITE_REG(NFLASH_ECC_CONTROL, 0x0); //set 31b = 0
4034 +               return -EIO;
4035 +       }
4036 +
4037 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4038 +       /*
4039 +        * The NAND device assumes that it is always writing to
4040 +        * a cleanly erased page. Hence, it performs its internal
4041 +        * write verification only on bits that transitioned from
4042 +        * 1 to 0. The device does NOT verify the whole page on a
4043 +        * byte by byte basis. It is possible that the page was
4044 +        * not completely erased or the page is becoming unusable
4045 +        * due to wear. The read with ECC would catch the error
4046 +        * later when the ECC page check fails, but we would rather
4047 +        * catch it early in the page write stage. Better to write
4048 +        * no data than invalid data.
4049 +        */
4050 +
4051 +       /* Send command to read back the page */
4052 +       this->cmdfunc (mtd, NAND_CMD_READ0, 0, page);
4053 +       /* Loop through and verify the data */
4054 +       if (this->verify_buf(mtd, this->data_poi, mtd->oobblock)) {
4055 +               DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4056 +               return -EIO;
4057 +       }
4058 +
4059 +       /* check, if we have a fs-supplied oob-buffer */
4060 +       if (oob_buf) {
4061 +               if (this->verify_buf(mtd, oob_data, mtd->oobsize)) {
4062 +                       DEBUG (MTD_DEBUG_LEVEL0, "%s: " "Failed write verify, page 0x%08x ", __FUNCTION__, page);
4063 +                       return -EIO;
4064 +               }
4065 +       } else {
4066 +               if (eccmode != NAND_ECC_NONE) {
4067 +                       int ecc_bytes = 0;
4068 +
4069 +                       switch (this->eccmode) {
4070 +                       case NAND_ECC_SOFT:
4071 +                       case NAND_ECC_HW3_256: ecc_bytes = (mtd->oobblock == 512) ? 6 : 3; break;
4072 +                       case NAND_ECC_HW3_512: ecc_bytes = 3; break;
4073 +                       case NAND_ECC_HW6_512: ecc_bytes = 6; break;
4074 +                       }
4075 +
4076 +
4077 +
4078 +                       for(i=0;i < (mtd->oobblock+mtd->oobsize);i++)
4079 +                       {
4080 +                               if(i>=mtd->oobblock)
4081 +                                       oob_data[i-mtd->oobblock] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4082 +                               else
4083 +                                       oob_data[0] = FLASH_READ_DATA((page*mtd->oobblock) +i);
4084 +                       }
4085 +
4086 +                       if(this->eccmode == NAND_ECC_HW3_512)
4087 +                       {
4088 +                               for(i=0;i<(mtd->oobblock/512);i++)
4089 +                       {
4090 +                               for(j=0;j<3;j++)
4091 +                               {
4092 +                                   if (oob_data[mtd->oobsize-1-j-4*i] != ecc_code[15-j-4*i]) {
4093 +                                                       DEBUG (MTD_DEBUG_LEVEL0,
4094 +                                                              "%s: Failed ECC write "
4095 +                                                      "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
4096 +                                                       return -EIO;
4097 +                                               }
4098 +                               }
4099 +                       }
4100 +                       }
4101 +               }//eccmode != NAND_ECC_NONE
4102 +       }
4103 +       /*
4104 +        * Terminate the read command. This is faster than sending a reset command or
4105 +        * applying a 20us delay before issuing the next programm sequence.
4106 +        * This is not a problem for all chips, but I have found a bunch of them.
4107 +        */
4108 +       //this->select_chip(mtd, -1);
4109 +       //this->select_chip(mtd, 0);
4110 +#endif
4111 +
4112 +       return 0;
4113 +}
4114 +
4115 +/*
4116 + * NAND write with iovec
4117 + */
4118 +static int sl2312_nand_writev (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4119 +               loff_t to, size_t * retlen)
4120 +{
4121 +       return (sl2312_nand_writev_ecc (mtd, vecs, count, to, retlen, NULL, 0));
4122 +}
4123 +
4124 +static int sl2312_nand_writev_ecc (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count,
4125 +               loff_t to, size_t * retlen, u_char *eccbuf, struct nand_oobinfo *oobsel)
4126 +{
4127 +       int i, page, len, total_len, ret = 0, written = 0;
4128 +       struct nand_chip *this = mtd->priv;
4129 +
4130 +       /* Calculate total length of data */
4131 +       total_len = 0;
4132 +       for (i = 0; i < count; i++)
4133 +               total_len += (int) vecs[i].iov_len;
4134 +
4135 +       DEBUG (MTD_DEBUG_LEVEL3,
4136 +              "nand_writev: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
4137 +
4138 +       /* Do not allow write past end of page */
4139 +       if ((to + total_len) > mtd->size) {
4140 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_writev: Attempted write past end of device\n");
4141 +               return -EINVAL;
4142 +       }
4143 +
4144 +       /* reject writes, which are not page aligned */
4145 +       if (NOTALIGNED (to) || NOTALIGNED(total_len)) {
4146 +               printk (KERN_NOTICE "nand_write_ecc: Attempt to write not page aligned data\n");
4147 +               return -EINVAL;
4148 +       }
4149 +
4150 +       // if oobsel is NULL, use chip defaults
4151 +       if (oobsel == NULL)
4152 +               oobsel = &mtd->oobinfo;
4153 +
4154 +       /* Shift to get page */
4155 +       page = ((int) to) >> this->page_shift;
4156 +
4157 +       /* Grab the lock and see if the device is available */
4158 +       sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4159 +
4160 +       /* Select the NAND device */
4161 +       this->select_chip(mtd, 0);
4162 +
4163 +       /* Check the WP bit */
4164 +       if (!(sl2312_device_ready(mtd) & 0x80)) {
4165 +               DEBUG (MTD_DEBUG_LEVEL0, "sl2312_nand_writev_ecc: Device is write protected!!!\n");
4166 +               ret = -EIO;
4167 +               goto out;
4168 +       }
4169 +
4170 +       /* Loop until all iovecs' data has been written */
4171 +       len = 0;
4172 +       while (count) {
4173 +               /*
4174 +                *  Check, if the tuple gives us not enough data for a
4175 +                *  full page write. Then we can use the iov direct,
4176 +                *  else we have to copy into data_buf.
4177 +                */
4178 +               if ((vecs->iov_len - len) >= mtd->oobblock) {
4179 +                       this->data_poi = (u_char *) vecs->iov_base;
4180 +                       this->data_poi += len;
4181 +                       len += mtd->oobblock;
4182 +                       /* Check, if we have to switch to the next tuple */
4183 +                       if (len >= (int) vecs->iov_len) {
4184 +                               vecs++;
4185 +                               len = 0;
4186 +                               count--;
4187 +                       }
4188 +               } else {
4189 +                       /*
4190 +                        * Read data out of each tuple until we have a full page
4191 +                        * to write or we've read all the tuples.
4192 +                       */
4193 +                       int cnt = 0;
4194 +                       while ((cnt < mtd->oobblock) && count) {
4195 +                               if (vecs->iov_base != NULL && vecs->iov_len) {
4196 +                                       this->data_buf[cnt++] = ((u_char *) vecs->iov_base)[len++];
4197 +                               }
4198 +                               /* Check, if we have to switch to the next tuple */
4199 +                               if (len >= (int) vecs->iov_len) {
4200 +                                       vecs++;
4201 +                                       len = 0;
4202 +                                       count--;
4203 +                               }
4204 +                       }
4205 +                       this->data_poi = this->data_buf;
4206 +               }
4207 +
4208 +               /* We use the same function for write and writev !) */
4209 +               ret = sl2312_nand_write_page (mtd, this, page, NULL, oobsel);
4210 +               if (ret)
4211 +                       goto out;
4212 +
4213 +               /* Update written bytes count */
4214 +               written += mtd->oobblock;;
4215 +
4216 +               /* Increment page address */
4217 +               page++;
4218 +       }
4219 +
4220 +out:
4221 +       /* De-select the NAND device */
4222 +       //this->select_chip(mtd, -1);
4223 +
4224 +       /* Wake up anyone waiting on the device */
4225 +       spin_lock_bh (&this->chip_lock);
4226 +       this->state = FL_READY;
4227 +       wake_up (&this->wq);
4228 +       spin_unlock_bh (&this->chip_lock);
4229 +
4230 +       *retlen = written;
4231 +       return ret;
4232 +}
4233 +
4234 +/*
4235 +static u_char ffchars[] = {
4236 +       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
4237 +       0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
4238 +};
4239 +*/
4240 +/*
4241 + * NAND write out-of-band
4242 + */
4243 +static int sl2312_nand_write_oob (struct mtd_info *mtd, loff_t to, size_t len, size_t * retlen, const u_char * buf)
4244 +{
4245 +       int column, page, status, ret = 0, j=0;
4246 +       struct nand_chip *this = mtd->priv;
4247 +       u_char *databuf, *oobbuf;
4248 +
4249 +
4250 +               databuf = &this->data_buf[0];
4251 +               oobbuf = &this->data_buf[mtd->oobblock];
4252 +               for (j = 0; j < mtd->oobsize; j++)
4253 +                       oobbuf[j] = 0xff;
4254 +//#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
4255 +//     int     i;
4256 +//#endif
4257 +
4258 +       DEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
4259 +
4260 +       /* Shift to get page */
4261 +       page = ((int) to) >> this->page_shift;
4262 +
4263 +       /* Mask to get column */
4264 +       column = to & 0x1f;
4265 +
4266 +       /* Initialize return length value */
4267 +       *retlen = 0;
4268 +
4269 +       /* Do not allow write past end of page */
4270 +       if ((column + len) > mtd->oobsize) {
4271 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Attempt to write past end of page\n");
4272 +               return -EINVAL;
4273 +       }
4274 +
4275 +       /* Grab the lock and see if the device is available */
4276 +       sl2312_nand_get_chip (this, mtd, FL_WRITING, NULL);
4277 +
4278 +       /* Select the NAND device */
4279 +       this->select_chip(mtd, 0);
4280 +
4281 +       /* Reset the chip. Some chips (like the Toshiba TC5832DC found
4282 +          in one of my DiskOnChip 2000 test units) will clear the whole
4283 +          data page too if we don't do this. I have no clue why, but
4284 +          I seem to have 'fixed' it in the doc2000 driver in
4285 +          August 1999.  dwmw2. */
4286 +       this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
4287 +
4288 +       /* Check the WP bit */
4289 +       if (!(sl2312_device_ready(mtd) & 0x80)) {
4290 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: Device is write protected!!!\n");
4291 +               ret = -EIO;
4292 +               goto out;
4293 +       }
4294 +       /* Write out desired data */
4295 +       this->cmdfunc (mtd, NAND_CMD_SEQIN, mtd->oobblock, page);
4296 +
4297 +       sl2312_nand_read_ecc (mtd, page, mtd->oobblock , retlen, databuf, oobbuf, NULL);
4298 +
4299 +    for(j=column;j<(column+len);j++)
4300 +       oobbuf[j] = buf[j-column];
4301 +    sl2312_nand_write_ecc (mtd, page, mtd->oobblock, retlen, databuf, oobbuf, NULL);
4302 +
4303 +       status = this->waitfunc (mtd, this, FL_WRITING);
4304 +
4305 +       /* See if device thinks it succeeded */
4306 +       if (status & 0x01) {
4307 +               DEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: " "Failed write, page 0x%08x\n", page);
4308 +               ret = -EIO;
4309 +               goto out;
4310 +       }
4311 +       /* Return happy */
4312 +       *retlen = len;
4313 +
4314 +
4315 +out:
4316 +       /* De-select the NAND device */
4317 +       //this->select_chip(mtd, -1);
4318 +
4319 +       /* Wake up anyone waiting on the device */
4320 +       spin_lock_bh (&this->chip_lock);
4321 +       this->state = FL_READY;
4322 +       wake_up (&this->wq);
4323 +       spin_unlock_bh (&this->chip_lock);
4324 +
4325 +       return ret;
4326 +}
4327 +
4328 +/*
4329 + * NAND sync
4330 + */
4331 +static void sl2312_nand_sync (struct mtd_info *mtd)
4332 +{
4333 +       struct nand_chip *this = mtd->priv;
4334 +       DECLARE_WAITQUEUE (wait, current);
4335 +
4336 +       DEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
4337 +
4338 +retry:
4339 +       /* Grab the spinlock */
4340 +       spin_lock_bh (&this->chip_lock);
4341 +
4342 +       /* See what's going on */
4343 +       switch (this->state) {
4344 +       case FL_READY:
4345 +       case FL_SYNCING:
4346 +               this->state = FL_SYNCING;
4347 +               spin_unlock_bh (&this->chip_lock);
4348 +               break;
4349 +
4350 +       default:
4351 +               /* Not an idle state */
4352 +               add_wait_queue (&this->wq, &wait);
4353 +               spin_unlock_bh (&this->chip_lock);
4354 +               schedule ();
4355 +
4356 +               remove_wait_queue (&this->wq, &wait);
4357 +               goto retry;
4358 +       }
4359 +
4360 +       /* Lock the device */
4361 +       spin_lock_bh (&this->chip_lock);
4362 +
4363 +       /* Set the device to be ready again */
4364 +       if (this->state == FL_SYNCING) {
4365 +               this->state = FL_READY;
4366 +               wake_up (&this->wq);
4367 +       }
4368 +
4369 +       /* Unlock the device */
4370 +       spin_unlock_bh (&this->chip_lock);
4371 +}
4372 +
4373 +
4374 +/*
4375 + * Scan for the NAND device
4376 + */
4377 +int sl2312_nand_scan (struct mtd_info *mtd, int maxchips)
4378 +{
4379 +       int i, j, nand_maf_id, nand_dev_id, busw;
4380 +       struct nand_chip *this = mtd->priv;
4381 +       unsigned char id[4];
4382 +
4383 +       /* Get buswidth to select the correct functions*/
4384 +       busw = this->options & NAND_BUSWIDTH_16;
4385 +
4386 +       /* check for proper chip_delay setup, set 20us if not */
4387 +       if (!this->chip_delay)
4388 +               this->chip_delay = 20;
4389 +
4390 +       /* check, if a user supplied command function given */
4391 +       if (this->cmdfunc == NULL)
4392 +               this->cmdfunc = sl2312_nand_command;
4393 +
4394 +       /* check, if a user supplied wait function given */
4395 +       if (this->waitfunc == NULL)
4396 +               this->waitfunc = sl2312_nand_waitfunc;
4397 +
4398 +       if (!this->select_chip)
4399 +               this->select_chip = sl2312_nand_select_chip;
4400 +       if (!this->write_byte)
4401 +               this->write_byte = sl2312_nand_write_byte; //busw ? nand_write_byte16 : nand_write_byte;
4402 +       if (!this->read_byte)
4403 +               this->read_byte = sl2312_nand_read_byte; //busw ? nand_read_byte16 : nand_read_byte;
4404 +//     if (!this->write_word)
4405 +//             this->write_word = nand_write_word;
4406 +//     if (!this->read_word)
4407 +//             this->read_word = nand_read_word;
4408 +//     if (!this->block_bad)
4409 +               this->block_bad = sl2312_nand_block_bad; //nand_block_bad;
4410 +       if (!this->block_markbad)
4411 +               this->block_markbad = sl2312_nand_default_block_markbad;
4412 +       if (!this->write_buf)
4413 +               this->write_buf = sl2312_nand_write_buf; //busw ? nand_write_buf16 : nand_write_buf;
4414 +       if (!this->read_buf)
4415 +               this->read_buf = sl2312_nand_read_buf; //busw ? nand_read_buf16 : nand_read_buf;
4416 +       if (!this->verify_buf)
4417 +               this->verify_buf = sl2312_nand_verify_buf; //busw ? nand_verify_buf16 : nand_verify_buf;
4418 +       if (!this->scan_bbt)
4419 +               this->scan_bbt = sl2312_nand_scan_bbt;
4420 +
4421 +       /* Select the device */
4422 +       this->select_chip(mtd, 0);
4423 +
4424 +       /* Read manufacturer and device IDs */
4425 +       nand_read_id(0,id);
4426 +
4427 +       nand_maf_id = id[0];
4428 +       nand_dev_id = id[1];
4429 +
4430 +       /* Print and store flash device information */
4431 +       for (i = 0; nand_flash_ids[i].name != NULL; i++) {
4432 +
4433 +               if (nand_dev_id != nand_flash_ids[i].id)
4434 +                       continue;
4435 +
4436 +               if (!mtd->name) mtd->name = nand_flash_ids[i].name;
4437 +               this->chipsize = nand_flash_ids[i].chipsize << 20;
4438 +
4439 +               /* New devices have all the information in additional id bytes */
4440 +               if (!nand_flash_ids[i].pagesize) {
4441 +                       int extid;
4442 +
4443 +                       /* The 4th id byte is the important one */
4444 +                       extid = id[3];
4445 +                       /* Calc pagesize */
4446 +                       mtd->oobblock = 1024 << (extid & 0x3);
4447 +                       extid >>= 2;
4448 +                       /* Calc oobsize */
4449 +                       mtd->oobsize = (8 << (extid & 0x03)) * (mtd->oobblock / 512);
4450 +                       extid >>= 2;
4451 +                       /* Calc blocksize. Blocksize is multiples of 64KiB */
4452 +                       mtd->erasesize = (64 * 1024)  << (extid & 0x03);
4453 +                       extid >>= 2;
4454 +                       /* Get buswidth information */
4455 +                       busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
4456 +
4457 +               } else {
4458 +                       /* Old devices have this data hardcoded in the
4459 +                        * device id table */
4460 +                       mtd->erasesize = nand_flash_ids[i].erasesize;
4461 +                       mtd->oobblock = nand_flash_ids[i].pagesize;
4462 +                       mtd->oobsize = mtd->oobblock / 32;
4463 +                       busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
4464 +               }
4465 +
4466 +               /* Check, if buswidth is correct. Hardware drivers should set
4467 +                * this correct ! */
4468 +               if (busw != (this->options & NAND_BUSWIDTH_16)) {
4469 +                       printk (KERN_INFO "NAND device: Manufacturer ID:"
4470 +                               " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4471 +                               nand_manuf_ids[i].name , mtd->name);
4472 +                       printk (KERN_WARNING
4473 +                               "NAND bus width %d instead %d bit\n",
4474 +                                       (this->options & NAND_BUSWIDTH_16) ? 16 : 8,
4475 +                                       busw ? 16 : 8);
4476 +                       this->select_chip(mtd, -1);
4477 +                       return 1;
4478 +               }
4479 +
4480 +               /* Calculate the address shift from the page size */
4481 +               this->page_shift = ffs(mtd->oobblock) - 1;
4482 +               this->bbt_erase_shift = this->phys_erase_shift = ffs(mtd->erasesize) - 1;
4483 +               this->chip_shift = ffs(this->chipsize) - 1;
4484 +
4485 +               /* Set the bad block position */
4486 +               this->badblockpos = mtd->oobblock > 512 ?
4487 +                       NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
4488 +
4489 +               /* Get chip options, preserve non chip based options */
4490 +               this->options &= ~NAND_CHIPOPTIONS_MSK;
4491 +               this->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
4492 +               /* Set this as a default. Board drivers can override it, if neccecary */
4493 +               this->options |= NAND_NO_AUTOINCR;
4494 +               /* Check if this is a not a samsung device. Do not clear the options
4495 +                * for chips which are not having an extended id.
4496 +                */
4497 +               if (nand_maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
4498 +                       this->options &= ~NAND_SAMSUNG_LP_OPTIONS;
4499 +
4500 +               /* Check for AND chips with 4 page planes */
4501 +       //      if (this->options & NAND_4PAGE_ARRAY)
4502 +       //              this->erase_cmd = multi_erase_cmd;
4503 +       //      else
4504 +       //              this->erase_cmd = single_erase_cmd;
4505 +
4506 +               /* Do not replace user supplied command function ! */
4507 +       //      if (mtd->oobblock > 512 && this->cmdfunc == nand_command)
4508 +       //              this->cmdfunc = nand_command_lp;
4509 +
4510 +               /* Try to identify manufacturer */
4511 +               for (j = 0; nand_manuf_ids[j].id != 0x0; j++) {
4512 +                       if (nand_manuf_ids[j].id == nand_maf_id)
4513 +                               break;
4514 +               }
4515 +               printk (KERN_INFO "NAND device: Manufacturer ID:"
4516 +                       " 0x%02x, Chip ID: 0x%02x (%s %s)\n", nand_maf_id, nand_dev_id,
4517 +                       nand_manuf_ids[j].name , nand_flash_ids[i].name);
4518 +               break;
4519 +       }
4520 +       /////////////////////////////
4521 +
4522 +       for (i=1; i < maxchips; i++) {
4523 +               this->select_chip(mtd, i);
4524 +
4525 +               /* Send the command for reading device ID */
4526 +               nand_read_id(1,id);
4527 +
4528 +               /* Read manufacturer and device IDs */
4529 +               if (nand_maf_id != id[0] ||
4530 +                   nand_dev_id != id[1])
4531 +                       break;
4532 +       }
4533 +       if (i > 1)
4534 +               printk(KERN_INFO "%d NAND chips detected\n", i);
4535 +
4536 +       /* Allocate buffers, if neccecary */
4537 +       if (!this->oob_buf) {
4538 +               size_t len;
4539 +               len = mtd->oobsize << (this->phys_erase_shift - this->page_shift);
4540 +               this->oob_buf = kmalloc (len, GFP_KERNEL);
4541 +               if (!this->oob_buf) {
4542 +                       printk (KERN_ERR "nand_scan(): Cannot allocate oob_buf\n");
4543 +                       return -ENOMEM;
4544 +               }
4545 +               this->options |= NAND_OOBBUF_ALLOC;
4546 +       }
4547 +
4548 +       if (!this->data_buf) {
4549 +               size_t len;
4550 +               len = mtd->oobblock + mtd->oobsize;
4551 +               this->data_buf = kmalloc (len, GFP_KERNEL);
4552 +               if (!this->data_buf) {
4553 +                       if (this->options & NAND_OOBBUF_ALLOC)
4554 +                               kfree (this->oob_buf);
4555 +                       printk (KERN_ERR "nand_scan(): Cannot allocate data_buf\n");
4556 +                       return -ENOMEM;
4557 +               }
4558 +               this->options |= NAND_DATABUF_ALLOC;
4559 +       }
4560 +
4561 +       /* Store the number of chips and calc total size for mtd */
4562 +       this->numchips = i;
4563 +       mtd->size = i * this->chipsize;
4564 +       /* Convert chipsize to number of pages per chip -1. */
4565 +       this->pagemask = (this->chipsize >> this->page_shift) - 1;
4566 +       /* Preset the internal oob buffer */
4567 +       memset(this->oob_buf, 0xff, mtd->oobsize << (this->phys_erase_shift - this->page_shift));
4568 +
4569 +       /* If no default placement scheme is given, select an
4570 +        * appropriate one */
4571 +       if (!this->autooob) {
4572 +               /* Select the appropriate default oob placement scheme for
4573 +                * placement agnostic filesystems */
4574 +               switch (mtd->oobsize) {
4575 +               case 8:
4576 +                       this->autooob = &nand_oob_8;
4577 +                       break;
4578 +               case 16:
4579 +                       this->autooob = &nand_oob_16;
4580 +                       break;
4581 +               case 64:
4582 +                       this->autooob = &nand_oob_64;
4583 +                       break;
4584 +               default:
4585 +                       printk (KERN_WARNING "No oob scheme defined for oobsize %d\n",
4586 +                               mtd->oobsize);
4587 +                       BUG();
4588 +               }
4589 +       }
4590 +
4591 +       /* The number of bytes available for the filesystem to place fs dependend
4592 +        * oob data */
4593 +       if (this->options & NAND_BUSWIDTH_16) {
4594 +               mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2);
4595 +               if (this->autooob->eccbytes & 0x01)
4596 +                       mtd->oobavail--;
4597 +       } else
4598 +               mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1);
4599 +
4600 +
4601 +       /*
4602 +        * check ECC mode, default to software
4603 +        * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize
4604 +        * fallback to software ECC
4605 +       */
4606 +       this->eccsize = 256;    /* set default eccsize */
4607 +       this->eccbytes = 3;
4608 +
4609 +       switch (this->eccmode) {
4610 +       case NAND_ECC_HW12_2048:
4611 +               if (mtd->oobblock < 2048) {
4612 +                       printk(KERN_WARNING "2048 byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
4613 +                              mtd->oobblock);
4614 +                       this->eccmode = NAND_ECC_SOFT;
4615 +                       this->calculate_ecc = nand_calculate_ecc;
4616 +                       this->correct_data = nand_correct_data;
4617 +               } else
4618 +                       this->eccsize = 2048;
4619 +               break;
4620 +
4621 +       case NAND_ECC_HW3_512:
4622 +       case NAND_ECC_HW6_512:
4623 +       case NAND_ECC_HW8_512:
4624 +               if (mtd->oobblock == 256) {
4625 +                       printk (KERN_WARNING "512 byte HW ECC not possible on 256 Byte pagesize, fallback to SW ECC \n");
4626 +                       this->eccmode = NAND_ECC_SOFT;
4627 +                       this->calculate_ecc = nand_calculate_ecc;
4628 +                       this->correct_data = nand_correct_data;
4629 +               } else
4630 +                       this->eccsize = 512; /* set eccsize to 512 */
4631 +               break;
4632 +
4633 +       case NAND_ECC_HW3_256:
4634 +               break;
4635 +
4636 +       case NAND_ECC_NONE:
4637 +               printk (KERN_WARNING "NAND_ECC_NONE selected by board driver. This is not recommended !!\n");
4638 +               this->eccmode = NAND_ECC_NONE;
4639 +               break;
4640 +
4641 +       case NAND_ECC_SOFT:
4642 +               this->calculate_ecc = nand_calculate_ecc;
4643 +               this->correct_data = nand_correct_data;
4644 +               break;
4645 +
4646 +       default:
4647 +               printk (KERN_WARNING "Invalid NAND_ECC_MODE %d\n", this->eccmode);
4648 +               BUG();
4649 +       }
4650 +
4651 +       /* Check hardware ecc function availability and adjust number of ecc bytes per
4652 +        * calculation step
4653 +       */
4654 +       switch (this->eccmode) {
4655 +       case NAND_ECC_HW12_2048:
4656 +               this->eccbytes += 4;
4657 +       case NAND_ECC_HW8_512:
4658 +               this->eccbytes += 2;
4659 +       case NAND_ECC_HW6_512:
4660 +               this->eccbytes += 3;
4661 +//     case NAND_ECC_HW3_512:
4662 +       case NAND_ECC_HW3_256:
4663 +               if (this->calculate_ecc && this->correct_data && this->enable_hwecc)
4664 +                       break;
4665 +               printk (KERN_WARNING "No ECC functions supplied, Hardware ECC not possible\n");
4666 +               BUG();
4667 +       }
4668 +
4669 +       mtd->eccsize = this->eccsize;
4670 +
4671 +       /* Set the number of read / write steps for one page to ensure ECC generation */
4672 +       switch (this->eccmode) {
4673 +       case NAND_ECC_HW12_2048:
4674 +               this->eccsteps = mtd->oobblock / 2048;
4675 +               break;
4676 +       case NAND_ECC_HW3_512:
4677 +       case NAND_ECC_HW6_512:
4678 +       case NAND_ECC_HW8_512:
4679 +               this->eccsteps = mtd->oobblock / 512;
4680 +               break;
4681 +       case NAND_ECC_HW3_256:
4682 +       case NAND_ECC_SOFT:
4683 +               this->eccsteps = mtd->oobblock / 256;
4684 +               break;
4685 +
4686 +       case NAND_ECC_NONE:
4687 +               this->eccsteps = 1;
4688 +               break;
4689 +       }
4690 +
4691 +       /* Initialize state, waitqueue and spinlock */
4692 +       this->state = FL_READY;
4693 +       init_waitqueue_head (&this->wq);
4694 +       spin_lock_init (&this->chip_lock);
4695 +
4696 +       /* De-select the device */
4697 +       this->select_chip(mtd, 0);
4698 +
4699 +       /* Print warning message for no device */
4700 +       if (!mtd->size) {
4701 +               printk (KERN_WARNING "No NAND device found!!!\n");
4702 +               return 1;
4703 +       }
4704 +
4705 +       /* Fill in remaining MTD driver data */
4706 +       mtd->type = MTD_NANDFLASH;
4707 +       mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
4708 +       mtd->ecctype = MTD_ECC_SW;
4709 +       mtd->erase = sl2312_nand_erase;
4710 +       mtd->point = NULL;
4711 +       mtd->unpoint = NULL;
4712 +       mtd->read = sl2312_nand_read;
4713 +       mtd->write = sl2312_nand_write;
4714 +       mtd->read_ecc = sl2312_nand_read_ecc;
4715 +       mtd->write_ecc = sl2312_nand_write_ecc;
4716 +       mtd->read_oob = sl2312_nand_read_oob;
4717 +       mtd->write_oob = sl2312_nand_write_oob;
4718 +       mtd->readv = NULL;
4719 +       mtd->writev = sl2312_nand_writev;
4720 +       mtd->writev_ecc = sl2312_nand_writev_ecc;
4721 +       mtd->sync = sl2312_nand_sync;
4722 +       mtd->lock = NULL;
4723 +       mtd->unlock = NULL;
4724 +       mtd->suspend = NULL;
4725 +       mtd->resume = NULL;
4726 +       mtd->block_isbad = sl2312_nand_block_isbad;
4727 +       mtd->block_markbad = sl2312_nand_block_markbad;
4728 +
4729 +       /* and make the autooob the default one */
4730 +       memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
4731 +
4732 +       mtd->owner = THIS_MODULE;
4733 +
4734 +       /* Build bad block table */
4735 +       return this->scan_bbt (mtd);
4736 +}
4737 +
4738 +/*End Add function*/
4739 +
4740 +/*
4741 + * Main initialization routine
4742 + */
4743 +extern int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
4744 +
4745 +int __init sl2312_mtd_init (void)
4746 +{
4747 +       struct nand_chip *this;
4748 +       int err = 0;
4749 +       struct mtd_partition *parts;
4750 +       int nr_parts = 0;
4751 +       int ret, data, *base;
4752 +
4753 +       printk("NAND MTD Driver Start Init ......\n");
4754 +
4755 +       base = (unsigned int *)(IO_ADDRESS(SL2312_GLOBAL_BASE) + 0x30);
4756 +       data = *base;
4757 +       data&=0xffffffeb;
4758 +       data|=0x3; //disable p & s flash
4759 +        *base = data;
4760 +
4761 +       /* Allocate memory for MTD device structure and private data */
4762 +       sl2312_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
4763 +       if (!sl2312_mtd) {
4764 +               printk ("Unable to allocate SL2312 NAND MTD device structure.\n");
4765 +               err = -ENOMEM;
4766 +               goto out;
4767 +       }
4768 +
4769 +      //  sl2312_device_setup();
4770 +
4771 +       /* io is indirect via a register so don't need to ioremap address */
4772 +
4773 +       /* Get pointer to private data */
4774 +       this = (struct nand_chip *) (&sl2312_mtd[1]);
4775 +
4776 +       /* Initialize structures */
4777 +       memset((char *) sl2312_mtd, 0, sizeof(struct mtd_info));
4778 +       memset((char *) this, 0, sizeof(struct nand_chip));
4779 +
4780 +       /* Link the private data with the MTD structure */
4781 +       sl2312_mtd->priv = this;
4782 +       sl2312_mtd->name = "sl2312-nand";
4783 +
4784 +       /* Set address of NAND IO lines */
4785 +       this->IO_ADDR_R = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4786 +       this->IO_ADDR_W = (void __iomem *)IO_ADDRESS((SL2312_FLASH_CTRL_BASE+NFLASH_DATA)); //(unsigned long)&(sl2312_ndfmcptr->dtr);
4787 +       this->read_byte = sl2312_nand_read_byte;
4788 +    this->write_byte = sl2312_nand_write_byte;
4789 +    this->write_buf = sl2312_nand_write_buf;
4790 +       this->read_buf = sl2312_nand_read_buf;
4791 +       this->verify_buf = sl2312_nand_verify_buf;
4792 +       this->select_chip = sl2312_nand_select_chip;
4793 +       this->block_bad = sl2312_nand_block_bad;
4794 +       this->hwcontrol = sl2312_hwcontrol;
4795 +       this->dev_ready = sl2312_device_ready;
4796 +       this->cmdfunc = sl2312_nand_command;
4797 +       this->waitfunc = sl2312_nand_waitfunc;
4798 +       //this->calculate_ecc = sl2312_readecc;
4799 +       this->enable_hwecc = sl2312_enable_hwecc;
4800 +       this->eccmode = NAND_ECC_HW3_512;
4801 +       /*this->eccsize = 512;  */
4802 +       /* 20 us command delay time */
4803 +       this->chip_delay = 20;
4804 +
4805 +       this->correct_data = nand_correct_data;
4806 +//     this->scan_bbt = sl2312_nand_scan_bbt;
4807 +
4808 +       /* Allocate memory for internal data buffer */
4809 +       this->data_buf = kmalloc (sizeof(u_char) * (sl2312_mtd->oobblock + sl2312_mtd->oobsize), GFP_KERNEL);
4810 +       if (!this->data_buf) {
4811 +               printk ("Unable to allocate NAND data buffer.\n");
4812 +               err = -ENOMEM;
4813 +               goto out_ior;
4814 +       }
4815 +
4816 +       /* Scan to find existance of the device */
4817 +       if (sl2312_nand_scan(sl2312_mtd, 1)) {
4818 +               err = -ENXIO;
4819 +               goto out_ior;
4820 +       }
4821 +
4822 +       /* Register the partitions */
4823 +       parts = sl2312_partitions;
4824 +       nr_parts = sizeof(sl2312_partitions)/sizeof(*parts);
4825 +
4826 +       ret = add_mtd_partitions(sl2312_mtd, sl2312_partitions, nr_parts);
4827 +       /*If we got an error, free all resources.*/
4828 +       if (ret < 0) {
4829 +               del_mtd_partitions(sl2312_mtd);
4830 +               map_destroy(sl2312_mtd);
4831 +       }
4832 +       goto out;
4833 +
4834 +//out_buf:
4835 +//     kfree (this->data_buf);
4836 +out_ior:
4837 +out:
4838 +       printk("NAND MTD Driver Init Success ......\n");
4839 +       return err;
4840 +}
4841 +
4842 +module_init(sl2312_mtd_init);
4843 +
4844 +/*
4845 + * Clean up routine
4846 + */
4847 +#ifdef MODULE
4848 +static void __exit sl2312_cleanup (void)
4849 +{
4850 +       struct nand_chip *this = (struct nand_chip *) &sl2312_mtd[1];
4851 +
4852 +       /* Unregister partitions */
4853 +       del_mtd_partitions(sl2312_mtd);
4854 +
4855 +       /* Unregister the device */
4856 +       del_mtd_device (sl2312_mtd);
4857 +
4858 +       /* Free internal data buffers */
4859 +       kfree (this->data_buf);
4860 +
4861 +       /* Free the MTD device structure */
4862 +       kfree (sl2312_mtd);
4863 +}
4864 +module_exit(sl2312_cleanup);
4865 +#endif
4866 +
4867 +MODULE_LICENSE("GPL");
4868 +MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
4869 +MODULE_DESCRIPTION("Glue layer for SmartMediaCard on Toshiba RBsl2312");
4870 --- /dev/null
4871 +++ b/drivers/mtd/nand/sl2312-flash-nand.h
4872 @@ -0,0 +1,24 @@
4873 +#ifndef SL2312_FLASH_NAND_H
4874 +#define SL2312_FLASH_NAND_H
4875 +
4876 +#include <linux/wait.h>\r
4877 +#include <linux/spinlock.h>
4878 +
4879 +/*Add function*/
4880 +static void nand_read_id(int chip_no,unsigned char *id);
4881 +\r
4882 +\r
4883 +\r
4884 +#define        NFLASH_WiDTH8              0x00000000
4885 +#define        NFLASH_WiDTH16             0x00000400
4886 +#define        NFLASH_WiDTH32             0x00000800\r
4887 +#define NFLASH_CHIP0_EN            0x00000000  // 16th bit = 0
4888 +#define NFLASH_CHIP1_EN            0x00010000  // 16th bit = 1
4889 +#define        NFLASH_DIRECT              0x00004000
4890 +#define        NFLASH_INDIRECT            0x00000000\r
4891 +\r
4892 +\r
4893 +#define        DWIDTH             NFLASH_WiDTH8\r
4894 +\r
4895 +
4896 +#endif /* SL2312_FLASH_NAND_H */
4897 --- /dev/null
4898 +++ b/include/linux/mtd/kvctl.h
4899 @@ -0,0 +1,40 @@
4900 +#ifndef KVCTL_H
4901 +#define KVCTL_H
4902 +
4903 +#define VCTL_HEAD_SIZE 8
4904 +#define VCTL_ENTRY_LEN 20
4905 +
4906 +typedef struct
4907 +{
4908 +  char header[4];
4909 +  unsigned int entry_num;
4910 +} vctl_mheader;
4911 +
4912 +typedef struct
4913 +{
4914 +  char header[4];
4915 +  unsigned int size;
4916 +  unsigned int type;
4917 +  char majorver[4];
4918 +  char minorver[4];
4919 +  unsigned char *payload;
4920 +} vctl_entry;
4921 +
4922 +typedef struct
4923 +{
4924 +  unsigned char mac[6];
4925 +  unsigned char vlanid;
4926 +  unsigned char vlanmap;
4927 +} vlaninfo;
4928 +
4929 +#define VCT_VENDORSPEC         0
4930 +#define VCT_BOOTLOADER         1
4931 +#define VCT_KERNEL             2
4932 +#define VCT_VERCTL             3
4933 +#define VCT_CURRCONF           4
4934 +#define VCT_DEFAULTCONF                5
4935 +#define VCT_ROOTFS             6
4936 +#define VCT_APP                        7
4937 +#define VCT_VLAN               8
4938 +
4939 +#endif
4940 --- a/drivers/mtd/maps/Makefile
4941 +++ b/drivers/mtd/maps/Makefile
4942 @@ -71,3 +71,7 @@
4943  obj-$(CONFIG_MTD_OMAP_NOR)     += omap_nor.o
4944  obj-$(CONFIG_MTD_MTX1)         += mtx-1_flash.o
4945  obj-$(CONFIG_MTD_TQM834x)      += tqm834x.o
4946 +###### for Storlink Soc #######
4947 +obj-$(CONFIG_MTD_SL2312_CFI) += sl2312-flash-cfi.o
4948 +obj-$(CONFIG_MTD_SL2312_SERIAL_ATMEL) += sl2312-flash-atmel.o
4949 +obj-$(CONFIG_MTD_SL2312_SERIAL_ST) += sl2312-flash-m25p80.o