4 #include <linux/mfd/glamo.h>
6 /* for the time being, we put the on-screen framebuffer into the lowest
7 * VRAM space. This should make the code easily compatible with the various
8 * 2MB/4MB/8MB variants of the Smedia chips */
9 #define GLAMO_OFFSET_VRAM 0x800000
10 #define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM)
12 /* we only allocate the minimum possible size for the framebuffer to make
13 * sure we have sufficient memory for other functions of the chip */
14 //#define GLAMO_FB_SIZE (640*480*4) /* == 0x12c000 */
15 #define GLAMO_INTERNAL_RAM_SIZE 0x800000
16 #define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
17 #define GLAMO_FB_SIZE (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
24 enum glamo_engine_state {
25 GLAMO_ENGINE_DISABLED,
26 GLAMO_ENGINE_SUSPENDED,
33 int irq_works; /* 0 means PCB does not support Glamo IRQ */
36 struct platform_device *pdev;
37 struct glamo_platform_data *pdata;
38 enum glamo_engine_state engine_state[__NUM_GLAMO_ENGINES];
47 int glamo_pll_rate(struct glamo_core *glamo, enum glamo_pll pll);
49 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
50 int glamo_engine_suspend(struct glamo_core *glamo, enum glamo_engine engine);
51 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
52 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
53 int glamo_engine_reclock(struct glamo_core *glamo,
54 enum glamo_engine engine, int ps);
56 void glamo_reg_read_batch(struct glamo_core *glamo, uint16_t reg,
57 uint16_t count, uint16_t *values);
58 void glamo_reg_write_batch(struct glamo_core *glamo, uint16_t reg,
59 uint16_t count, uint16_t *values);
60 #endif /* __GLAMO_CORE_H */