target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.c

   1 /* Smedia Glamo 336x/337x driver
   2  *
   3  * (C) 2007 by Openmoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/init.h>
  31 #include <linux/irq.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/kernel_stat.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/mfd/core.h>
  38 #include <linux/mfd/glamo.h>
  39 #include <linux/glamofb.h>
  40 #include <linux/io.h>
  41
  42 #include <asm/div64.h>
  43
  44 #include <linux/pm.h>
  45
  46 #include "glamo-regs.h"
  47 #include "glamo-core.h"
  48
  49 #define GLAMO_MEM_REFRESH_COUNT 0x100
  50
  51 /*
  52  * Glamo internal settings
  53  *
  54  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
  55  * above.  Couple of GTA02 users report trouble with memory bus when they
  56  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
  57  * scheme if their Glamo chip needs it.
  58  *
  59  * you can override the faster default on kernel commandline using
  60  *
  61  *   glamo3362.slow_memory=1
  62  *
  63  * for example
  64  */
  65
  66 static int slow_memory = 0;
  67 module_param(slow_memory, int, 0644);
  68
  69 struct reg_range {
  70         int start;
  71         int count;
  72         char *name;
  73         char dump;
  74 };
  75
  76 struct reg_range reg_range[] = {
  77         { 0x0000, 0x76,         "General",      1 },
  78         { 0x0200, 0x18,         "Host Bus",     1 },
  79         { 0x0300, 0x38,         "Memory",       1 },
  80 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
  81 /*              { 0x0500, 0x300,        "ISP",          0 }, */
  82 /*              { 0x0800, 0x400,        "JPEG",         0 }, */
  83 /*              { 0x0c00, 0xcc,         "MPEG",         0 }, */
  84         { 0x1100, 0xb2,         "LCD 1",        1 },
  85         { 0x1200, 0x64,         "LCD 2",        1 },
  86         { 0x1400, 0x42,         "MMC",          1 },
  87 /*              { 0x1500, 0x080,        "MPU 0",        0 },
  88         { 0x1580, 0x080,        "MPU 1",        0 },
  89         { 0x1600, 0x080,        "Cmd Queue",    0 },
  90         { 0x1680, 0x080,        "RISC CPU",     0 },*/
  91         { 0x1700, 0x400,        "2D Unit",      0 },
  92 /*      { 0x1b00, 0x900,        "3D Unit",      0 }, */
  93 };
  94
  95 static inline void __reg_write(struct glamo_core *glamo,
  96                                 u_int16_t reg, u_int16_t val)
  97 {
  98         writew(val, glamo->base + reg);
  99 }
 100
 101 static inline u_int16_t __reg_read(struct glamo_core *glamo,
 102                                    u_int16_t reg)
 103 {
 104         return readw(glamo->base + reg);
 105 }
 106
 107 static void __reg_set_bit_mask(struct glamo_core *glamo,
 108                                 u_int16_t reg, u_int16_t mask,
 109                                 u_int16_t val)
 110 {
 111         u_int16_t tmp;
 112
 113         val &= mask;
 114
 115         tmp = __reg_read(glamo, reg);
 116         tmp &= ~mask;
 117         tmp |= val;
 118         __reg_write(glamo, reg, tmp);
 119 }
 120
 121 static void reg_set_bit_mask(struct glamo_core *glamo,
 122                                 u_int16_t reg, u_int16_t mask,
 123                                 u_int16_t val)
 124 {
 125         spin_lock(&glamo->lock);
 126         __reg_set_bit_mask(glamo, reg, mask, val);
 127         spin_unlock(&glamo->lock);
 128 }
 129
 130 static int __reg_write_batch(struct glamo_core *glamo,
 131                         uint16_t start, size_t num, uint16_t *regs)
 132 {
 133         int end = start + num * 2
 134         for(end = start + num * 2; start < end; start += 2, ++regs) {
 135                 *regs = __reg_read(glamo, start);
 136         }
 137 }
 138
 139 static inline void __reg_set_bit(struct glamo_core *glamo,
 140                                  u_int16_t reg, u_int16_t bit)
 141 {
 142         __reg_set_bit_mask(glamo, reg, bit, 0xffff);
 143 }
 144
 145 static inline void __reg_clear_bit(struct glamo_core *glamo,
 146                                    u_int16_t reg, u_int16_t bit)
 147 {
 148         __reg_set_bit_mask(glamo, reg, bit, 0);
 149 }
 150
 151 /***********************************************************************
 152  * resources of sibling devices
 153  ***********************************************************************/
 154
 155 static struct resource glamo_fb_resources[] = {
 156         {
 157                 .name   = "glamo-fb-regs",
 158                 .start  = GLAMO_REGOFS_LCD,
 159                 .end    = GLAMO_REGOFS_MMC - 1,
 160                 .flags  = IORESOURCE_MEM,
 161         }, {
 162                 .name   = "glamo-fb-mem",
 163                 .start  = GLAMO_OFFSET_FB,
 164                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
 165                 .flags  = IORESOURCE_MEM,
 166         },
 167 };
 168
 169 static struct resource glamo_mmc_resources[] = {
 170         {
 171                 .start  = GLAMO_REGOFS_MMC,
 172                 .end    = GLAMO_REGOFS_MPROC0 - 1,
 173                 .flags  = IORESOURCE_MEM
 174         }, {
 175                 .start  = IRQ_GLAMO_MMC,
 176                 .end    = IRQ_GLAMO_MMC,
 177                 .flags  = IORESOURCE_IRQ,
 178         }, { /* our data buffer for MMC transfers */
 179                 .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
 180                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
 181                                   GLAMO_MMC_BUFFER_SIZE - 1,
 182                 .flags  = IORESOURCE_MEM
 183         },
 184 };
 185
 186 enum glamo_cells {
 187         GLAMO_CELL_FB,
 188         GLAMO_CELL_MMC,
 189         GLAMO_CELL_GPIO,
 190 };
 191
 192 static struct mfd_cell glamo_cells[] = {
 193         [GLAMO_CELL_FB] = {
 194                 .name = "glamo-fb",
 195                 .num_resources = ARRAY_SIZE(glamo_fb_resources),
 196                 .resources = glamo_fb_resources,
 197         },
 198         [GLAMO_CELL_MMC] = {
 199                 .name = "glamo-mci",
 200                 .num_resources = ARRAY_SIZE(glamo_mmc_resources),
 201                 .resources = glamo_mmc_resources,
 202         },
 203         [GLAMO_CELL_GPIO] = {
 204                 .name = "glamo-gpio",
 205         },
 206 };
 207
 208
 209 /***********************************************************************
 210  * IRQ demultiplexer
 211  ***********************************************************************/
 212 #define irq2glamo(x)    (x - IRQ_GLAMO(0))
 213
 214 static void glamo_ack_irq(unsigned int irq)
 215 {
 216         struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
 217         /* clear interrupt source */
 218         __reg_write(glamo, GLAMO_REG_IRQ_CLEAR,
 219                     1 << irq2glamo(irq));
 220 }
 221
 222 static void glamo_mask_irq(unsigned int irq)
 223 {
 224         struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
 225         u_int16_t tmp;
 226
 227         /* clear bit in enable register */
 228         tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
 229         tmp &= ~(1 << irq2glamo(irq));
 230         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
 231 }
 232
 233 static void glamo_unmask_irq(unsigned int irq)
 234 {
 235         struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
 236         u_int16_t tmp;
 237
 238         /* set bit in enable register */
 239         tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
 240         tmp |= (1 << irq2glamo(irq));
 241         __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
 242 }
 243
 244 static struct irq_chip glamo_irq_chip = {
 245         .name   = "glamo",
 246         .ack    = glamo_ack_irq,
 247         .mask   = glamo_mask_irq,
 248         .unmask = glamo_unmask_irq,
 249 };
 250
 251 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
 252 {
 253         struct glamo_core *glamo = get_irq_desc_chip_data(desc);
 254         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 255
 256         if (unlikely(desc->status & IRQ_INPROGRESS)) {
 257                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
 258                 desc->chip->mask(irq);
 259                 desc->chip->ack(irq);
 260                 return;
 261         }
 262         kstat_incr_irqs_this_cpu(irq, desc);
 263
 264         desc->chip->ack(irq);
 265         desc->status |= IRQ_INPROGRESS;
 266
 267         do {
 268                 u_int16_t irqstatus;
 269                 int i;
 270
 271                 if (unlikely((desc->status &
 272                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
 273                                 (IRQ_PENDING | IRQ_MASKED))) {
 274                         /* dealing with pending IRQ, unmasking */
 275                         desc->chip->unmask(irq);
 276                         desc->status &= ~IRQ_MASKED;
 277                 }
 278
 279                 desc->status &= ~IRQ_PENDING;
 280
 281                 /* read IRQ status register */
 282                 irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
 283                 for (i = 0; i < 9; i++)
 284                         if (irqstatus & (1 << i))
 285                                 desc_handle_irq(IRQ_GLAMO(i),
 286                                     irq_desc+IRQ_GLAMO(i));
 287
 288         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 289
 290         desc->status &= ~IRQ_INPROGRESS;
 291 }
 292
 293
 294 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
 295                            const char *buf, size_t count)
 296 {
 297         unsigned long reg = simple_strtoul(buf, NULL, 10);
 298         struct glamo_core *glamo = dev_get_drvdata(dev);
 299
 300         while (*buf && (*buf != ' '))
 301                 buf++;
 302         if (*buf != ' ')
 303                 return -EINVAL;
 304         while (*buf && (*buf == ' '))
 305                 buf++;
 306         if (!*buf)
 307                 return -EINVAL;
 308
 309         printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
 310                reg, simple_strtoul(buf, NULL, 10));
 311
 312         __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
 313
 314         return count;
 315 }
 316
 317 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
 318                         char *buf)
 319 {
 320         struct glamo_core *glamo = dev_get_drvdata(dev);
 321         int n, n1 = 0, r;
 322         char * end = buf;
 323
 324         spin_lock(&glamo->lock);
 325
 326         for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
 327                 if (!reg_range[r].dump)
 328                         continue;
 329                 n1 = 0;
 330                 end += sprintf(end, "\n%s\n", reg_range[r].name);
 331                 for (n = reg_range[r].start;
 332                      n < reg_range[r].start + reg_range[r].count; n += 2) {
 333                         if (((n1++) & 7) == 0)
 334                                 end += sprintf(end, "\n%04X:  ", n);
 335                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
 336                 }
 337                 end += sprintf(end, "\n");
 338                 if (!attr) {
 339                         printk("%s", buf);
 340                         end = buf;
 341                 }
 342         }
 343         spin_unlock(&glamo->lock);
 344
 345         return end - buf;
 346 }
 347
 348 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
 349 static struct attribute *glamo_sysfs_entries[] = {
 350         &dev_attr_regs.attr,
 351         NULL
 352 };
 353 static struct attribute_group glamo_attr_group = {
 354         .name   = NULL,
 355         .attrs  = glamo_sysfs_entries,
 356 };
 357
 358
 359
 360 /***********************************************************************
 361  * 'engine' support
 362  ***********************************************************************/
 363
 364 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 365 {
 366         switch (engine) {
 367         case GLAMO_ENGINE_LCD:
 368                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 369                                    GLAMO_HOSTBUS2_MMIO_EN_LCD,
 370                                    GLAMO_HOSTBUS2_MMIO_EN_LCD);
 371                 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
 372                             GLAMO_CLOCK_LCD_EN_M5CLK |
 373                             GLAMO_CLOCK_LCD_EN_DHCLK |
 374                             GLAMO_CLOCK_LCD_EN_DMCLK |
 375                             GLAMO_CLOCK_LCD_EN_DCLK |
 376                             GLAMO_CLOCK_LCD_DG_M5CLK |
 377                             GLAMO_CLOCK_LCD_DG_DMCLK);
 378                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 379                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 380                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 381                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
 382                 break;
 383         case GLAMO_ENGINE_MMC:
 384                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 385                                    GLAMO_HOSTBUS2_MMIO_EN_MMC,
 386                                    GLAMO_HOSTBUS2_MMIO_EN_MMC);
 387                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 388                                    GLAMO_CLOCK_MMC_EN_M9CLK |
 389                                    GLAMO_CLOCK_MMC_EN_TCLK |
 390                                    GLAMO_CLOCK_MMC_DG_M9CLK |
 391                                    GLAMO_CLOCK_MMC_DG_TCLK,
 392                                    0xffff);
 393                 /* enable the TCLK divider clk input */
 394                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 395                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
 396                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
 397                 break;
 398         case GLAMO_ENGINE_2D:
 399                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 400                                    GLAMO_CLOCK_2D_EN_M7CLK |
 401                                    GLAMO_CLOCK_2D_EN_GCLK |
 402                                    GLAMO_CLOCK_2D_DG_M7CLK |
 403                                    GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
 404                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 405                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
 406                                    GLAMO_HOSTBUS2_MMIO_EN_2D);
 407                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 408                                    GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 409                                                    0xffff);
 410                 break;
 411         case GLAMO_ENGINE_CMDQ:
 412                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 413                                    GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
 414                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 415                                    GLAMO_HOSTBUS2_MMIO_EN_CQ,
 416                                    GLAMO_HOSTBUS2_MMIO_EN_CQ);
 417                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 418                                    GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
 419                                                    0xffff);
 420                 break;
 421         /* FIXME: Implementation */
 422         default:
 423                 return -EINVAL;
 424         }
 425
 426         glamo->engine_enabled_bitfield |= 1 << engine;
 427
 428         return 0;
 429 }
 430
 431 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 432 {
 433         int ret;
 434
 435         spin_lock(&glamo->lock);
 436
 437         ret = __glamo_engine_enable(glamo, engine);
 438
 439         spin_unlock(&glamo->lock);
 440
 441         return ret;
 442 }
 443 EXPORT_SYMBOL_GPL(glamo_engine_enable);
 444
 445 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 446 {
 447         switch (engine) {
 448         case GLAMO_ENGINE_LCD:
 449                 /* remove pixel clock to LCM */
 450                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 451                             GLAMO_CLOCK_LCD_EN_DCLK, 0);
 452                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 453                             GLAMO_CLOCK_LCD_EN_DHCLK |
 454                             GLAMO_CLOCK_LCD_EN_DMCLK, 0);
 455                 /* kill memory clock */
 456                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 457                             GLAMO_CLOCK_LCD_EN_M5CLK, 0);
 458                 /* stop dividing the clocks */
 459                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 460                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 461                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 462                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
 463                 break;
 464
 465         case GLAMO_ENGINE_MMC:
 466                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 467                                                    GLAMO_CLOCK_MMC_EN_M9CLK |
 468                                                    GLAMO_CLOCK_MMC_EN_TCLK |
 469                                                    GLAMO_CLOCK_MMC_DG_M9CLK |
 470                                                    GLAMO_CLOCK_MMC_DG_TCLK, 0);
 471                 /* disable the TCLK divider clk input */
 472                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 473                                         GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
 474                 break;
 475         case GLAMO_ENGINE_CMDQ:
 476                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 477                                            GLAMO_CLOCK_2D_EN_M6CLK,
 478                                                            0);
 479                         __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 480                                            GLAMO_HOSTBUS2_MMIO_EN_CQ,
 481                                            GLAMO_HOSTBUS2_MMIO_EN_CQ);
 482 /*                      __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 483                                            GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
 484                                                            0);*/
 485                 break;
 486         case GLAMO_ENGINE_2D:
 487                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 488                                                            GLAMO_CLOCK_2D_EN_M7CLK |
 489                                                            GLAMO_CLOCK_2D_EN_GCLK |
 490                                                            GLAMO_CLOCK_2D_DG_M7CLK |
 491                                                            GLAMO_CLOCK_2D_DG_GCLK,
 492                                                            0);
 493                         __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 494                                            GLAMO_HOSTBUS2_MMIO_EN_2D,
 495                                            GLAMO_HOSTBUS2_MMIO_EN_2D);
 496                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 497                                            GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 498                                                            0);
 499                 break;
 500         default:
 501                 return -EINVAL;
 502         }
 503
 504         glamo->engine_enabled_bitfield &= ~(1 << engine);
 505
 506         return 0;
 507 }
 508 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 509 {
 510         int ret;
 511
 512         spin_lock(&glamo->lock);
 513
 514         ret = __glamo_engine_disable(glamo, engine);
 515
 516         spin_unlock(&glamo->lock);
 517
 518         return ret;
 519 }
 520 EXPORT_SYMBOL_GPL(glamo_engine_disable);
 521
 522 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
 523         [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
 524         [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
 525         [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
 526         [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
 527         [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
 528         [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
 529         [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
 530         [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
 531 };
 532
 533 void glamo_engine_clkreg_set(struct glamo_core *glamo,
 534                              enum glamo_engine engine,
 535                              u_int16_t mask, u_int16_t val)
 536 {
 537         reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
 538 }
 539 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
 540
 541 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
 542                                   enum glamo_engine engine)
 543 {
 544         u_int16_t val;
 545
 546         spin_lock(&glamo->lock);
 547         val = __reg_read(glamo, engine_clock_regs[engine]);
 548         spin_unlock(&glamo->lock);
 549
 550         return val;
 551 }
 552 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
 553
 554 static const struct glamo_script engine_div_regs[__NUM_GLAMO_ENGINES] = {
 555         [GLAMO_ENGINE_LCD] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_DCLK},
 556         [GLAMO_ENGINE_MMC] = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_TCLK},
 557         [GLAMO_ENGINE_2D]  = {GLAMO_REG_CLOCK_GEN5_1, GLAMO_CLOCK_GEN51_EN_DIV_GCLK},
 558 };
 559
 560 void glamo_engine_div_enable(struct glamo_core *glamo, enum glamo_engine engine)
 561 {
 562         uint16_t reg = engine_div_regs[engine].reg;
 563         uint16_t bit = engine_div_regs[engine].val;
 564         uint16_t val;
 565
 566         spin_lock(&glamo->lock);
 567         val = __reg_read(glamo, reg);
 568         __reg_write(glamo, reg, val | bit);
 569         spin_unlock(&glamo->lock);
 570         mdelay(5);
 571 }
 572 EXPORT_SYMBOL_GPL(glamo_engine_div_enable);
 573
 574 void glamo_engine_div_disable(struct glamo_core *glamo, enum glamo_engine engine)
 575 {
 576         uint16_t reg = engine_div_regs[engine].reg;
 577         uint16_t bit = engine_div_regs[engine].val;
 578         uint16_t val;
 579
 580         spin_lock(&glamo->lock);
 581         val = __reg_read(glamo, reg);
 582         __reg_write(glamo, reg, val & ~bit);
 583         spin_unlock(&glamo->lock);
 584 }
 585 EXPORT_SYMBOL_GPL(glamo_engine_div_disable);
 586
 587 static const struct glamo_script reset_regs[] = {
 588         [GLAMO_ENGINE_LCD] = {
 589                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
 590         },
 591 #if 0
 592         [GLAMO_ENGINE_HOST] = {
 593                 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
 594         },
 595         [GLAMO_ENGINE_MEM] = {
 596                 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
 597         },
 598 #endif
 599         [GLAMO_ENGINE_MMC] = {
 600                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
 601         },
 602         [GLAMO_ENGINE_CMDQ] = {
 603                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
 604         },
 605         [GLAMO_ENGINE_2D] = {
 606                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
 607         },
 608         [GLAMO_ENGINE_JPEG] = {
 609                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
 610         },
 611 };
 612
 613 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
 614 {
 615         uint16_t reg = reset_regs[engine].reg;
 616         uint16_t val = reset_regs[engine].val;
 617
 618         if (engine >= ARRAY_SIZE(reset_regs)) {
 619                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
 620                 return;
 621         }
 622
 623
 624         spin_lock(&glamo->lock);
 625         __reg_set_bit(glamo, reg, val);
 626         __reg_clear_bit(glamo, reg, val);
 627         spin_unlock(&glamo->lock);
 628 }
 629 EXPORT_SYMBOL_GPL(glamo_engine_reset);
 630
 631 int glamo_pll_rate(struct glamo_core *glamo,
 632                           enum glamo_pll pll)
 633 {
 634         u_int16_t reg;
 635         unsigned int osci = glamo->pdata->osci_clock_rate;
 636
 637         switch (pll) {
 638         case GLAMO_PLL1:
 639                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
 640                 break;
 641         case GLAMO_PLL2:
 642                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
 643                 break;
 644         default:
 645                 return -EINVAL;
 646         }
 647         return osci*reg;
 648 }
 649 EXPORT_SYMBOL_GPL(glamo_pll_rate);
 650
 651 int glamo_engine_reclock(struct glamo_core *glamo,
 652                          enum glamo_engine engine,
 653                          int hz)
 654 {
 655         int pll;
 656         u_int16_t reg, mask, div;
 657
 658         if (!hz)
 659                 return -EINVAL;
 660
 661         switch (engine) {
 662         case GLAMO_ENGINE_LCD:
 663                 pll = GLAMO_PLL1;
 664                 reg = GLAMO_REG_CLOCK_GEN7;
 665                 mask = 0xff;
 666                 break;
 667         case GLAMO_ENGINE_MMC:
 668                 pll = GLAMO_PLL1;
 669                 reg = GLAMO_REG_CLOCK_GEN8;
 670                 mask = 0xff;
 671                 break;
 672         default:
 673                 dev_warn(&glamo->pdev->dev,
 674                          "reclock of engine 0x%x not supported\n", engine);
 675                 return -EINVAL;
 676                 break;
 677         }
 678
 679         pll = glamo_pll_rate(glamo, pll);
 680
 681         div = pll / hz;
 682
 683         if (div != 0 && pll / div <= hz)
 684                 --div;
 685
 686         if (div > mask)
 687                 div = mask;
 688
 689         dev_dbg(&glamo->pdev->dev,
 690                         "PLL %d, kHZ %d, div %d\n", pll, hz / 1000, div);
 691
 692         reg_set_bit_mask(glamo, reg, mask, div);
 693         mdelay(5); /* wait some time to stabilize */
 694
 695         return pll / (div + 1);
 696 }
 697 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
 698
 699 /***********************************************************************
 700  * script support
 701  ***********************************************************************/
 702
 703 int glamo_run_script(struct glamo_core *glamo, const struct glamo_script *script,
 704                      int len, int may_sleep)
 705 {
 706         int i;
 707     const struct glamo_script *line = script;
 708
 709         for (i = 0; i < len; ++i, ++line) {
 710                 switch (line->reg) {
 711                 case 0xffff:
 712                         return 0;
 713                 case 0xfffe:
 714                         if (may_sleep)
 715                                 msleep(line->val);
 716                         else
 717                                 mdelay(line->val * 4);
 718                         break;
 719                 case 0xfffd:
 720                         /* spin until PLLs lock */
 721                         while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
 722                                 ;
 723                         break;
 724
 725                 /*
 726                  * couple of people reported artefacts with 2.6.28 changes, this
 727                  * allows reversion to 2.6.24 settings
 728                  */
 729
 730                 case 0x200:
 731                         switch (slow_memory) {
 732                         /* choice 1 is the most conservative */
 733                         case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
 734                                 __reg_write(glamo, script[i].reg, 0xef0);
 735                                 break;
 736                         case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
 737                                 __reg_write(glamo, script[i].reg, 0xea0);
 738                                 break;
 739                         case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
 740                                 __reg_write(glamo, script[i].reg, 0xe50);
 741                                 break;
 742                         case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
 743                                 __reg_write(glamo, script[i].reg, 0xe00);
 744                                 break;
 745
 746                         /* using PLL2 for memory bus increases CPU bandwidth significantly */
 747                         case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
 748                                 __reg_write(glamo, script[i].reg, 0xef3);
 749                                 break;
 750                         case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
 751                                 __reg_write(glamo, script[i].reg, 0xea3);
 752                                 break;
 753                         case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
 754                                 __reg_write(glamo, script[i].reg, 0xe53);
 755                                 break;
 756                         /* default of 0 or >7 is fastest */
 757                         default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
 758                                 __reg_write(glamo, script[i].reg, 0xe03);
 759                                 break;
 760                         }
 761                         break;
 762
 763                 default:
 764                         __reg_write(glamo, script[i].reg, script[i].val);
 765                         break;
 766                 }
 767         }
 768
 769         return 0;
 770 }
 771 EXPORT_SYMBOL(glamo_run_script);
 772
 773 static const struct glamo_script glamo_init_script[] = {
 774         { GLAMO_REG_CLOCK_HOST,         0x1000 },
 775                 { 0xfffe, 2 },
 776         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
 777         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
 778         { GLAMO_REG_CLOCK_LCD,          0x1000 },
 779         { GLAMO_REG_CLOCK_MMC,          0x1000 },
 780         { GLAMO_REG_CLOCK_ISP,          0x1000 },
 781         { GLAMO_REG_CLOCK_ISP,          0x3000 },
 782         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
 783         { GLAMO_REG_CLOCK_3D,           0x1000 },
 784         { GLAMO_REG_CLOCK_3D,           0x3000 },
 785         { GLAMO_REG_CLOCK_2D,           0x1000 },
 786         { GLAMO_REG_CLOCK_2D,           0x3000 },
 787         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
 788         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 789         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 790         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
 791                 { 0xfffe, 2 },
 792         { GLAMO_REG_CLOCK_HOST,         0x0000 },
 793         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
 794         { GLAMO_REG_CLOCK_LCD,          0x0000 },
 795         { GLAMO_REG_CLOCK_MMC,          0x0000 },
 796 #if 0
 797 /* unused engines must be left in reset to stop MMC block read "blackouts" */
 798         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 799         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 800         { GLAMO_REG_CLOCK_JPEG,         0x0000 },
 801         { GLAMO_REG_CLOCK_3D,           0x0000 },
 802         { GLAMO_REG_CLOCK_3D,           0x0000 },
 803         { GLAMO_REG_CLOCK_2D,           0x0000 },
 804         { GLAMO_REG_CLOCK_2D,           0x0000 },
 805         { GLAMO_REG_CLOCK_RISC1,        0x0000 },
 806         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 807         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 808 #endif
 809         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 810         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 811         { 0xfffd, 0 },
 812         /*
 813          * b9 of this register MUST be zero to get any interrupts on INT#
 814          * the other set bits enable all the engine interrupt sources
 815          */
 816         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 817         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
 818         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
 819         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
 820         { GLAMO_REG_CLOCK_HOST,         0x000d },
 821         /*
 822          * b7..b4 = 0 = no wait states on read or write
 823          * b0 = 1 select PLL2 for Host interface, b1 = enable it
 824          */
 825         { 0x200,        0x0e03 /* this is replaced by script parser */ },
 826         { 0x202,        0x07ff },
 827         { 0x212,        0x0000 },
 828         { 0x214,        0x4000 },
 829         { 0x216,        0xf00e },
 830
 831         /* S-Media recommended "set tiling mode to 512 mode for memory access
 832          * more efficiency when 640x480" */
 833         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
 834         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
 835
 836         { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
 837
 838         { GLAMO_REG_MEM_TIMING1,        0x0108 },
 839         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
 840         { GLAMO_REG_MEM_TIMING3,        0x0000 },
 841         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
 842         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
 843         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
 844         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
 845         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
 846         { GLAMO_REG_MEM_TIMING9,        0x6006 },
 847         { GLAMO_REG_MEM_TIMING10,       0x00ff },
 848         { GLAMO_REG_MEM_TIMING11,       0x0001 },
 849         { GLAMO_REG_MEM_POWER1,         0x0020 },
 850         { GLAMO_REG_MEM_POWER2,         0x0000 },
 851         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 852                 { 0xfffe, 1 },
 853         { GLAMO_REG_MEM_DRAM1,          0xc100 },
 854                 { 0xfffe, 1 },
 855         { GLAMO_REG_MEM_DRAM1,          0xe100 },
 856         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
 857         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
 858 };
 859 #if 0
 860 static struct glamo_script glamo_resume_script[] = {
 861
 862         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 863         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 864         { GLAMO_REG_DFT_GEN6, 1 },
 865                 { 0xfffe, 100 },
 866                 { 0xfffd, 0 },
 867         { 0x200,        0x0e03 },
 868
 869         /*
 870          * b9 of this register MUST be zero to get any interrupts on INT#
 871          * the other set bits enable all the engine interrupt sources
 872          */
 873         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 874         { GLAMO_REG_CLOCK_HOST,         0x0018 },
 875         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
 876
 877         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 878                 { 0xfffe, 1 },
 879         { GLAMO_REG_MEM_DRAM1,          0xc100 },
 880                 { 0xfffe, 1 },
 881         { GLAMO_REG_MEM_DRAM1,          0xe100 },
 882         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
 883         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
 884 };
 885 #endif
 886
 887 enum glamo_power {
 888         GLAMO_POWER_ON,
 889         GLAMO_POWER_SUSPEND,
 890 };
 891
 892 static void glamo_power(struct glamo_core *glamo,
 893                         enum glamo_power new_state)
 894 {
 895         int n;
 896         unsigned long flags;
 897
 898         spin_lock_irqsave(&glamo->lock, flags);
 899
 900         dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
 901
 902         /*
 903 Power management
 904 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
 905 {
 906     { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
 907     { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
 908     { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
 909     { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
 910     { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
 911 };
 912
 913 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
 914 {
 915     { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
 916     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
 917     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
 918     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
 919 };
 920
 921 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
 922 {
 923     { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
 924     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
 925     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
 926     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
 927 };
 928 */
 929
 930         switch (new_state) {
 931         case GLAMO_POWER_ON:
 932
 933                 /*
 934                  * glamo state on resume is nondeterministic in some
 935                  * fundamental way, it has also been observed that the
 936                  * Glamo reset pin can get asserted by, eg, touching it with
 937                  * a scope probe.  So the only answer is to roll with it and
 938                  * force an external reset on the Glamo during resume.
 939                  */
 940
 941                 (glamo->pdata->glamo_external_reset)(0);
 942                 udelay(10);
 943                 (glamo->pdata->glamo_external_reset)(1);
 944                 mdelay(5);
 945
 946                 glamo_run_script(glamo, glamo_init_script,
 947                          ARRAY_SIZE(glamo_init_script), 0);
 948
 949                 break;
 950
 951         case GLAMO_POWER_SUSPEND:
 952
 953                 /* nuke interrupts */
 954                 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
 955
 956                 /* stash a copy of which engines were running */
 957                 glamo->engine_enabled_bitfield_suspend =
 958                                                  glamo->engine_enabled_bitfield;
 959
 960                 /* take down each engine before we kill mem and pll */
 961                 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
 962                         if (glamo->engine_enabled_bitfield & (1 << n))
 963                                 __glamo_engine_disable(glamo, n);
 964
 965                 /* enable self-refresh */
 966
 967                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
 968                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
 969                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
 970                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
 971                                         GLAMO_MEM_REFRESH_COUNT);
 972                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
 973                                         GLAMO_MEM_DRAM1_EN_MODEREG_SET |
 974                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
 975                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
 976                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
 977                                         GLAMO_MEM_REFRESH_COUNT);
 978
 979                 /* force RAM into deep powerdown */
 980
 981                 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
 982                                         GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
 983                                         (7 << 6) | /* tRC */
 984                                         (1 << 4) | /* tRP */
 985                                         (1 << 2) | /* tRCD */
 986                                         2); /* CAS latency */
 987
 988                 /* disable clocks to memory */
 989                 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
 990
 991                 /* all dividers from OSCI */
 992                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
 993
 994                 /* PLL2 into bypass */
 995                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
 996
 997                 __reg_write(glamo, 0x200, 0x0e00);
 998
 999
1000                 /* kill PLLS 1 then 2 */
1001                 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1002                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1003
1004                 break;
1005         }
1006
1007         spin_unlock_irqrestore(&glamo->lock, flags);
1008 }
1009
1010 #if 0
1011 #define MEMDETECT_RETRY 6
1012 static unsigned int detect_memsize(struct glamo_core *glamo)
1013 {
1014         int i;
1015
1016         /*static const u_int16_t pattern[] = {
1017                 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1018                 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1019                 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1020                 0x7777, 0x2a2a, 0x8888, 0x1a1a
1021         }; */
1022
1023         for (i = 0; i < MEMDETECT_RETRY; i++) {
1024                 switch (glamo->type) {
1025                 case 3600:
1026                         __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1027                         __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1028                         break;
1029                 case 3650:
1030                         switch (glamo->revision) {
1031                         case GLAMO_CORE_REV_A0:
1032                                 if (i & 1)
1033                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1034                                                     0x097a);
1035                                 else
1036                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1037                                                     0x0173);
1038
1039                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1040                                 msleep(1);
1041                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1042                                 break;
1043                         default:
1044                                 if (i & 1)
1045                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1046                                                     0x0972);
1047                                 else
1048                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1049                                                     0x0872);
1050
1051                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1052                                 msleep(1);
1053                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1054                                 break;
1055                         }
1056                         break;
1057                 case 3700:
1058                         /* FIXME */
1059                 default:
1060                         break;
1061                 }
1062
1063 #if 0
1064                 /* FIXME: finish implementation */
1065                 for (j = 0; j < 8; j++) {
1066                         __
1067 #endif
1068         }
1069
1070         return 0;
1071 }
1072 #endif
1073
1074 /* Find out if we can support this version of the Glamo chip */
1075 static int glamo_supported(struct glamo_core *glamo)
1076 {
1077         u_int16_t dev_id, rev_id; /*, memsize; */
1078
1079         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1080         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1081
1082         switch (dev_id) {
1083         case 0x3650:
1084                 switch (rev_id) {
1085                 case GLAMO_CORE_REV_A2:
1086                         break;
1087                 case GLAMO_CORE_REV_A0:
1088                 case GLAMO_CORE_REV_A1:
1089                 case GLAMO_CORE_REV_A3:
1090                         dev_warn(&glamo->pdev->dev, "untested core revision "
1091                                  "%04x, your mileage may vary\n", rev_id);
1092                         break;
1093                 default:
1094                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1095                                  "%04x, your mileage may vary\n", rev_id);
1096                         /* maybe should abort ? */
1097                 }
1098                 break;
1099         case 0x3600:
1100         case 0x3700:
1101         default:
1102                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1103                         dev_id);
1104                 return 0;
1105         }
1106
1107         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1108                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1109                  glamo_pll_rate(glamo, GLAMO_PLL1),
1110                  glamo_pll_rate(glamo, GLAMO_PLL2));
1111
1112         return 1;
1113 }
1114
1115 static int __init glamo_probe(struct platform_device *pdev)
1116 {
1117         int rc = 0, irq;
1118         struct glamo_core *glamo;
1119
1120         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1121         if (!glamo)
1122                 return -ENOMEM;
1123
1124         spin_lock_init(&glamo->lock);
1125         glamo->pdev = pdev;
1126         glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1127         glamo->irq = platform_get_irq(pdev, 0);
1128         glamo->pdata = pdev->dev.platform_data;
1129         if (!glamo->mem || !glamo->pdata) {
1130                 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1131                 rc = -ENOENT;
1132                 goto bail_free;
1133         }
1134
1135         /* register a number of sibling devices whoise IOMEM resources
1136          * are siblings of pdev's IOMEM resource */
1137
1138         /* only remap the generic, hostbus and memory controller registers */
1139         glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1140         if (!glamo->base) {
1141                 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1142                 goto bail_free;
1143         }
1144
1145         platform_set_drvdata(pdev, glamo);
1146
1147         (glamo->pdata->glamo_external_reset)(0);
1148         udelay(10);
1149         (glamo->pdata->glamo_external_reset)(1);
1150         mdelay(10);
1151
1152         /*
1153          * finally set the mfd interrupts up
1154          * can't do them earlier or sibling probes blow up
1155          */
1156
1157         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1158                 set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
1159                 set_irq_flags(irq, IRQF_VALID);
1160                 set_irq_chip_data(irq, glamo);
1161         }
1162
1163         if (glamo->pdata->glamo_irq_is_wired &&
1164             !glamo->pdata->glamo_irq_is_wired()) {
1165                 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1166                 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1167                 set_irq_chip_data(glamo->irq, glamo);
1168                 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1169                 glamo->irq_works = 1;
1170         } else {
1171                 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1172                 glamo->irq_works = 0;
1173         }
1174
1175         /* confirm it isn't insane version */
1176         if (!glamo_supported(glamo)) {
1177                 dev_err(&pdev->dev, "This Glamo is not supported\n");
1178                 goto bail_irq;
1179         }
1180
1181         /* sysfs */
1182         rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1183         if (rc < 0) {
1184                 dev_err(&pdev->dev, "cannot create sysfs group\n");
1185                 goto bail_irq;
1186         }
1187
1188         /* init the chip with canned register set */
1189
1190         dev_dbg(&glamo->pdev->dev, "running init script\n");
1191         glamo_run_script(glamo, glamo_init_script,
1192                          ARRAY_SIZE(glamo_init_script), 1);
1193
1194         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1195                  glamo_pll_rate(glamo, GLAMO_PLL1),
1196                  glamo_pll_rate(glamo, GLAMO_PLL2));
1197
1198         mfd_add_devices(&pdev->dev, pdev->id, glamo_cells,
1199                               ARRAY_SIZE(glamo_cells),
1200                                                   glamo->mem, 0);
1201
1202         /* only request the generic, hostbus and memory controller MMIO */
1203         glamo->mem = request_mem_region(glamo->mem->start,
1204                                         GLAMO_REGOFS_VIDCAP, "glamo-core");
1205         if (!glamo->mem) {
1206                 dev_err(&pdev->dev, "failed to request memory region\n");
1207                 goto bail_irq;
1208         }
1209
1210         return 0;
1211
1212 bail_irq:
1213         disable_irq(glamo->irq);
1214         set_irq_chained_handler(glamo->irq, NULL);
1215         set_irq_chip_data(glamo->irq, NULL);
1216
1217         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1218                 set_irq_flags(irq, 0);
1219                 set_irq_chip(irq, NULL);
1220                 set_irq_chip_data(irq, NULL);
1221         }
1222
1223         iounmap(glamo->base);
1224 bail_free:
1225         platform_set_drvdata(pdev, NULL);
1226         kfree(glamo);
1227
1228         return rc;
1229 }
1230
1231 static int glamo_remove(struct platform_device *pdev)
1232 {
1233         struct glamo_core *glamo = platform_get_drvdata(pdev);
1234         int irq;
1235
1236         disable_irq(glamo->irq);
1237         set_irq_chained_handler(glamo->irq, NULL);
1238         set_irq_chip_data(glamo->irq, NULL);
1239
1240         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1241                 set_irq_flags(irq, 0);
1242                 set_irq_chip(irq, NULL);
1243                 set_irq_chip_data(irq, NULL);
1244         }
1245
1246         platform_set_drvdata(pdev, NULL);
1247         mfd_remove_devices(&pdev->dev);
1248         iounmap(glamo->base);
1249         release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1250         kfree(glamo);
1251
1252         return 0;
1253 }
1254
1255 #ifdef CONFIG_PM
1256
1257 static int glamo_suspend(struct device *dev)
1258 {
1259         struct glamo_core *glamo = dev_get_drvdata(dev);
1260         glamo->suspending = 1;
1261         glamo_power(glamo, GLAMO_POWER_SUSPEND);
1262
1263         return 0;
1264 }
1265
1266 static int glamo_resume(struct device *dev)
1267 {
1268         struct glamo_core *glamo = dev_get_drvdata(dev);
1269         glamo_power(glamo, GLAMO_POWER_ON);
1270         glamo->suspending = 0;
1271         return 0;
1272 }
1273
1274 static struct dev_pm_ops glamo_pm_ops = {
1275         .suspend = glamo_suspend,
1276         .resume  = glamo_resume,
1277 };
1278
1279 #define GLAMO_PM_OPS (&glamo_pm_ops)
1280
1281 #else
1282 #define GLAMO_PM_OPS NULL
1283 #endif
1284
1285 static struct platform_driver glamo_driver = {
1286         .probe          = glamo_probe,
1287         .remove         = glamo_remove,
1288         .driver         = {
1289                 .name   = "glamo3362",
1290                 .owner  = THIS_MODULE,
1291                 .pm     = GLAMO_PM_OPS,
1292         },
1293 };
1294
1295 static int __devinit glamo_init(void)
1296 {
1297         return platform_driver_register(&glamo_driver);
1298 }
1299
1300 static void __exit glamo_cleanup(void)
1301 {
1302         platform_driver_unregister(&glamo_driver);
1303 }
1304
1305 module_init(glamo_init);
1306 module_exit(glamo_cleanup);
1307
1308 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1309 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1310 MODULE_LICENSE("GPL");