target/linux/rb532/files-2.6.24/drivers/net/korina.c

   1 /**************************************************************************
   2  *
   3  *  BRIEF MODULE DESCRIPTION
   4  *     Driver for the IDT RC32434 on-chip ethernet controller.
   5  *
   6  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
   7  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  *
  30  **************************************************************************
  31  * May 2004 rkt, neb
  32  *
  33  * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
  34  *
  35  * Aug 2004 Sadik
  36  *
  37  * Added NAPI
  38  *
  39  **************************************************************************
  40  */
  41
  42 #include <linux/autoconf.h>
  43 #include <linux/module.h>
  44 #include <linux/kernel.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/sched.h>
  47 #include <linux/ctype.h>
  48 #include <linux/types.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/interrupt.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/init.h>
  53 #include <linux/ioport.h>
  54 #include <linux/proc_fs.h>
  55 #include <linux/in.h>
  56 #include <linux/slab.h>
  57 #include <linux/string.h>
  58 #include <linux/delay.h>
  59 #include <linux/netdevice.h>
  60 #include <linux/etherdevice.h>
  61 #include <linux/skbuff.h>
  62 #include <linux/errno.h>
  63 #include <linux/platform_device.h>
  64 #include <asm/bootinfo.h>
  65 #include <asm/system.h>
  66 #include <asm/bitops.h>
  67 #include <asm/pgtable.h>
  68 #include <asm/segment.h>
  69 #include <asm/io.h>
  70 #include <asm/dma.h>
  71
  72 #include <asm/rc32434/rb.h>
  73 #include "rc32434_eth.h"
  74
  75 #define DRIVER_VERSION "(mar2904)"
  76
  77 #define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
  78
  79 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
  80                                    ((dev)->dev_addr[1]))
  81 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
  82                                    ((dev)->dev_addr[3] << 16) | \
  83                                    ((dev)->dev_addr[4] << 8)  | \
  84                                    ((dev)->dev_addr[5]))
  85
  86 #define MII_CLOCK 1250000                               /* no more than 2.5MHz */
  87 #define CONFIG_IDT_USE_NAPI 1
  88
  89
  90 static inline void rc32434_abort_tx(struct net_device *dev)
  91 {
  92         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
  93         rc32434_abort_dma(dev, lp->tx_dma_regs);
  94
  95 }
  96
  97 static inline void rc32434_abort_rx(struct net_device *dev)
  98 {
  99         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 100         rc32434_abort_dma(dev, lp->rx_dma_regs);
 101
 102 }
 103
 104 static inline void rc32434_start_tx(struct rc32434_local *lp,  volatile DMAD_t td)
 105 {
 106         rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
 107 }
 108
 109 static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
 110 {
 111         rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 112 }
 113
 114 static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
 115 {
 116         rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
 117 }
 118
 119 static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
 120 {
 121         rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
 122 }
 123
 124 #ifdef RC32434_PROC_DEBUG
 125 static int rc32434_read_proc(char *buf, char **start, off_t fpos,
 126                              int length, int *eof, void *data)
 127 {
 128         struct net_device *dev = (struct net_device *)data;
 129         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 130         int len = 0;
 131
 132         /* print out header */
 133         len += sprintf(buf + len, "\n\tKorina Ethernet Debug\n\n");
 134         len += sprintf (buf + len,
 135                         "DMA halt count      = %10d, DMA run count = %10d\n",
 136                         lp->dma_halt_cnt, lp->dma_run_cnt);
 137
 138         if (fpos >= len) {
 139                 *start = buf;
 140                 *eof = 1;
 141                 return 0;
 142         }
 143         *start = buf + fpos;
 144
 145         if ((len -= fpos) > length)
 146                 return length;
 147         *eof = 1;
 148
 149         return len;
 150
 151 }
 152 #endif
 153
 154
 155 /*
 156  * Restart the RC32434 ethernet controller.
 157  */
 158 static int rc32434_restart(struct net_device *dev)
 159 {
 160         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 161
 162         /*
 163          * Disable interrupts
 164          */
 165         disable_irq(lp->rx_irq);
 166         disable_irq(lp->tx_irq);
 167 #ifdef  RC32434_REVISION
 168         disable_irq(lp->ovr_irq);
 169 #endif
 170         disable_irq(lp->und_irq);
 171
 172         /* Mask F E bit in Tx DMA */
 173         __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
 174         /* Mask D H E bit in Rx DMA */
 175         __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
 176
 177         rc32434_init(dev);
 178         rc32434_multicast_list(dev);
 179
 180         enable_irq(lp->und_irq);
 181 #ifdef  RC32434_REVISION
 182         enable_irq(lp->ovr_irq);
 183 #endif
 184         enable_irq(lp->tx_irq);
 185         enable_irq(lp->rx_irq);
 186
 187         return 0;
 188 }
 189
 190 static int rc32434_probe(struct platform_device *pdev)
 191 {
 192         struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
 193         struct rc32434_local *lp = NULL;
 194         struct net_device *dev = NULL;
 195         struct resource *r;
 196         int i, retval,err;
 197
 198         dev = alloc_etherdev(sizeof(struct rc32434_local));
 199         if(!dev) {
 200                 ERR("Korina_eth: alloc_etherdev failed\n");
 201                 return -1;
 202         }
 203
 204         platform_set_drvdata(pdev, dev);
 205         SET_NETDEV_DEV(dev, &pdev->dev);
 206         bif->dev = dev;
 207
 208         memcpy(dev->dev_addr, bif->mac, 6);
 209
 210         /* Initialize the device structure. */
 211         if (dev->priv == NULL) {
 212                 lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
 213                 memset(lp, 0, sizeof(struct rc32434_local));
 214         }
 215         else {
 216                 lp = (struct rc32434_local *)dev->priv;
 217         }
 218
 219         lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx");
 220         lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx");
 221         lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr");
 222         lp->und_irq = platform_get_irq_byname(pdev, "korina_und");
 223
 224         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs");
 225         dev->base_addr = r->start;
 226         lp->eth_regs = ioremap_nocache(r->start, r->end - r->start);
 227         if (!lp->eth_regs) {
 228                 ERR("Can't remap eth registers\n");
 229                 retval = -ENXIO;
 230                 goto probe_err_out;
 231         }
 232
 233         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx");
 234         lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
 235         if (!lp->rx_dma_regs) {
 236                 ERR("Can't remap Rx DMA registers\n");
 237                 retval = -ENXIO;
 238                 goto probe_err_out;
 239         }
 240
 241         r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx");
 242         lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start);
 243         if (!lp->tx_dma_regs) {
 244                 ERR("Can't remap Tx DMA registers\n");
 245                 retval = -ENXIO;
 246                 goto probe_err_out;
 247         }
 248
 249 #ifdef RC32434_PROC_DEBUG
 250         lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
 251                                          rc32434_read_proc, dev);
 252 #endif
 253
 254         lp->td_ring =   (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
 255         if (!lp->td_ring) {
 256                 ERR("Can't allocate descriptors\n");
 257                 retval = -ENOMEM;
 258                 goto probe_err_out;
 259         }
 260
 261         dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
 262
 263         /* now convert TD_RING pointer to KSEG1 */
 264         lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
 265         lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
 266
 267
 268         spin_lock_init(&lp->lock);
 269
 270         /* just use the rx dma irq */
 271         dev->irq = lp->rx_irq;
 272
 273         dev->priv = lp;
 274         lp->dev = dev;
 275
 276         dev->open = rc32434_open;
 277         dev->stop = rc32434_close;
 278         dev->hard_start_xmit = rc32434_send_packet;
 279         dev->get_stats  = rc32434_get_stats;
 280         dev->set_multicast_list = &rc32434_multicast_list;
 281         dev->tx_timeout = rc32434_tx_timeout;
 282         dev->watchdog_timeo = RC32434_TX_TIMEOUT;
 283
 284         netif_napi_add(dev, &lp->napi, rc32434_poll, 64);
 285         lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
 286         tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
 287
 288         if ((err = register_netdev(dev))) {
 289                 printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
 290                 free_netdev(dev);
 291                 retval = -EINVAL;
 292                 goto probe_err_out;
 293         }
 294
 295         INFO("Rx IRQ %d, Tx IRQ %d, ", lp->rx_irq, lp->tx_irq);
 296         for (i = 0; i < 6; i++) {
 297                 printk("%2.2x", dev->dev_addr[i]);
 298                 if (i<5)
 299                         printk(":");
 300         }
 301         printk("\n");
 302
 303         return 0;
 304
 305  probe_err_out:
 306         rc32434_cleanup_module();
 307         ERR(" failed.  Returns %d\n", retval);
 308         return retval;
 309
 310 }
 311
 312 static int rc32434_remove(struct platform_device *pdev)
 313 {
 314         struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data;
 315
 316         if (bif->dev != NULL) {
 317                 struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
 318                 if (lp != NULL) {
 319                         if (lp->eth_regs)
 320                                 iounmap((void*)lp->eth_regs);
 321                         if (lp->rx_dma_regs)
 322                                 iounmap((void*)lp->rx_dma_regs);
 323                         if (lp->tx_dma_regs)
 324                                 iounmap((void*)lp->tx_dma_regs);
 325                         if (lp->td_ring)
 326                                 kfree((void*)KSEG0ADDR(lp->td_ring));
 327
 328 #ifdef RC32434_PROC_DEBUG
 329                         if (lp->ps) {
 330                                 remove_proc_entry(bif->name, proc_net);
 331                         }
 332 #endif
 333                         kfree(lp);
 334                 }
 335
 336                 platform_set_drvdata(pdev, NULL);
 337                 unregister_netdev(bif->dev);
 338                 free_netdev(bif->dev);
 339                 kfree(bif->dev);
 340         }
 341         return 0;
 342 }
 343
 344
 345 static int rc32434_open(struct net_device *dev)
 346 {
 347         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 348
 349         /* Initialize */
 350         if (rc32434_init(dev)) {
 351                 ERR("Error: cannot open the Ethernet device\n");
 352                 return -EAGAIN;
 353         }
 354
 355         /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
 356         if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
 357                   IRQF_SHARED | IRQF_DISABLED,
 358                         "Korina ethernet Rx", dev)) {
 359                 ERR(": unable to get Rx DMA IRQ %d\n",
 360                     lp->rx_irq);
 361                 return -EAGAIN;
 362         }
 363         if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
 364                   IRQF_SHARED | IRQF_DISABLED,
 365                         "Korina ethernet Tx", dev)) {
 366                 ERR(": unable to get Tx DMA IRQ %d\n",
 367                     lp->tx_irq);
 368                 free_irq(lp->rx_irq, dev);
 369                 return -EAGAIN;
 370         }
 371
 372 #ifdef  RC32434_REVISION
 373         /* Install handler for overrun error. */
 374         if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
 375                         IRQF_SHARED | IRQF_DISABLED,
 376                         "Ethernet Overflow", dev)) {
 377                 ERR(": unable to get OVR IRQ %d\n",
 378                     lp->ovr_irq);
 379                 free_irq(lp->rx_irq, dev);
 380                 free_irq(lp->tx_irq, dev);
 381                 return -EAGAIN;
 382         }
 383 #endif
 384
 385         /* Install handler for underflow error. */
 386         if (request_irq(lp->und_irq, &rc32434_und_interrupt,
 387                         IRQF_SHARED | IRQF_DISABLED,
 388                         "Ethernet Underflow", dev)) {
 389                 ERR(": unable to get UND IRQ %d\n",
 390                     lp->und_irq);
 391                 free_irq(lp->rx_irq, dev);
 392                 free_irq(lp->tx_irq, dev);
 393 #ifdef  RC32434_REVISION
 394                 free_irq(lp->ovr_irq, dev);
 395 #endif
 396                 return -EAGAIN;
 397         }
 398
 399
 400         return 0;
 401 }
 402
 403
 404
 405
 406 static int rc32434_close(struct net_device *dev)
 407 {
 408         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 409         u32 tmp;
 410
 411         /* Disable interrupts */
 412         disable_irq(lp->rx_irq);
 413         disable_irq(lp->tx_irq);
 414 #ifdef  RC32434_REVISION
 415         disable_irq(lp->ovr_irq);
 416 #endif
 417         disable_irq(lp->und_irq);
 418
 419         tmp = __raw_readl(&lp->tx_dma_regs->dmasm);
 420         tmp = tmp | DMASM_f_m | DMASM_e_m;
 421         __raw_writel(tmp, &lp->tx_dma_regs->dmasm);
 422
 423         tmp = __raw_readl(&lp->rx_dma_regs->dmasm);
 424         tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
 425         __raw_writel(tmp, &lp->rx_dma_regs->dmasm);
 426
 427         free_irq(lp->rx_irq, dev);
 428         free_irq(lp->tx_irq, dev);
 429 #ifdef  RC32434_REVISION
 430         free_irq(lp->ovr_irq, dev);
 431 #endif
 432         free_irq(lp->und_irq, dev);
 433         return 0;
 434 }
 435
 436
 437 /* transmit packet */
 438 static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
 439 {
 440         struct rc32434_local            *lp = (struct rc32434_local *)dev->priv;
 441         unsigned long                   flags;
 442         u32                                     length;
 443         DMAD_t                          td;
 444
 445
 446         spin_lock_irqsave(&lp->lock, flags);
 447
 448         td = &lp->td_ring[lp->tx_chain_tail];
 449
 450         /* stop queue when full, drop pkts if queue already full */
 451         if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
 452                 lp->tx_full = 1;
 453
 454                 if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
 455                         netif_stop_queue(dev);
 456                 }
 457                 else {
 458                         lp->stats.tx_dropped++;
 459                         dev_kfree_skb_any(skb);
 460                         spin_unlock_irqrestore(&lp->lock, flags);
 461                         return 1;
 462                 }
 463         }
 464
 465         lp->tx_count ++;
 466
 467         lp->tx_skb[lp->tx_chain_tail] = skb;
 468
 469         length = skb->len;
 470         dma_cache_wback((u32)skb->data, skb->len);
 471
 472         /* Setup the transmit descriptor. */
 473         dma_cache_inv((u32) td, sizeof(*td));
 474         td->ca = CPHYSADDR(skb->data);
 475
 476         if(__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
 477                 if( lp->tx_chain_status == empty ) {
 478                         td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /*  Update tail      */
 479                         lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /*   Move tail       */
 480                         __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR    */
 481                         lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
 482                 }
 483                 else {
 484                         td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m;                                 /* Update tail */
 485                         lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
 486                         lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
 487                         lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
 488                         __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
 489                         lp->tx_chain_head = lp->tx_chain_tail;                                                  /* Move head to tail */
 490                         lp->tx_chain_status = empty;
 491                 }
 492         }
 493         else {
 494                 if( lp->tx_chain_status == empty ) {
 495                         td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
 496                         lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
 497                         lp->tx_chain_status = filled;
 498                 }
 499                 else {
 500                         td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m;                                /* Update tail */
 501                         lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &=  ~(DMAD_cof_m);          /* Link to prev */
 502                         lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link =  CPHYSADDR(td);              /* Link to prev */
 503                         lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK;                          /* Move tail */
 504                 }
 505         }
 506         dma_cache_wback((u32) td, sizeof(*td));
 507
 508         dev->trans_start = jiffies;
 509
 510         spin_unlock_irqrestore(&lp->lock, flags);
 511
 512         return 0;
 513 }
 514
 515
 516 /* Ethernet MII-PHY Handler */
 517 static void rc32434_mii_handler(unsigned long data)
 518 {
 519         struct net_device *dev = (struct net_device *)data;
 520         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 521         unsigned long   flags;
 522         unsigned long duplex_status;
 523         int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
 524
 525         spin_lock_irqsave(&lp->lock, flags);
 526
 527         /* Two ports are using the same MII, the difference is the PHY address */
 528         __raw_writel(0, &rc32434_eth0_regs->miimcfg);
 529         __raw_writel(0, &rc32434_eth0_regs->miimcmd);
 530         __raw_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
 531         __raw_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
 532         while(__raw_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
 533
 534         ERR("irq:%x             port_addr:%x    RDD:%x\n",
 535             lp->rx_irq, port_addr, __raw_readl(&rc32434_eth0_regs->miimrdd));
 536         duplex_status = (__raw_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
 537         if(duplex_status != lp->duplex_mode) {
 538                 ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
 539                 lp->duplex_mode = duplex_status;
 540                 rc32434_restart(dev);
 541         }
 542
 543         lp->mii_phy_timer.expires = jiffies + 10 * HZ;
 544         add_timer(&lp->mii_phy_timer);
 545
 546         spin_unlock_irqrestore(&lp->lock, flags);
 547
 548 }
 549
 550 #ifdef  RC32434_REVISION
 551 /* Ethernet Rx Overflow interrupt */
 552 static irqreturn_t
 553 rc32434_ovr_interrupt(int irq, void *dev_id)
 554 {
 555         struct net_device *dev = (struct net_device *)dev_id;
 556         struct rc32434_local *lp;
 557         unsigned int ovr;
 558         irqreturn_t retval = IRQ_NONE;
 559
 560         ASSERT(dev != NULL);
 561
 562         lp = (struct rc32434_local *)dev->priv;
 563         spin_lock(&lp->lock);
 564         ovr = __raw_readl(&lp->eth_regs->ethintfc);
 565
 566         if(ovr & ETHINTFC_ovr_m) {
 567                 netif_stop_queue(dev);
 568
 569                 /* clear OVR bit */
 570                 __raw_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
 571
 572                 /* Restart interface */
 573                 rc32434_restart(dev);
 574                 retval = IRQ_HANDLED;
 575         }
 576         spin_unlock(&lp->lock);
 577
 578         return retval;
 579 }
 580
 581 #endif
 582
 583
 584 /* Ethernet Tx Underflow interrupt */
 585 static irqreturn_t
 586 rc32434_und_interrupt(int irq, void *dev_id)
 587 {
 588         struct net_device *dev = (struct net_device *)dev_id;
 589         struct rc32434_local *lp;
 590         unsigned int und;
 591         irqreturn_t retval = IRQ_NONE;
 592
 593         ASSERT(dev != NULL);
 594
 595         lp = (struct rc32434_local *)dev->priv;
 596
 597         spin_lock(&lp->lock);
 598
 599         und = __raw_readl(&lp->eth_regs->ethintfc);
 600
 601         if(und & ETHINTFC_und_m) {
 602                 netif_stop_queue(dev);
 603
 604                 __raw_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
 605
 606                 /* Restart interface */
 607                 rc32434_restart(dev);
 608                 retval = IRQ_HANDLED;
 609         }
 610
 611         spin_unlock(&lp->lock);
 612
 613         return retval;
 614 }
 615
 616
 617 /* Ethernet Rx DMA interrupt */
 618 static irqreturn_t
 619 rc32434_rx_dma_interrupt(int irq, void *dev_id)
 620 {
 621         struct net_device *dev = (struct net_device *)dev_id;
 622         struct rc32434_local* lp;
 623         volatile u32 dmas,dmasm;
 624         irqreturn_t retval;
 625
 626         ASSERT(dev != NULL);
 627
 628         lp = (struct rc32434_local *)dev->priv;
 629
 630         dmas = __raw_readl(&lp->rx_dma_regs->dmas);
 631         if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
 632                 /* Mask D H E bit in Rx DMA */
 633                 dmasm = __raw_readl(&lp->rx_dma_regs->dmasm);
 634                 __raw_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
 635                 netif_rx_schedule(dev, &lp->napi);
 636
 637                 if (dmas & DMAS_e_m)
 638                         ERR(": DMA error\n");
 639
 640                 retval = IRQ_HANDLED;
 641         }
 642         else
 643                 retval = IRQ_NONE;
 644
 645         return retval;
 646 }
 647
 648
 649 static int rc32434_rx(struct net_device *dev, int limit)
 650 {
 651         struct rc32434_local *lp = netdev_priv(dev);
 652         volatile DMAD_t  rd = &lp->rd_ring[lp->rx_next_done];
 653         struct sk_buff *skb, *skb_new;
 654         u8 *pkt_buf;
 655         u32 devcs, pkt_len, dmas, rx_free_desc;
 656         u32 pktuncrc_len;
 657         int count;
 658
 659         dma_cache_inv((u32)rd, sizeof(*rd));
 660         for (count = 0; count < limit; count++) {
 661                 /* init the var. used for the later operations within the while loop */
 662                 skb_new = NULL;
 663                 devcs = rd->devcs;
 664                 pkt_len = RCVPKT_LENGTH(devcs);
 665                 skb = lp->rx_skb[lp->rx_next_done];
 666
 667                 if ((devcs & ( ETHRX_ld_m)) !=  ETHRX_ld_m) {
 668                         /* check that this is a whole packet */
 669                         /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
 670                         lp->stats.rx_errors++;
 671                         lp->stats.rx_dropped++;
 672                 }
 673                 else if ( (devcs & ETHRX_rok_m)  ) {
 674
 675                                 /* must be the (first and) last descriptor then */
 676                                 pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
 677
 678                                 pktuncrc_len = pkt_len - 4;
 679                                 /* invalidate the cache */
 680                                 dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
 681
 682                                 /* Malloc up new buffer. */
 683                                 skb_new = netdev_alloc_skb(dev, RC32434_RBSIZE + 2);
 684
 685                                 if (skb_new != NULL){
 686                                         /* Make room */
 687                                         skb_put(skb, pktuncrc_len);
 688
 689                                         skb->protocol = eth_type_trans(skb, dev);
 690
 691                                         /* pass the packet to upper layers */
 692                                         netif_receive_skb(skb);
 693
 694                                         dev->last_rx = jiffies;
 695                                         lp->stats.rx_packets++;
 696                                         lp->stats.rx_bytes += pktuncrc_len;
 697
 698                                         if (IS_RCV_MP(devcs))
 699                                                 lp->stats.multicast++;
 700
 701                                         /* 16 bit align */
 702                                         skb_reserve(skb_new, 2);
 703
 704                                         skb_new->dev = dev;
 705                                         lp->rx_skb[lp->rx_next_done] = skb_new;
 706                                 }
 707                                 else {
 708                                         ERR("no memory, dropping rx packet.\n");
 709                                         lp->stats.rx_errors++;
 710                                         lp->stats.rx_dropped++;
 711                                 }
 712                 }
 713                 else {
 714                         /* This should only happen if we enable accepting broken packets */
 715                         lp->stats.rx_errors++;
 716                         lp->stats.rx_dropped++;
 717
 718                         /* add statistics counters */
 719                         if (IS_RCV_CRC_ERR(devcs)) {
 720                                 DBG(2, "RX CRC error\n");
 721                                 lp->stats.rx_crc_errors++;
 722                         }
 723                         else if (IS_RCV_LOR_ERR(devcs)) {
 724                                 DBG(2, "RX LOR error\n");
 725                                 lp->stats.rx_length_errors++;
 726                         }
 727                         else if (IS_RCV_LE_ERR(devcs)) {
 728                                 DBG(2, "RX LE error\n");
 729                                 lp->stats.rx_length_errors++;
 730                         }
 731                         else if (IS_RCV_OVR_ERR(devcs)) {
 732                                 lp->stats.rx_over_errors++;
 733                         }
 734                         else if (IS_RCV_CV_ERR(devcs)) {
 735                                 /* code violation */
 736                                 DBG(2, "RX CV error\n");
 737                                 lp->stats.rx_frame_errors++;
 738                         }
 739                         else if (IS_RCV_CES_ERR(devcs)) {
 740                                 DBG(2, "RX Preamble error\n");
 741                         }
 742                 }
 743                 rd->devcs = 0;
 744
 745                 /* restore descriptor's curr_addr */
 746                 if(skb_new) {
 747                         rd->ca = CPHYSADDR(skb_new->data);
 748                 }
 749                 else
 750                         rd->ca = CPHYSADDR(skb->data);
 751
 752                 rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
 753                 lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &=  ~(DMAD_cod_m);
 754
 755                 lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
 756                 dma_cache_wback((u32)rd, sizeof(*rd));
 757                 rd = &lp->rd_ring[lp->rx_next_done];
 758                 __raw_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
 759         }
 760
 761         dmas = __raw_readl(&lp->rx_dma_regs->dmas);
 762
 763         if(dmas & DMAS_h_m) {
 764                 /* Mask off halt and error bits */
 765                 __raw_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
 766 #ifdef RC32434_PROC_DEBUG
 767                 lp->dma_halt_cnt++;
 768 #endif
 769                 rd->devcs = 0;
 770                 skb = lp->rx_skb[lp->rx_next_done];
 771                 rd->ca = CPHYSADDR(skb->data);
 772                 dma_cache_wback((u32)rd, sizeof(*rd));
 773                 rc32434_chain_rx(lp,rd);
 774         }
 775
 776         return count;
 777 }
 778
 779 static int rc32434_poll(struct napi_struct *napi, int budget)
 780 {
 781         struct rc32434_local *lp =
 782                 container_of(napi, struct rc32434_local, napi);
 783         struct net_device *dev = lp->dev;
 784         int work_done;
 785
 786         work_done = rc32434_rx(dev, budget);
 787         if (work_done < budget) {
 788                 netif_rx_complete(dev, napi);
 789
 790                 /* Mask off interrupts */
 791                 writel(readl(&lp->rx_dma_regs->dmasm) &
 792                         (DMASM_d_m | DMASM_h_m |DMASM_e_m),
 793                         &lp->rx_dma_regs->dmasm);
 794         }
 795         return work_done;
 796 }
 797
 798
 799
 800 /* Ethernet Tx DMA interrupt */
 801 static irqreturn_t
 802 rc32434_tx_dma_interrupt(int irq, void *dev_id)
 803 {
 804         struct net_device *dev = (struct net_device *)dev_id;
 805         struct rc32434_local *lp;
 806         volatile u32 dmas,dmasm;
 807         irqreturn_t retval;
 808
 809         ASSERT(dev != NULL);
 810
 811         lp = (struct rc32434_local *)dev->priv;
 812
 813         dmas = __raw_readl(&lp->tx_dma_regs->dmas);
 814
 815         if (dmas & (DMAS_f_m | DMAS_e_m)) {
 816                 dmasm = __raw_readl(&lp->tx_dma_regs->dmasm);
 817                 /* Mask F E bit in Tx DMA */
 818                 __raw_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
 819
 820                 tasklet_hi_schedule(lp->tx_tasklet);
 821
 822                 if(lp->tx_chain_status == filled && (__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
 823                         __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
 824                         lp->tx_chain_status = empty;
 825                         lp->tx_chain_head = lp->tx_chain_tail;
 826                         dev->trans_start = jiffies;
 827                 }
 828
 829                 if (dmas & DMAS_e_m)
 830                         ERR(": DMA error\n");
 831
 832                 retval = IRQ_HANDLED;
 833         }
 834         else
 835                 retval = IRQ_NONE;
 836
 837         return retval;
 838 }
 839
 840
 841 static void rc32434_tx_tasklet(unsigned long tx_data_dev)
 842 {
 843         struct net_device *dev = (struct net_device *)tx_data_dev;
 844         struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
 845         volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
 846         u32 devcs;
 847         unsigned long   flags;
 848         volatile u32 dmas;
 849
 850         spin_lock_irqsave(&lp->lock, flags);
 851
 852         /* process all desc that are done */
 853         while(IS_DMA_FINISHED(td->control)) {
 854                 if(lp->tx_full == 1) {
 855                         netif_wake_queue(dev);
 856                         lp->tx_full = 0;
 857                 }
 858
 859                 devcs = lp->td_ring[lp->tx_next_done].devcs;
 860                 if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
 861                         lp->stats.tx_errors++;
 862                         lp->stats.tx_dropped++;
 863
 864                         /* should never happen */
 865                         DBG(1, __FUNCTION__ ": split tx ignored\n");
 866                 }
 867                 else if (IS_TX_TOK(devcs)) {
 868                         lp->stats.tx_packets++;
 869                         lp->stats.tx_bytes+=lp->tx_skb[lp->tx_next_done]->len;
 870                 }
 871                 else {
 872                         lp->stats.tx_errors++;
 873                         lp->stats.tx_dropped++;
 874
 875                         /* underflow */
 876                         if (IS_TX_UND_ERR(devcs))
 877                                 lp->stats.tx_fifo_errors++;
 878
 879                         /* oversized frame */
 880                         if (IS_TX_OF_ERR(devcs))
 881                                 lp->stats.tx_aborted_errors++;
 882
 883                         /* excessive deferrals */
 884                         if (IS_TX_ED_ERR(devcs))
 885                                 lp->stats.tx_carrier_errors++;
 886
 887                         /* collisions: medium busy */
 888                         if (IS_TX_EC_ERR(devcs))
 889                                 lp->stats.collisions++;
 890
 891                         /* late collision */
 892                         if (IS_TX_LC_ERR(devcs))
 893                                 lp->stats.tx_window_errors++;
 894
 895                 }
 896
 897                 /* We must always free the original skb */
 898                 if (lp->tx_skb[lp->tx_next_done] != NULL) {
 899                         dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
 900                         lp->tx_skb[lp->tx_next_done] = NULL;
 901                 }
 902
 903                 lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
 904                 lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
 905                 lp->td_ring[lp->tx_next_done].link = 0;
 906                 lp->td_ring[lp->tx_next_done].ca = 0;
 907                 lp->tx_count --;
 908
 909                 /* go on to next transmission */
 910                 lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
 911                 td = &lp->td_ring[lp->tx_next_done];
 912
 913         }
 914
 915         dmas = __raw_readl(&lp->tx_dma_regs->dmas);
 916         __raw_writel( ~dmas, &lp->tx_dma_regs->dmas);
 917
 918         /* Enable F E bit in Tx DMA */
 919         __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
 920         spin_unlock_irqrestore(&lp->lock, flags);
 921
 922 }
 923
 924
 925 static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
 926 {
 927         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 928         return &lp->stats;
 929 }
 930
 931
 932 /*
 933  * Set or clear the multicast filter for this adaptor.
 934  */
 935 static void rc32434_multicast_list(struct net_device *dev)
 936 {
 937         /* listen to broadcasts always and to treat     */
 938         /*       IFF bits independantly */
 939         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 940         unsigned long flags;
 941         u32 recognise = ETHARC_ab_m;            /* always accept broadcasts */
 942
 943         if (dev->flags & IFF_PROMISC)                   /* set promiscuous mode */
 944                 recognise |= ETHARC_pro_m;
 945
 946         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
 947                 recognise |= ETHARC_am_m;               /* all multicast & bcast */
 948         else if (dev->mc_count > 0) {
 949                 DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
 950                 recognise |= ETHARC_am_m;               /* for the time being */
 951         }
 952
 953         spin_lock_irqsave(&lp->lock, flags);
 954         __raw_writel(recognise, &lp->eth_regs->etharc);
 955         spin_unlock_irqrestore(&lp->lock, flags);
 956 }
 957
 958
 959 static void rc32434_tx_timeout(struct net_device *dev)
 960 {
 961         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 962         unsigned long flags;
 963
 964         spin_lock_irqsave(&lp->lock, flags);
 965         rc32434_restart(dev);
 966         spin_unlock_irqrestore(&lp->lock, flags);
 967
 968 }
 969
 970
 971 /*
 972  * Initialize the RC32434 ethernet controller.
 973  */
 974 static int rc32434_init(struct net_device *dev)
 975 {
 976         struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
 977         int i, j;
 978
 979         /* Disable DMA */
 980         rc32434_abort_tx(dev);
 981         rc32434_abort_rx(dev);
 982
 983         /* reset ethernet logic */
 984         __raw_writel(0, &lp->eth_regs->ethintfc);
 985         while((__raw_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
 986                 dev->trans_start = jiffies;
 987
 988         /* Enable Ethernet Interface */
 989         __raw_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
 990
 991         tasklet_disable(lp->tx_tasklet);
 992
 993         /* Initialize the transmit Descriptors */
 994         for (i = 0; i < RC32434_NUM_TDS; i++) {
 995                 lp->td_ring[i].control = DMAD_iof_m;
 996                 lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
 997                 lp->td_ring[i].ca = 0;
 998                 lp->td_ring[i].link = 0;
 999                 if (lp->tx_skb[i] != NULL) {
1000                         dev_kfree_skb_any(lp->tx_skb[i]);
1001                         lp->tx_skb[i] = NULL;
1002                 }
1003         }
1004         lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =      lp->tx_full = lp->tx_count = 0;
1005         lp->    tx_chain_status = empty;
1006
1007         /*
1008          * Initialize the receive descriptors so that they
1009          * become a circular linked list, ie. let the last
1010          * descriptor point to the first again.
1011          */
1012         for (i=0; i<RC32434_NUM_RDS; i++) {
1013                 struct sk_buff *skb = lp->rx_skb[i];
1014
1015                 if (lp->rx_skb[i] == NULL) {
1016                         skb = dev_alloc_skb(RC32434_RBSIZE + 2);
1017                         if (skb == NULL) {
1018                                 ERR("No memory in the system\n");
1019                                 for (j = 0; j < RC32434_NUM_RDS; j ++)
1020                                         if (lp->rx_skb[j] != NULL)
1021                                                 dev_kfree_skb_any(lp->rx_skb[j]);
1022
1023                                 return 1;
1024                         }
1025                         else {
1026                                 skb->dev = dev;
1027                                 skb_reserve(skb, 2);
1028                                 lp->rx_skb[i] = skb;
1029                                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
1030
1031                         }
1032                 }
1033                 lp->rd_ring[i].control =        DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
1034                 lp->rd_ring[i].devcs = 0;
1035                 lp->rd_ring[i].ca = CPHYSADDR(skb->data);
1036                 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
1037
1038         }
1039         /* loop back */
1040         lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
1041         lp->rx_next_done   = 0;
1042
1043         lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
1044         lp->rx_chain_head = 0;
1045         lp->rx_chain_tail = 0;
1046         lp->rx_chain_status = empty;
1047
1048         __raw_writel(0, &lp->rx_dma_regs->dmas);
1049         /* Start Rx DMA */
1050         rc32434_start_rx(lp, &lp->rd_ring[0]);
1051
1052         /* Enable F E bit in Tx DMA */
1053         __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
1054         /* Enable D H E bit in Rx DMA */
1055         __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1056
1057         /* Accept only packets destined for this Ethernet device address */
1058         __raw_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
1059
1060         /* Set all Ether station address registers to their initial values */
1061         __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
1062         __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
1063
1064         __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
1065         __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
1066
1067         __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
1068         __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
1069
1070         __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
1071         __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
1072
1073
1074         /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
1075         __raw_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
1076         //ETHMAC2_flc_m         ETHMAC2_fd_m    lp->duplex_mode
1077
1078         /* Back to back inter-packet-gap */
1079         __raw_writel(0x15, &lp->eth_regs->ethipgt);
1080         /* Non - Back to back inter-packet-gap */
1081         __raw_writel(0x12, &lp->eth_regs->ethipgr);
1082
1083         /* Management Clock Prescaler Divisor */
1084         /* Clock independent setting */
1085         __raw_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
1086                        &lp->eth_regs->ethmcp);
1087
1088         /* don't transmit until fifo contains 48b */
1089         __raw_writel(48, &lp->eth_regs->ethfifott);
1090
1091         __raw_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
1092
1093         napi_enable(&lp->napi);
1094         tasklet_enable(lp->tx_tasklet);
1095
1096         netif_start_queue(dev);
1097
1098         return 0;
1099 }
1100
1101 static struct platform_driver korina_driver = {
1102         .driver.name = "korina",
1103         .probe = rc32434_probe,
1104         .remove = rc32434_remove,
1105 };
1106
1107 static int __init rc32434_init_module(void)
1108 {
1109         return platform_driver_register(&korina_driver);
1110 }
1111
1112 static void rc32434_cleanup_module(void)
1113 {
1114         return platform_driver_unregister(&korina_driver);
1115 }
1116
1117 module_init(rc32434_init_module);
1118 module_exit(rc32434_cleanup_module);