1 From 693f0ff3dbc53f910dff57ac15c324f7a94cc0ad Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 23:50:53 +0100
4 Subject: [PATCH 509/513] net-next: mediatek: add support for mt7621
6 Add support for SoCs from the mt7620 family. This include mt7620 and mt7621.
7 These all have one dedicated external gbit port and a builtin 5 port 100mbit
8 switch. Additionally one of the 5 switch ports can be changed to become an
9 additional gbit port that we can attach a phy to. This patch includes
10 rudimentary code to power up the switch. There are a lot of magic values
11 that get written to the switch and the internal phys. These values come
12 straight from the SDK driver.
14 Signed-off-by: John Crispin <blogic@openwrt.org>
15 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
16 Signed-off-by: Michael Lee <igvtee@gmail.com>
18 drivers/net/ethernet/mediatek/soc_mt7621.c | 184 ++++++++++++++++++++++++++++
19 1 file changed, 184 insertions(+)
20 create mode 100644 drivers/net/ethernet/mediatek/soc_mt7621.c
22 diff --git a/drivers/net/ethernet/mediatek/soc_mt7621.c b/drivers/net/ethernet/mediatek/soc_mt7621.c
24 index 0000000..d6f7f23
26 +++ b/drivers/net/ethernet/mediatek/soc_mt7621.c
28 +/* This program is free software; you can redistribute it and/or modify
29 + * it under the terms of the GNU General Public License as published by
30 + * the Free Software Foundation; version 2 of the License
32 + * This program is distributed in the hope that it will be useful,
33 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 + * GNU General Public License for more details.
37 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
38 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
39 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
42 +#include <linux/module.h>
43 +#include <linux/platform_device.h>
44 +#include <linux/if_vlan.h>
45 +#include <linux/of_net.h>
47 +#include <asm/mach-ralink/ralink_regs.h>
49 +#include "mtk_eth_soc.h"
50 +#include "gsw_mt7620.h"
54 +#define MT7620A_CDMA_CSG_CFG 0x400
55 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
56 +#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
57 +#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
58 +#define MT7620A_RESET_FE BIT(21)
59 +#define MT7621_RESET_FE BIT(6)
60 +#define MT7620A_RESET_ESW BIT(23)
61 +#define MT7620_L4_VALID BIT(23)
62 +#define MT7621_L4_VALID BIT(24)
64 +#define MT7620_TX_DMA_UDF BIT(15)
65 +#define MT7621_TX_DMA_UDF BIT(19)
66 +#define TX_DMA_FP_BMAP ((0xff) << 19)
68 +#define CDMA_ICS_EN BIT(2)
69 +#define CDMA_UCS_EN BIT(1)
70 +#define CDMA_TCS_EN BIT(0)
72 +#define GDMA_ICS_EN BIT(22)
73 +#define GDMA_TCS_EN BIT(21)
74 +#define GDMA_UCS_EN BIT(20)
76 +/* frame engine counters */
77 +#define MT7620_REG_MIB_OFFSET 0x1000
78 +#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
79 +#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
80 +#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
82 +#define MT7621_REG_MIB_OFFSET 0x2000
83 +#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
84 +#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
85 +#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
87 +#define GSW_REG_GDMA1_MAC_ADRL 0x508
88 +#define GSW_REG_GDMA1_MAC_ADRH 0x50C
90 +#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
91 +#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
93 +/* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
94 + * but after test it should be BIT(13).
96 +#define MT7620_FE_GDM1_AF BIT(13)
97 +#define MT7621_FE_GDM1_AF BIT(28)
98 +#define MT7621_FE_GDM2_AF BIT(29)
100 +static const u16 mt7621_reg_table[FE_REG_COUNT] = {
101 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
102 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
103 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
104 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
105 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
106 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
107 + [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
108 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
109 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
110 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
111 + [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
112 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
113 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
114 + [FE_REG_FE_DMA_VID_BASE] = 0,
115 + [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
116 + [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
117 + [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
120 +static int mt7621_gsw_config(struct fe_priv *priv)
122 + if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
123 + mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
128 +static void mt7621_fe_reset(void)
130 + fe_reset(MT7621_RESET_FE);
133 +static void mt7621_rxvlan_config(bool enable)
136 + fe_w32(1, MT7621_CDMP_EG_CTRL);
138 + fe_w32(0, MT7621_CDMP_EG_CTRL);
141 +static int mt7621_fwd_config(struct fe_priv *priv)
143 + struct net_device *dev = priv_netdev(priv);
145 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff,
146 + MT7620A_GDMA1_FWD_CFG);
148 + /* mt7621 don't have txcsum config */
149 + mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
150 + mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
151 + (priv->flags & FE_FLAG_RX_VLAN_CTAG));
156 +static void mt7621_tx_dma(struct fe_tx_dma *txd)
158 + txd->txd4 = BIT(25);
161 +static void mt7621_init_data(struct fe_soc_data *data,
162 + struct net_device *netdev)
164 + struct fe_priv *priv = netdev_priv(netdev);
166 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
167 + FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT |
168 + FE_FLAG_HAS_SWITCH;
170 + netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
171 + NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
172 + NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
175 +static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
177 + unsigned long flags;
179 + spin_lock_irqsave(&priv->page_lock, flags);
180 + fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
181 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
182 + GSW_REG_GDMA1_MAC_ADRL);
183 + spin_unlock_irqrestore(&priv->page_lock, flags);
186 +static struct fe_soc_data mt7621_data = {
187 + .init_data = mt7621_init_data,
188 + .reset_fe = mt7621_fe_reset,
189 + .set_mac = mt7621_set_mac,
190 + .fwd_config = mt7621_fwd_config,
191 + .tx_dma = mt7621_tx_dma,
192 + .switch_init = mtk_gsw_init,
193 + .switch_config = mt7621_gsw_config,
194 + .reg_table = mt7621_reg_table,
195 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
196 + .rx_int = RT5350_RX_DONE_INT,
197 + .tx_int = RT5350_TX_DONE_INT,
198 + .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
199 + .checksum_bit = MT7621_L4_VALID,
200 + .has_carrier = mt7620_has_carrier,
201 + .mdio_read = mt7620_mdio_read,
202 + .mdio_write = mt7620_mdio_write,
203 + .mdio_adjust_link = mt7620_mdio_link_adjust,
206 +const struct of_device_id of_fe_match[] = {
207 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
211 +MODULE_DEVICE_TABLE(of, of_fe_match);