target/linux/ramips/patches-4.3/0505-net-next-mediatek-add-support-for-rt2880.patch

   1 From f8c8f4bd2a13e0cc060c93812377373d436f7f02 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 18 Nov 2015 03:13:05 +0100
   4 Subject: [PATCH 505/513] net-next: mediatek: add support for rt2880
   5
   6 rt2880 is the oldest SoC with this core. It has a single gBit port that will
   7 normally be attached to an external phy of switch. The patch also adds the
   8 code required to drive the mdio bus.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  12 Signed-off-by: Michael Lee <igvtee@gmail.com>
  13 ---
  14  drivers/net/ethernet/mediatek/mdio_rt2880.c |  222 +++++++++++++++++++++++++++
  15  drivers/net/ethernet/mediatek/mdio_rt2880.h |   23 +++
  16  drivers/net/ethernet/mediatek/soc_rt2880.c  |   76 +++++++++
  17  3 files changed, 321 insertions(+)
  18  create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
  19  create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
  20  create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
  21
  22 diff --git a/drivers/net/ethernet/mediatek/mdio_rt2880.c b/drivers/net/ethernet/mediatek/mdio_rt2880.c
  23 new file mode 100644
  24 index 0000000..eb9df6e
  25 --- /dev/null
  26 +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
  27 @@ -0,0 +1,222 @@
  28 +/*   This program is free software; you can redistribute it and/or modify
  29 + *   it under the terms of the GNU General Public License as published by
  30 + *   the Free Software Foundation; version 2 of the License
  31 + *
  32 + *   This program is distributed in the hope that it will be useful,
  33 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  34 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  35 + *   GNU General Public License for more details.
  36 + *
  37 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  38 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
  39 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  40 + */
  41 +
  42 +#include <linux/module.h>
  43 +#include <linux/kernel.h>
  44 +#include <linux/types.h>
  45 +#include <linux/of_net.h>
  46 +#include <linux/of_mdio.h>
  47 +
  48 +#include "mtk_eth_soc.h"
  49 +#include "mdio_rt2880.h"
  50 +#include "mdio.h"
  51 +
  52 +#define FE_MDIO_RETRY  1000
  53 +
  54 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
  55 +{
  56 +       switch (priv->phy->speed[0]) {
  57 +       case SPEED_1000:
  58 +               return "1000";
  59 +       case SPEED_100:
  60 +               return "100";
  61 +       case SPEED_10:
  62 +               return "10";
  63 +       }
  64 +
  65 +       return "?";
  66 +}
  67 +
  68 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
  69 +{
  70 +       u32 mdio_cfg;
  71 +
  72 +       if (!priv->link[0]) {
  73 +               netif_carrier_off(priv->netdev);
  74 +               netdev_info(priv->netdev, "link down\n");
  75 +               return;
  76 +       }
  77 +
  78 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
  79 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
  80 +                  FE_MDIO_CFG_GP1_FRC_EN;
  81 +
  82 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
  83 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
  84 +
  85 +       if (priv->phy->tx_fc[0])
  86 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
  87 +
  88 +       if (priv->phy->rx_fc[0])
  89 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
  90 +
  91 +       switch (priv->phy->speed[0]) {
  92 +       case SPEED_10:
  93 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
  94 +               break;
  95 +       case SPEED_100:
  96 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
  97 +               break;
  98 +       case SPEED_1000:
  99 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
 100 +               break;
 101 +       default:
 102 +               BUG();
 103 +       }
 104 +
 105 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
 106 +
 107 +       netif_carrier_on(priv->netdev);
 108 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
 109 +                   rt2880_speed_str(priv),
 110 +                   (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
 111 +}
 112 +
 113 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
 114 +{
 115 +       int retries;
 116 +
 117 +       retries = FE_MDIO_RETRY;
 118 +       while (1) {
 119 +               u32 t;
 120 +
 121 +               t = fe_r32(FE_MDIO_ACCESS);
 122 +               if ((t & BIT(31)) == 0)
 123 +                       return 0;
 124 +
 125 +               if (retries-- == 0)
 126 +                       break;
 127 +
 128 +               udelay(1);
 129 +       }
 130 +
 131 +       dev_err(priv->device, "MDIO operation timed out\n");
 132 +       return -ETIMEDOUT;
 133 +}
 134 +
 135 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 136 +{
 137 +       struct fe_priv *priv = bus->priv;
 138 +       int err;
 139 +       u32 t;
 140 +
 141 +       err = rt2880_mdio_wait_ready(priv);
 142 +       if (err)
 143 +               return 0xffff;
 144 +
 145 +       t = (phy_addr << 24) | (phy_reg << 16);
 146 +       fe_w32(t, FE_MDIO_ACCESS);
 147 +       t |= BIT(31);
 148 +       fe_w32(t, FE_MDIO_ACCESS);
 149 +
 150 +       err = rt2880_mdio_wait_ready(priv);
 151 +       if (err)
 152 +               return 0xffff;
 153 +
 154 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
 155 +                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
 156 +
 157 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
 158 +}
 159 +
 160 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 161 +{
 162 +       struct fe_priv *priv = bus->priv;
 163 +       int err;
 164 +       u32 t;
 165 +
 166 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
 167 +                phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
 168 +
 169 +       err = rt2880_mdio_wait_ready(priv);
 170 +       if (err)
 171 +               return err;
 172 +
 173 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
 174 +       fe_w32(t, FE_MDIO_ACCESS);
 175 +       t |= BIT(31);
 176 +       fe_w32(t, FE_MDIO_ACCESS);
 177 +
 178 +       return rt2880_mdio_wait_ready(priv);
 179 +}
 180 +
 181 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
 182 +{
 183 +       const __be32 *id = of_get_property(np, "reg", NULL);
 184 +       const __be32 *link;
 185 +       int size;
 186 +       int phy_mode;
 187 +
 188 +       if (!id || (be32_to_cpu(*id) != 0)) {
 189 +               pr_err("%s: invalid port id\n", np->name);
 190 +               return;
 191 +       }
 192 +
 193 +       priv->phy->phy_fixed[0] = of_get_property(np,
 194 +                                                 "mediatek,fixed-link", &size);
 195 +       if (priv->phy->phy_fixed[0] &&
 196 +           (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
 197 +               pr_err("%s: invalid fixed link property\n", np->name);
 198 +               priv->phy->phy_fixed[0] = NULL;
 199 +               return;
 200 +       }
 201 +
 202 +       phy_mode = of_get_phy_mode(np);
 203 +       switch (phy_mode) {
 204 +       case PHY_INTERFACE_MODE_RGMII:
 205 +               break;
 206 +       case PHY_INTERFACE_MODE_MII:
 207 +               break;
 208 +       case PHY_INTERFACE_MODE_RMII:
 209 +               break;
 210 +       default:
 211 +               if (!priv->phy->phy_fixed[0])
 212 +                       dev_err(priv->device, "port %d - invalid phy mode\n",
 213 +                               priv->phy->speed[0]);
 214 +               break;
 215 +       }
 216 +
 217 +       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
 218 +       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
 219 +               return;
 220 +
 221 +       if (priv->phy->phy_fixed[0]) {
 222 +               link = priv->phy->phy_fixed[0];
 223 +               priv->phy->speed[0] = be32_to_cpup(link++);
 224 +               priv->phy->duplex[0] = be32_to_cpup(link++);
 225 +               priv->phy->tx_fc[0] = be32_to_cpup(link++);
 226 +               priv->phy->rx_fc[0] = be32_to_cpup(link++);
 227 +
 228 +               priv->link[0] = 1;
 229 +               switch (priv->phy->speed[0]) {
 230 +               case SPEED_10:
 231 +                       break;
 232 +               case SPEED_100:
 233 +                       break;
 234 +               case SPEED_1000:
 235 +                       break;
 236 +               default:
 237 +                       dev_err(priv->device, "invalid link speed: %d\n",
 238 +                               priv->phy->speed[0]);
 239 +                       priv->phy->phy_fixed[0] = 0;
 240 +                       return;
 241 +               }
 242 +               dev_info(priv->device, "using fixed link parameters\n");
 243 +               rt2880_mdio_link_adjust(priv, 0);
 244 +               return;
 245 +       }
 246 +
 247 +       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0])
 248 +               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
 249 +}
 250 diff --git a/drivers/net/ethernet/mediatek/mdio_rt2880.h b/drivers/net/ethernet/mediatek/mdio_rt2880.h
 251 new file mode 100644
 252 index 0000000..6884894
 253 --- /dev/null
 254 +++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
 255 @@ -0,0 +1,23 @@
 256 +/*   This program is free software; you can redistribute it and/or modify
 257 + *   it under the terms of the GNU General Public License as published by
 258 + *   the Free Software Foundation; version 2 of the License
 259 + *
 260 + *   This program is distributed in the hope that it will be useful,
 261 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 262 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 263 + *   GNU General Public License for more details.
 264 + *
 265 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 266 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 267 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 268 + */
 269 +
 270 +#ifndef _RALINK_MDIO_RT2880_H__
 271 +#define _RALINK_MDIO_RT2880_H__
 272 +
 273 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
 274 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
 275 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
 276 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
 277 +
 278 +#endif
 279 diff --git a/drivers/net/ethernet/mediatek/soc_rt2880.c b/drivers/net/ethernet/mediatek/soc_rt2880.c
 280 new file mode 100644
 281 index 0000000..0792dab
 282 --- /dev/null
 283 +++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
 284 @@ -0,0 +1,76 @@
 285 +/*   This program is free software; you can redistribute it and/or modify
 286 + *   it under the terms of the GNU General Public License as published by
 287 + *   the Free Software Foundation; version 2 of the License
 288 + *
 289 + *   This program is distributed in the hope that it will be useful,
 290 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 291 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 292 + *   GNU General Public License for more details.
 293 + *
 294 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 295 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 296 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 297 + */
 298 +
 299 +#include <linux/module.h>
 300 +
 301 +#include <asm/mach-ralink/ralink_regs.h>
 302 +
 303 +#include "mtk_eth_soc.h"
 304 +#include "mdio_rt2880.h"
 305 +
 306 +#define RT2880_RESET_FE                        BIT(18)
 307 +
 308 +static void rt2880_init_data(struct fe_soc_data *data,
 309 +                            struct net_device *netdev)
 310 +{
 311 +       struct fe_priv *priv = netdev_priv(netdev);
 312 +
 313 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
 314 +               FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
 315 +       netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
 316 +       /* this should work according to the datasheet but actually does not*/
 317 +       /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
 318 +}
 319 +
 320 +void rt2880_fe_reset(void)
 321 +{
 322 +       fe_reset(RT2880_RESET_FE);
 323 +}
 324 +
 325 +static int rt2880_fwd_config(struct fe_priv *priv)
 326 +{
 327 +       int ret;
 328 +
 329 +       ret = fe_set_clock_cycle(priv);
 330 +       if (ret)
 331 +               return ret;
 332 +
 333 +       fe_fwd_config(priv);
 334 +       fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
 335 +       fe_csum_config(priv);
 336 +
 337 +       return ret;
 338 +}
 339 +
 340 +struct fe_soc_data rt2880_data = {
 341 +       .init_data = rt2880_init_data,
 342 +       .reset_fe = rt2880_fe_reset,
 343 +       .fwd_config = rt2880_fwd_config,
 344 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
 345 +       .checksum_bit = RX_DMA_L4VALID,
 346 +       .rx_int = FE_RX_DONE_INT,
 347 +       .tx_int = FE_TX_DONE_INT,
 348 +       .status_int = FE_CNT_GDM_AF,
 349 +       .mdio_read = rt2880_mdio_read,
 350 +       .mdio_write = rt2880_mdio_write,
 351 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
 352 +       .port_init = rt2880_port_init,
 353 +};
 354 +
 355 +const struct of_device_id of_fe_match[] = {
 356 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
 357 +       {},
 358 +};
 359 +
 360 +MODULE_DEVICE_TABLE(of, of_fe_match);
 361 --
 362 1.7.10.4
 363