1 From 322a9598692943961791ac6e5a3f385b379dcdc3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 14 Dec 2015 21:23:18 +0100
4 Subject: [PATCH 503/513] net-next: mediatek: add switch driver for mt7620
6 This driver is very basic and only provides basic init and irq support.
7 Switchdev support for this device will follow.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 drivers/net/ethernet/mediatek/gsw_mt7620.c | 255 ++++++++++++++++++++++++++++
12 drivers/net/ethernet/mediatek/gsw_mt7620.h | 117 +++++++++++++
13 2 files changed, 372 insertions(+)
14 create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.c
15 create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
17 diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.c b/drivers/net/ethernet/mediatek/gsw_mt7620.c
19 index 0000000..a37ed1b
21 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
23 +/* This program is free software; you can redistribute it and/or modify
24 + * it under the terms of the GNU General Public License as published by
25 + * the Free Software Foundation; version 2 of the License
27 + * This program is distributed in the hope that it will be useful,
28 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 + * GNU General Public License for more details.
32 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
33 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
34 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
37 +#include <linux/module.h>
38 +#include <linux/kernel.h>
39 +#include <linux/types.h>
40 +#include <linux/platform_device.h>
41 +#include <linux/of_device.h>
42 +#include <linux/of_irq.h>
44 +#include <ralink_regs.h>
46 +#include "mtk_eth_soc.h"
47 +#include "gsw_mt7620.h"
49 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
51 + iowrite32(val, gsw->base + reg);
54 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
56 + return ioread32(gsw->base + reg);
59 +static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
61 + struct fe_priv *priv = (struct fe_priv *)_priv;
62 + struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
64 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
66 + status = mtk_switch_r32(gsw, GSW_REG_ISR);
67 + if (status & PORT_IRQ_ST_CHG)
68 + for (i = 0; i <= max; i++) {
69 + u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
70 + int link = status & 0x1;
72 + if (link != priv->link[i])
73 + mt7620_print_link_state(priv, i, link,
77 + priv->link[i] = link;
79 + mtk_switch_w32(gsw, status, GSW_REG_ISR);
84 +static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
86 + u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
88 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
89 + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
91 + if (of_property_read_bool(np, "mediatek,mt7530")) {
94 + /* turn off ephy and set phy base addr to 12 */
95 + mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
96 + (0x1f << 24) | (0xc << 16),
99 + /* set MT7530 central align */
100 + val = mt7530_mdio_r32(gsw, 0x7830);
103 + mt7530_mdio_w32(gsw, 0x7830, val);
105 + val = mt7530_mdio_r32(gsw, 0x7a40);
107 + mt7530_mdio_w32(gsw, 0x7a40, val);
109 + mt7530_mdio_w32(gsw, 0x7a78, 0x855);
111 + /* global page 4 */
112 + _mt7620_mii_write(gsw, 1, 31, 0x4000);
114 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
116 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
118 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
120 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
121 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
122 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
123 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
124 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
125 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
127 + /* global page 3 */
128 + _mt7620_mii_write(gsw, 1, 31, 0x3000);
129 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
131 + /* global page 2 */
132 + _mt7620_mii_write(gsw, 1, 31, 0x2000);
134 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
135 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
136 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
137 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
138 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
139 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
141 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
142 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
143 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
144 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
145 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
146 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
148 + /* global page 1 */
149 + _mt7620_mii_write(gsw, 1, 31, 0x1000);
150 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
153 + /* global page 0 */
154 + _mt7620_mii_write(gsw, 1, 31, 0x8000);
155 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
156 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
157 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
158 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
160 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
161 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
162 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
163 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
165 + /* global page 2 */
166 + _mt7620_mii_write(gsw, 1, 31, 0xa000);
167 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
168 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
169 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
170 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
172 + /* CPU Port6 Force Link 1G, FC ON */
173 + mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
175 + /* Set Port 6 as CPU Port */
176 + mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
179 + if (gsw->port4 == PORT4_EPHY) {
180 + u32 val = rt_sysc_r32(SYSC_REG_CFG1);
183 + rt_sysc_w32(val, SYSC_REG_CFG1);
184 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
185 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
186 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
187 + pr_info("gsw: setting port4 to ephy mode\n");
191 +static const struct of_device_id mediatek_gsw_match[] = {
192 + { .compatible = "mediatek,mt7620-gsw" },
195 +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
197 +int mtk_gsw_init(struct fe_priv *priv)
199 + struct device_node *np = priv->switch_np;
200 + struct platform_device *pdev = of_find_device_by_node(np);
201 + struct mt7620_gsw *gsw;
206 + if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
209 + gsw = platform_get_drvdata(pdev);
210 + priv->soc->swpriv = gsw;
212 + mt7620_hw_init(gsw, np);
215 + request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
217 + mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
223 +static int mt7620_gsw_probe(struct platform_device *pdev)
225 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 + const char *port4 = NULL;
227 + struct mt7620_gsw *gsw;
228 + struct device_node *np;
230 + gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
234 + gsw->base = devm_ioremap_resource(&pdev->dev, res);
236 + return -EADDRNOTAVAIL;
238 + gsw->dev = &pdev->dev;
240 + of_property_read_string(np, "mediatek,port4", &port4);
241 + if (port4 && !strcmp(port4, "ephy"))
242 + gsw->port4 = PORT4_EPHY;
243 + else if (port4 && !strcmp(port4, "gmac"))
244 + gsw->port4 = PORT4_EXT;
246 + gsw->port4 = PORT4_EPHY;
248 + gsw->irq = irq_of_parse_and_map(np, 0);
250 + platform_set_drvdata(pdev, gsw);
255 +static int mt7620_gsw_remove(struct platform_device *pdev)
257 + platform_set_drvdata(pdev, NULL);
262 +static struct platform_driver gsw_driver = {
263 + .probe = mt7620_gsw_probe,
264 + .remove = mt7620_gsw_remove,
266 + .name = "mt7620-gsw",
267 + .owner = THIS_MODULE,
268 + .of_match_table = mediatek_gsw_match,
272 +module_platform_driver(gsw_driver);
274 +MODULE_LICENSE("GPL");
275 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
276 +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
277 +MODULE_VERSION(MTK_FE_DRV_VERSION);
278 diff --git a/drivers/net/ethernet/mediatek/gsw_mt7620.h b/drivers/net/ethernet/mediatek/gsw_mt7620.h
280 index 0000000..0d6ee84
282 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
284 +/* This program is free software; you can redistribute it and/or modify
285 + * it under the terms of the GNU General Public License as published by
286 + * the Free Software Foundation; version 2 of the License
288 + * This program is distributed in the hope that it will be useful,
289 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
290 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
291 + * GNU General Public License for more details.
293 + * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
294 + * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
295 + * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
298 +#ifndef _RALINK_GSW_MT7620_H__
299 +#define _RALINK_GSW_MT7620_H__
301 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
303 +#ifdef CONFIG_SOC_MT7621
304 +#define MT7620A_GSW_REG_PIAC 0x0004
306 +#define MT7620A_GSW_REG_PIAC 0x7004
309 +#define GSW_NUM_VLANS 16
310 +#define GSW_NUM_VIDS 4096
311 +#define GSW_NUM_PORTS 7
314 +#define GSW_MDIO_ACCESS BIT(31)
315 +#define GSW_MDIO_READ BIT(19)
316 +#define GSW_MDIO_WRITE BIT(18)
317 +#define GSW_MDIO_START BIT(16)
318 +#define GSW_MDIO_ADDR_SHIFT 20
319 +#define GSW_MDIO_REG_SHIFT 25
321 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
322 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
323 +#define GSW_REG_SMACCR0 0x3fE4
324 +#define GSW_REG_SMACCR1 0x3fE8
325 +#define GSW_REG_CKGCR 0x3ff0
327 +#define GSW_REG_IMR 0x7008
328 +#define GSW_REG_ISR 0x700c
329 +#define GSW_REG_GPC1 0x7014
331 +#define SYSC_REG_CHIP_REV_ID 0x0c
332 +#define SYSC_REG_CFG1 0x14
333 +#define RST_CTRL_MCM BIT(2)
334 +#define SYSC_PAD_RGMII2_MDIO 0x58
335 +#define SYSC_GPIO_MODE 0x60
337 +#define PORT_IRQ_ST_CHG 0x7f
339 +#ifdef CONFIG_SOC_MT7621
340 +#define ESW_PHY_POLLING 0x0000
342 +#define ESW_PHY_POLLING 0x7000
345 +#define PMCR_IPG BIT(18)
346 +#define PMCR_MAC_MODE BIT(16)
347 +#define PMCR_FORCE BIT(15)
348 +#define PMCR_TX_EN BIT(14)
349 +#define PMCR_RX_EN BIT(13)
350 +#define PMCR_BACKOFF BIT(9)
351 +#define PMCR_BACKPRES BIT(8)
352 +#define PMCR_RX_FC BIT(5)
353 +#define PMCR_TX_FC BIT(4)
354 +#define PMCR_SPEED(_x) (_x << 2)
355 +#define PMCR_DUPLEX BIT(1)
356 +#define PMCR_LINK BIT(0)
358 +#define PHY_AN_EN BIT(31)
359 +#define PHY_PRE_EN BIT(30)
360 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
363 + /* Global attributes. */
364 + GSW_ATTR_ENABLE_VLAN,
365 + /* Port attributes. */
366 + GSW_ATTR_PORT_UNTAG,
375 + struct device *dev;
376 + void __iomem *base;
379 + unsigned long int autopoll;
382 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
383 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
384 +int mtk_gsw_init(struct fe_priv *priv);
386 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
387 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
388 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
389 +int mt7620_has_carrier(struct fe_priv *priv);
390 +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
391 + int speed, int duplex);
393 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
394 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
396 +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
397 + u32 phy_register, u32 write_data);
398 +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);