1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
14 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
15 index 7c592ce..2f05c85 100644
16 --- a/drivers/spi/Kconfig
17 +++ b/drivers/spi/Kconfig
18 @@ -463,6 +463,12 @@ config SPI_RT2880
20 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
23 + tristate "MediaTek MT7621 SPI Controller"
26 + This selects a driver for the MediaTek MT7621 SPI Controller.
29 tristate "Samsung S3C24XX series SPI"
30 depends on ARCH_S3C24XX
31 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
32 index 3d690ef..5389710 100644
33 --- a/drivers/spi/Makefile
34 +++ b/drivers/spi/Makefile
35 @@ -49,6 +49,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
36 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
37 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
38 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
39 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
40 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
41 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
42 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
43 diff --git a/drivers/spi/spi-mt7621.c b/drivers/spi/spi-mt7621.c
45 index 0000000..dedf4a1
47 +++ b/drivers/spi/spi-mt7621.c
50 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
52 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
53 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
54 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
56 + * Some parts are based on spi-orion.c:
57 + * Author: Shadi Ammouri <shadi@marvell.com>
58 + * Copyright (C) 2007-2008 Marvell Ltd.
60 + * This program is free software; you can redistribute it and/or modify
61 + * it under the terms of the GNU General Public License version 2 as
62 + * published by the Free Software Foundation.
65 +#include <linux/init.h>
66 +#include <linux/module.h>
67 +#include <linux/clk.h>
68 +#include <linux/err.h>
69 +#include <linux/delay.h>
70 +#include <linux/io.h>
71 +#include <linux/reset.h>
72 +#include <linux/spi/spi.h>
73 +#include <linux/of_device.h>
74 +#include <linux/platform_device.h>
75 +#include <linux/swab.h>
77 +#include <ralink_regs.h>
79 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
81 +#define DRIVER_NAME "spi-mt7621"
83 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
85 +/* SPISTAT register bit field */
86 +#define SPISTAT_BUSY BIT(0)
88 +#define MT7621_SPI_TRANS 0x00
89 +#define SPITRANS_BUSY BIT(16)
91 +#define MT7621_SPI_OPCODE 0x04
92 +#define MT7621_SPI_DATA0 0x08
93 +#define MT7621_SPI_DATA4 0x18
94 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
95 +#define SPI_CTL_START BIT(8)
97 +#define MT7621_SPI_POLAR 0x38
98 +#define MT7621_SPI_MASTER 0x28
99 +#define MT7621_SPI_MOREBUF 0x2c
100 +#define MT7621_SPI_SPACE 0x3c
102 +#define MT7621_CPHA BIT(5)
103 +#define MT7621_CPOL BIT(4)
104 +#define MT7621_LSB_FIRST BIT(3)
106 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
111 + struct spi_master *master;
112 + void __iomem *base;
113 + unsigned int sys_freq;
114 + unsigned int speed;
118 + struct mt7621_spi_ops *ops;
121 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
123 + return spi_master_get_devdata(spi->master);
126 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
128 + return ioread32(rs->base + reg);
131 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
133 + iowrite32(val, rs->base + reg);
136 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
138 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
145 + master &= ~(1 << 10);
147 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
150 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
152 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
153 + int cs = spi->chip_select;
156 + mt7621_spi_reset(rs, cs);
159 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
162 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
164 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
168 + dev_dbg(&spi->dev, "speed:%u\n", speed);
170 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
171 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
179 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
180 + reg &= ~(0xfff << 16);
181 + reg |= (rate - 2) << 16;
184 + reg &= ~MT7621_LSB_FIRST;
185 + if (spi->mode & SPI_LSB_FIRST)
186 + reg |= MT7621_LSB_FIRST;
188 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
189 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
193 + reg |= MT7621_CPHA;
196 + reg |= MT7621_CPOL;
199 + reg |= MT7621_CPOL | MT7621_CPHA;
202 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
207 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
209 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
212 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
215 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
216 + if ((status & SPITRANS_BUSY) == 0) {
226 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
227 + struct spi_message *m)
229 + struct mt7621_spi *rs = spi_master_get_devdata(master);
230 + struct spi_device *spi = m->spi;
231 + unsigned int speed = spi->max_speed_hz;
232 + struct spi_transfer *t = NULL;
236 + u32 data[9] = { 0 };
239 + mt7621_spi_wait_till_ready(spi);
241 + list_for_each_entry(t, &m->transfers, transfer_list) {
242 + const u8 *buf = t->tx_buf;
250 + if (WARN_ON(len + t->len > 36)) {
255 + for (i = 0; i < t->len; i++, len++)
256 + data[len / 4] |= buf[i] << (8 * (len & 3));
259 + if (WARN_ON(rx_len > 32)) {
264 + if (mt7621_spi_prepare(spi, speed)) {
268 + data[0] = swab32(data[0]);
270 + data[0] >>= (4 - len) * 8;
272 + for (i = 0; i < len; i += 4)
273 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
275 + val = (min_t(int, len, 4) * 8) << 24;
277 + val |= (len - 4) * 8;
278 + val |= (rx_len * 8) << 12;
279 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
281 + mt7621_spi_set_cs(spi, 1);
283 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
284 + val |= SPI_CTL_START;
285 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
287 + mt7621_spi_wait_till_ready(spi);
289 + mt7621_spi_set_cs(spi, 0);
291 + for (i = 0; i < rx_len; i += 4)
292 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
294 + m->actual_length = len + rx_len;
297 + list_for_each_entry(t, &m->transfers, transfer_list) {
298 + u8 *buf = t->rx_buf;
303 + for (i = 0; i < t->len; i++, len++)
304 + buf[i] = data[len / 4] >> (8 * (len & 3));
308 + m->status = status;
309 + spi_finalize_current_message(master);
314 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
315 + struct spi_message *m)
317 + struct mt7621_spi *rs = spi_master_get_devdata(master);
318 + struct spi_device *spi = m->spi;
319 + unsigned int speed = spi->max_speed_hz;
320 + struct spi_transfer *t = NULL;
324 + u32 data[9] = { 0 };
327 + mt7621_spi_wait_till_ready(spi);
329 + list_for_each_entry(t, &m->transfers, transfer_list) {
330 + const u8 *buf = t->tx_buf;
338 + if (WARN_ON(len + t->len > 16)) {
343 + for (i = 0; i < t->len; i++, len++)
344 + data[len / 4] |= buf[i] << (8 * (len & 3));
345 + if (speed > t->speed_hz)
346 + speed = t->speed_hz;
349 + if (WARN_ON(rx_len > 16)) {
354 + if (mt7621_spi_prepare(spi, speed)) {
359 + for (i = 0; i < len; i += 4)
360 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
363 + val |= (rx_len * 8) << 12;
364 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
366 + mt7621_spi_set_cs(spi, 1);
368 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
369 + val |= SPI_CTL_START;
370 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
372 + mt7621_spi_wait_till_ready(spi);
374 + mt7621_spi_set_cs(spi, 0);
376 + for (i = 0; i < rx_len; i += 4)
377 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
379 + m->actual_length = rx_len;
382 + list_for_each_entry(t, &m->transfers, transfer_list) {
383 + u8 *buf = t->rx_buf;
388 + for (i = 0; i < t->len; i++, len++)
389 + buf[i] = data[len / 4] >> (8 * (len & 3));
393 + m->status = status;
394 + spi_finalize_current_message(master);
399 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
400 + struct spi_message *m)
402 + struct spi_device *spi = m->spi;
403 + int cs = spi->chip_select;
406 + return mt7621_spi_transfer_full_duplex(master, m);
407 + return mt7621_spi_transfer_half_duplex(master, m);
410 +static int mt7621_spi_setup(struct spi_device *spi)
412 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
414 + if ((spi->max_speed_hz == 0) ||
415 + (spi->max_speed_hz > (rs->sys_freq / 2)))
416 + spi->max_speed_hz = (rs->sys_freq / 2);
418 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
419 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
420 + spi->max_speed_hz);
427 +static const struct of_device_id mt7621_spi_match[] = {
428 + { .compatible = "ralink,mt7621-spi" },
431 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
433 +static int mt7621_spi_probe(struct platform_device *pdev)
435 + const struct of_device_id *match;
436 + struct spi_master *master;
437 + struct mt7621_spi *rs;
438 + unsigned long flags;
439 + void __iomem *base;
440 + struct resource *r;
443 + struct mt7621_spi_ops *ops;
445 + match = of_match_device(mt7621_spi_match, &pdev->dev);
448 + ops = (struct mt7621_spi_ops *)match->data;
450 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
451 + base = devm_ioremap_resource(&pdev->dev, r);
453 + return PTR_ERR(base);
455 + clk = devm_clk_get(&pdev->dev, NULL);
457 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
459 + return PTR_ERR(clk);
462 + status = clk_prepare_enable(clk);
466 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
467 + if (master == NULL) {
468 + dev_info(&pdev->dev, "master allocation failed\n");
472 + master->mode_bits = RT2880_SPI_MODE_BITS;
474 + master->setup = mt7621_spi_setup;
475 + master->transfer_one_message = mt7621_spi_transfer_one_message;
476 + master->bits_per_word_mask = SPI_BPW_MASK(8);
477 + master->dev.of_node = pdev->dev.of_node;
478 + master->num_chipselect = 2;
480 + dev_set_drvdata(&pdev->dev, master);
482 + rs = spi_master_get_devdata(master);
485 + rs->master = master;
486 + rs->sys_freq = clk_get_rate(rs->clk);
488 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
489 + spin_lock_irqsave(&rs->lock, flags);
491 + device_reset(&pdev->dev);
493 + mt7621_spi_reset(rs, 0);
495 + return spi_register_master(master);
498 +static int mt7621_spi_remove(struct platform_device *pdev)
500 + struct spi_master *master;
501 + struct mt7621_spi *rs;
503 + master = dev_get_drvdata(&pdev->dev);
504 + rs = spi_master_get_devdata(master);
506 + clk_disable(rs->clk);
507 + spi_unregister_master(master);
512 +MODULE_ALIAS("platform:" DRIVER_NAME);
514 +static struct platform_driver mt7621_spi_driver = {
516 + .name = DRIVER_NAME,
517 + .owner = THIS_MODULE,
518 + .of_match_table = mt7621_spi_match,
520 + .probe = mt7621_spi_probe,
521 + .remove = mt7621_spi_remove,
524 +module_platform_driver(mt7621_spi_driver);
526 +MODULE_DESCRIPTION("MT7621 SPI driver");
527 +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
528 +MODULE_LICENSE("GPL");