1 From 69fdd2c4f937796b934e89c33acde9d082e27bfd Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 4 Aug 2014 20:36:29 +0200
4 Subject: [PATCH 27/53] GPIO: MIPS: ralink: add gpio driver for ralink SoC
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Cc: linux-mips@linux-mips.org
11 Cc: linux-gpio@vger.kernel.org
13 arch/mips/include/asm/mach-ralink/gpio.h | 24 ++
14 drivers/gpio/Kconfig | 6 +
15 drivers/gpio/Makefile | 1 +
16 drivers/gpio/gpio-ralink.c | 355 ++++++++++++++++++++++++++++++
17 4 files changed, 386 insertions(+)
18 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
19 create mode 100644 drivers/gpio/gpio-ralink.c
21 diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
23 index 0000000..f68ee16
25 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
28 + * Ralink SoC GPIO API support
30 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
31 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License version 2 as published
35 + * by the Free Software Foundation.
39 +#ifndef __ASM_MACH_RALINK_GPIO_H
40 +#define __ASM_MACH_RALINK_GPIO_H
42 +#define ARCH_NR_GPIOS 128
43 +#include <asm-generic/gpio.h>
45 +#define gpio_get_value __gpio_get_value
46 +#define gpio_set_value __gpio_set_value
47 +#define gpio_cansleep __gpio_cansleep
48 +#define gpio_to_irq __gpio_to_irq
50 +#endif /* __ASM_MACH_RALINK_GPIO_H */
51 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
52 index 8949b3f..4a3e7df 100644
53 --- a/drivers/gpio/Kconfig
54 +++ b/drivers/gpio/Kconfig
55 @@ -404,6 +404,12 @@ config GPIO_SCH311X
56 To compile this driver as a module, choose M here: the module will
57 be called gpio-sch311x.
60 + bool "Ralink GPIO Support"
63 + Say yes here to support the Ralink SoC GPIO device
65 config GPIO_SPEAR_SPICS
66 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
68 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
69 index f79a7c4..13448d78 100644
70 --- a/drivers/gpio/Makefile
71 +++ b/drivers/gpio/Makefile
72 @@ -75,6 +75,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
73 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
74 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
75 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
76 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
77 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
78 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
79 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
80 diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
82 index 0000000..2be9b8a
84 +++ b/drivers/gpio/gpio-ralink.c
87 + * This program is free software; you can redistribute it and/or modify it
88 + * under the terms of the GNU General Public License version 2 as published
89 + * by the Free Software Foundation.
91 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
92 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
95 +#include <linux/module.h>
96 +#include <linux/io.h>
97 +#include <linux/gpio.h>
98 +#include <linux/spinlock.h>
99 +#include <linux/platform_device.h>
100 +#include <linux/of_irq.h>
101 +#include <linux/irqdomain.h>
102 +#include <linux/interrupt.h>
104 +enum ralink_gpio_reg {
118 +struct ralink_gpio_chip {
119 + struct gpio_chip chip;
120 + u8 regs[GPIO_REG_MAX];
123 + void __iomem *membase;
124 + struct irq_domain *domain;
132 +static struct irq_domain *irq_map[MAP_MAX];
133 +static int irq_map_count;
134 +static atomic_t irq_refcount = ATOMIC_INIT(0);
136 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
138 + struct ralink_gpio_chip *rg;
140 + rg = container_of(chip, struct ralink_gpio_chip, chip);
145 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
147 + iowrite32(val, rg->membase + rg->regs[reg]);
150 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
152 + return ioread32(rg->membase + rg->regs[reg]);
155 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
157 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
159 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
162 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
164 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
166 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
169 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
171 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
172 + unsigned long flags;
175 + spin_lock_irqsave(&rg->lock, flags);
176 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
178 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
179 + spin_unlock_irqrestore(&rg->lock, flags);
184 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
185 + unsigned offset, int value)
187 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
188 + unsigned long flags;
191 + spin_lock_irqsave(&rg->lock, flags);
192 + ralink_gpio_set(chip, offset, value);
193 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
195 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
196 + spin_unlock_irqrestore(&rg->lock, flags);
201 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
203 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
208 + return irq_create_mapping(rg->domain, pin);
211 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
215 + for (i = 0; i < irq_map_count; i++) {
216 + struct irq_domain *domain = irq_map[i];
217 + struct ralink_gpio_chip *rg;
218 + unsigned long pending;
221 + rg = (struct ralink_gpio_chip *) domain->host_data;
222 + pending = rt_gpio_r32(rg, GPIO_REG_INT);
224 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
225 + u32 map = irq_find_mapping(domain, bit);
226 + generic_handle_irq(map);
227 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
232 +static void ralink_gpio_irq_unmask(struct irq_data *d)
234 + struct ralink_gpio_chip *rg;
235 + unsigned long flags;
238 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
239 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
240 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
242 + spin_lock_irqsave(&rg->lock, flags);
243 + rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
244 + rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
245 + spin_unlock_irqrestore(&rg->lock, flags);
248 +static void ralink_gpio_irq_mask(struct irq_data *d)
250 + struct ralink_gpio_chip *rg;
251 + unsigned long flags;
254 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
255 + rise = rt_gpio_r32(rg, GPIO_REG_RENA);
256 + fall = rt_gpio_r32(rg, GPIO_REG_FENA);
258 + spin_lock_irqsave(&rg->lock, flags);
259 + rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
260 + rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
261 + spin_unlock_irqrestore(&rg->lock, flags);
264 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
266 + struct ralink_gpio_chip *rg;
267 + u32 mask = BIT(d->hwirq);
269 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
271 + if (type == IRQ_TYPE_PROBE) {
272 + if ((rg->rising | rg->falling) & mask)
275 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
278 + if (type & IRQ_TYPE_EDGE_RISING)
279 + rg->rising |= mask;
281 + rg->rising &= ~mask;
283 + if (type & IRQ_TYPE_EDGE_FALLING)
284 + rg->falling |= mask;
286 + rg->falling &= ~mask;
291 +static struct irq_chip ralink_gpio_irq_chip = {
293 + .irq_unmask = ralink_gpio_irq_unmask,
294 + .irq_mask = ralink_gpio_irq_mask,
295 + .irq_mask_ack = ralink_gpio_irq_mask,
296 + .irq_set_type = ralink_gpio_irq_type,
299 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
301 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
302 + irq_set_handler_data(irq, d);
307 +static const struct irq_domain_ops irq_domain_ops = {
308 + .xlate = irq_domain_xlate_onecell,
312 +static void ralink_gpio_irq_init(struct device_node *np,
313 + struct ralink_gpio_chip *rg)
315 + if (irq_map_count >= MAP_MAX)
318 + rg->irq = irq_of_parse_and_map(np, 0);
322 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
323 + &irq_domain_ops, rg);
325 + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
329 + irq_map[irq_map_count++] = rg->domain;
331 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
332 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
334 + if (!atomic_read(&irq_refcount))
335 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
336 + atomic_inc(&irq_refcount);
338 + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
341 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
343 + int gpio = chip->base + offset;
345 + return pinctrl_request_gpio(gpio);
348 +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
350 + int gpio = chip->base + offset;
352 + pinctrl_free_gpio(gpio);
355 +static int ralink_gpio_probe(struct platform_device *pdev)
357 + struct device_node *np = pdev->dev.of_node;
358 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
359 + struct ralink_gpio_chip *rg;
360 + const __be32 *ngpio, *gpiobase;
363 + dev_err(&pdev->dev, "failed to find resource\n");
367 + rg = devm_kzalloc(&pdev->dev,
368 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
372 + rg->membase = devm_ioremap_resource(&pdev->dev, res);
373 + if (!rg->membase) {
374 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
378 + if (of_property_read_u8_array(np, "ralink,register-map",
379 + rg->regs, GPIO_REG_MAX)) {
380 + dev_err(&pdev->dev, "failed to read register definition\n");
384 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
386 + dev_err(&pdev->dev, "failed to read number of pins\n");
390 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
392 + rg->chip.base = be32_to_cpu(*gpiobase);
394 + rg->chip.base = -1;
396 + spin_lock_init(&rg->lock);
398 + rg->chip.dev = &pdev->dev;
399 + rg->chip.label = dev_name(&pdev->dev);
400 + rg->chip.of_node = np;
401 + rg->chip.ngpio = be32_to_cpu(*ngpio);
402 + rg->chip.direction_input = ralink_gpio_direction_input;
403 + rg->chip.direction_output = ralink_gpio_direction_output;
404 + rg->chip.get = ralink_gpio_get;
405 + rg->chip.set = ralink_gpio_set;
406 + rg->chip.request = ralink_gpio_request;
407 + rg->chip.to_irq = ralink_gpio_to_irq;
408 + rg->chip.free = ralink_gpio_free;
410 + /* set polarity to low for all lines */
411 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
413 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
415 + ralink_gpio_irq_init(np, rg);
417 + return gpiochip_add(&rg->chip);
420 +static const struct of_device_id ralink_gpio_match[] = {
421 + { .compatible = "ralink,rt2880-gpio" },
424 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
426 +static struct platform_driver ralink_gpio_driver = {
427 + .probe = ralink_gpio_probe,
429 + .name = "rt2880_gpio",
430 + .owner = THIS_MODULE,
431 + .of_match_table = ralink_gpio_match,
435 +static int __init ralink_gpio_init(void)
437 + return platform_driver_register(&ralink_gpio_driver);
440 +subsys_initcall(ralink_gpio_init);