1 From d410e5478c622c01fcf31427533df5f433df9146 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 28 Jul 2013 19:45:30 +0200
4 Subject: [PATCH 26/53] DT: Add documentation for gpio-ralink
6 Describe gpio-ralink binding.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 Cc: linux-mips@linux-mips.org
10 Cc: devicetree@vger.kernel.org
11 Cc: linux-gpio@vger.kernel.org
13 .../devicetree/bindings/gpio/gpio-ralink.txt | 40 ++++++++++++++++++++
14 1 file changed, 40 insertions(+)
15 create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
18 +++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
20 +Ralink SoC GPIO controller bindings
24 + - "ralink,rt2880-gpio" for Ralink controllers
25 +- #gpio-cells : Should be two.
26 + - first cell is the pin number
27 + - second cell is used to specify optional parameters (unused)
28 +- gpio-controller : Marks the device node as a GPIO controller
29 +- reg : Physical base address and length of the controller's registers
30 +- interrupt-parent: phandle to the INTC device node
31 +- interrupts : Specify the INTC interrupt number
32 +- ralink,num-gpios : Specify the number of GPIOs
33 +- ralink,register-map : The register layout depends on the GPIO bank and actual
34 + SoC type. Register offsets need to be in this order.
35 + [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
38 +- ralink,gpio-base : Specify the GPIO chips base number
43 + compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
50 + interrupt-parent = <&intc>;
53 + ralink,gpio-base = <0>;
54 + ralink,num-gpios = <24>;
55 + ralink,register-map = [ 00 04 08 0c