1 From 4d805af8246efdc330d6af9a8bd10ce892327598 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 24 Jan 2014 17:01:17 +0100
4 Subject: [PATCH 03/53] MIPS: ralink: cleanup early_printk
6 Add support for the new MT7621/8 SoC and kill ifdefs.
7 Cleanup some whitespace error while we are at it.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/ralink/early_printk.c | 25 +++++++++++++++++++++++++
12 1 file changed, 25 insertions(+)
14 diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
15 index 255d695..c04ee53 100644
16 --- a/arch/mips/ralink/early_printk.c
17 +++ b/arch/mips/ralink/early_printk.c
19 #define MT7628_CHIP_NAME1 0x20203832
21 #define UART_REG_TX 0x04
22 +#define UART_REG_LCR 0x0c
23 #define UART_REG_LSR 0x14
24 #define UART_REG_LSR_RT2880 0x1c
26 static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
27 static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
28 +static int init_complete;
30 static inline void uart_w32(u32 val, unsigned reg)
32 @@ -47,8 +49,31 @@ static inline int soc_is_mt7628(void)
33 (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
36 +static inline void find_uart_base(void)
40 + if (!soc_is_mt7628())
43 + for (i = 0; i < 3; i++) {
44 + u32 reg = uart_r32(UART_REG_LCR + (0x100 * i));
49 + uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + (0x100 * i));
54 void prom_putchar(unsigned char ch)
56 + if (!init_complete) {
61 if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
62 uart_w32(ch, UART_TX);
63 while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)