1 From dae867771332e7541783ebb6bacf33356ad449b3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 31 Jan 2013 13:44:10 +0100
4 Subject: [PATCH 12/79] Document: devicetree: add OF documents for MIPS
7 Signed-off-by: John Crispin <blogic@openwrt.org>
8 Acked-by: David Daney <david.daney@cavium.com>
9 Patchwork: http://patchwork.linux-mips.org/patch/4901/
11 Documentation/devicetree/bindings/mips/cpu_irq.txt | 47 ++++++++++++++++++++
12 1 file changed, 47 insertions(+)
13 create mode 100644 Documentation/devicetree/bindings/mips/cpu_irq.txt
15 diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt
17 index 0000000..13aa4b6
19 +++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt
21 +MIPS CPU interrupt controller
23 +On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU
24 +IRQs from a devicetree file and create a irq_domain for IRQ controller.
26 +With the irq_domain in place we can describe how the 8 IRQs are wired to the
27 +platforms internal interrupt controller cascade.
29 +Below is an example of a platform describing the cascade inside the devicetree
30 +and the code used to load it inside arch_init_irq().
33 +- compatible : Should be "mti,cpu-interrupt-controller"
36 + cpu-irq: cpu-irq@0 {
37 + #address-cells = <0>;
39 + interrupt-controller;
40 + #interrupt-cells = <1>;
42 + compatible = "mti,cpu-interrupt-controller";
46 + compatible = "ralink,rt2880-intc";
47 + reg = <0x200 0x100>;
49 + interrupt-controller;
50 + #interrupt-cells = <1>;
52 + interrupt-parent = <&cpu-irq>;
57 +Example platform irq.c:
58 +static struct of_device_id __initdata of_irq_ids[] = {
59 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
60 + { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
64 +void __init arch_init_irq(void)
66 + of_irq_init(of_irq_ids);