1 --- a/drivers/spi/Kconfig
2 +++ b/drivers/spi/Kconfig
5 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
8 + tristate "MediaTek MT7621 SPI Controller"
11 + This selects a driver for the MediaTek MT7621 SPI Controller.
14 tristate "Samsung S3C24XX series SPI"
15 depends on ARCH_S3C24XX
16 --- a/drivers/spi/Makefile
17 +++ b/drivers/spi/Makefile
19 obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mpc512x-psc.o
20 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
21 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
22 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
23 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
24 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
25 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
27 +++ b/drivers/spi/spi-mt7621.c
30 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
32 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
33 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
34 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@openwrt.org>
36 + * Some parts are based on spi-orion.c:
37 + * Author: Shadi Ammouri <shadi@marvell.com>
38 + * Copyright (C) 2007-2008 Marvell Ltd.
40 + * This program is free software; you can redistribute it and/or modify
41 + * it under the terms of the GNU General Public License version 2 as
42 + * published by the Free Software Foundation.
45 +#include <linux/init.h>
46 +#include <linux/module.h>
47 +#include <linux/clk.h>
48 +#include <linux/err.h>
49 +#include <linux/delay.h>
50 +#include <linux/io.h>
51 +#include <linux/reset.h>
52 +#include <linux/spi/spi.h>
53 +#include <linux/of_device.h>
54 +#include <linux/platform_device.h>
55 +#include <linux/swab.h>
57 +#include <ralink_regs.h>
59 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
61 +#define DRIVER_NAME "spi-mt7621"
63 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
65 +/* SPISTAT register bit field */
66 +#define SPISTAT_BUSY BIT(0)
68 +#define MT7621_SPI_TRANS 0x00
69 +#define SPITRANS_BUSY BIT(16)
71 +#define MT7621_SPI_OPCODE 0x04
72 +#define MT7621_SPI_DATA0 0x08
73 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
74 +#define SPI_CTL_START BIT(8)
76 +#define MT7621_SPI_POLAR 0x38
77 +#define MT7621_SPI_MASTER 0x28
78 +#define MT7621_SPI_MOREBUF 0x2c
79 +#define MT7621_SPI_SPACE 0x3c
81 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
86 + struct spi_master *master;
88 + unsigned int sys_freq;
93 + struct mt7621_spi_ops *ops;
96 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
98 + return spi_master_get_devdata(spi->master);
101 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
103 + return ioread32(rs->base + reg);
106 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
108 + iowrite32(val, rs->base + reg);
111 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
113 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
114 + int cs = spi->chip_select;
119 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
122 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
124 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
127 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
130 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
131 + if ((status & SPITRANS_BUSY) == 0) {
141 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
142 + struct spi_message *m)
144 + struct mt7621_spi *rs = spi_master_get_devdata(master);
145 + struct spi_device *spi = m->spi;
146 + struct spi_transfer *t = NULL;
150 + u32 data[9] = { 0 };
153 + mt7621_spi_wait_till_ready(spi);
155 + list_for_each_entry(t, &m->transfers, transfer_list) {
156 + const u8 *buf = t->tx_buf;
164 + if (WARN_ON(len + t->len > 36)) {
169 + for (i = 0; i < t->len; i++, len++)
170 + data[len / 4] |= buf[i] << (8 * (len & 3));
173 + if (WARN_ON(rx_len > 32)) {
178 + data[0] = swab32(data[0]);
180 + data[0] >>= (4 - len) * 8;
182 + for (i = 0; i < len; i += 4)
183 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
185 + val = (min_t(int, len, 4) * 8) << 24;
187 + val |= (len - 4) * 8;
188 + val |= (rx_len * 8) << 12;
189 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
191 + mt7621_spi_set_cs(spi, 1);
193 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
194 + val |= SPI_CTL_START;
195 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
197 + mt7621_spi_wait_till_ready(spi);
199 + mt7621_spi_set_cs(spi, 0);
201 + for (i = 0; i < rx_len; i += 4)
202 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
204 + m->actual_length = len + rx_len;
207 + list_for_each_entry(t, &m->transfers, transfer_list) {
208 + u8 *buf = t->rx_buf;
213 + for (i = 0; i < t->len; i++, len++)
214 + buf[i] = data[len / 4] >> (8 * (len & 3));
218 + m->status = status;
219 + spi_finalize_current_message(master);
224 +static int mt7621_spi_setup(struct spi_device *spi)
229 +static void mt7621_spi_reset(struct mt7621_spi *rs)
231 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
233 + master &= ~(0xfff << 16);
234 + master |= 13 << 16;
238 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
241 +static const struct of_device_id mt7621_spi_match[] = {
242 + { .compatible = "ralink,mt7621-spi" },
245 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
247 +static int mt7621_spi_probe(struct platform_device *pdev)
249 + const struct of_device_id *match;
250 + struct spi_master *master;
251 + struct mt7621_spi *rs;
252 + unsigned long flags;
253 + void __iomem *base;
254 + struct resource *r;
257 + struct mt7621_spi_ops *ops;
259 + match = of_match_device(mt7621_spi_match, &pdev->dev);
262 + ops = (struct mt7621_spi_ops *)match->data;
264 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 + base = devm_ioremap_resource(&pdev->dev, r);
267 + return PTR_ERR(base);
269 + clk = devm_clk_get(&pdev->dev, NULL);
271 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
273 + return PTR_ERR(clk);
276 + status = clk_prepare_enable(clk);
280 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
281 + if (master == NULL) {
282 + dev_dbg(&pdev->dev, "master allocation failed\n");
286 + master->mode_bits = RT2880_SPI_MODE_BITS;
288 + master->setup = mt7621_spi_setup;
289 + master->transfer_one_message = mt7621_spi_transfer_one_message;
290 + master->bits_per_word_mask = SPI_BPW_MASK(8);
291 + master->dev.of_node = pdev->dev.of_node;
292 + master->num_chipselect = 2;
294 + dev_set_drvdata(&pdev->dev, master);
296 + rs = spi_master_get_devdata(master);
299 + rs->master = master;
300 + rs->sys_freq = clk_get_rate(rs->clk);
302 + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
303 + spin_lock_irqsave(&rs->lock, flags);
305 + device_reset(&pdev->dev);
307 + mt7621_spi_reset(rs);
309 + return spi_register_master(master);
312 +static int mt7621_spi_remove(struct platform_device *pdev)
314 + struct spi_master *master;
315 + struct mt7621_spi *rs;
317 + master = dev_get_drvdata(&pdev->dev);
318 + rs = spi_master_get_devdata(master);
320 + clk_disable(rs->clk);
321 + spi_unregister_master(master);
326 +MODULE_ALIAS("platform:" DRIVER_NAME);
328 +static struct platform_driver mt7621_spi_driver = {
330 + .name = DRIVER_NAME,
331 + .owner = THIS_MODULE,
332 + .of_match_table = mt7621_spi_match,
334 + .probe = mt7621_spi_probe,
335 + .remove = mt7621_spi_remove,
338 +module_platform_driver(mt7621_spi_driver);
340 +MODULE_DESCRIPTION("MT7621 SPI driver");
341 +MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
342 +MODULE_LICENSE("GPL");