target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:15:12 +0100
   4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/spi/Kconfig      |    6 +
  12  drivers/spi/Makefile     |    1 +
  13  drivers/spi/spi-rt2880.c |  432 ++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 439 insertions(+)
  15  create mode 100644 drivers/spi/spi-rt2880.c
  16
  17 --- a/drivers/spi/Kconfig
  18 +++ b/drivers/spi/Kconfig
  19 @@ -433,6 +433,12 @@ config SPI_QUP
  20           This driver can also be built as a module.  If so, the module
  21           will be called spi_qup.
  22
  23 +config SPI_RT2880
  24 +       tristate "Ralink RT288x SPI Controller"
  25 +       depends on RALINK
  26 +       help
  27 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  28 +
  29  config SPI_S3C24XX
  30         tristate "Samsung S3C24XX series SPI"
  31         depends on ARCH_S3C24XX
  32 --- a/drivers/spi/Makefile
  33 +++ b/drivers/spi/Makefile
  34 @@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI)          += spi-pxa
  35  obj-$(CONFIG_SPI_QUP)                  += spi-qup.o
  36  obj-$(CONFIG_SPI_ROCKCHIP)             += spi-rockchip.o
  37  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  38 +obj-$(CONFIG_SPI_RT2880)               += spi-rt2880.o
  39  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  40  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  41  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  42 --- /dev/null
  43 +++ b/drivers/spi/spi-rt2880.c
  44 @@ -0,0 +1,533 @@
  45 +/*
  46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  47 + *
  48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  50 + *
  51 + * Some parts are based on spi-orion.c:
  52 + *   Author: Shadi Ammouri <shadi@marvell.com>
  53 + *   Copyright (C) 2007-2008 Marvell Ltd.
  54 + *
  55 + * This program is free software; you can redistribute it and/or modify
  56 + * it under the terms of the GNU General Public License version 2 as
  57 + * published by the Free Software Foundation.
  58 + */
  59 +
  60 +#include <linux/init.h>
  61 +#include <linux/module.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/err.h>
  64 +#include <linux/delay.h>
  65 +#include <linux/io.h>
  66 +#include <linux/reset.h>
  67 +#include <linux/spi/spi.h>
  68 +#include <linux/platform_device.h>
  69 +
  70 +#define DRIVER_NAME                    "spi-rt2880"
  71 +/* only one slave is supported*/
  72 +#define RALINK_NUM_CHIPSELECTS         1
  73 +
  74 +#define RAMIPS_SPI_STAT                        0x00
  75 +#define RAMIPS_SPI_CFG                 0x10
  76 +#define RAMIPS_SPI_CTL                 0x14
  77 +#define RAMIPS_SPI_DATA                        0x20
  78 +#define RAMIPS_SPI_ADDR                        0x24
  79 +#define RAMIPS_SPI_BS                  0x28
  80 +#define RAMIPS_SPI_USER                        0x2C
  81 +#define RAMIPS_SPI_TXFIFO              0x30
  82 +#define RAMIPS_SPI_RXFIFO              0x34
  83 +#define RAMIPS_SPI_FIFO_STAT           0x38
  84 +#define RAMIPS_SPI_MODE                        0x3C
  85 +#define RAMIPS_SPI_DEV_OFFSET          0x40
  86 +#define RAMIPS_SPI_DMA                 0x80
  87 +#define RAMIPS_SPI_DMASTAT             0x84
  88 +#define RAMIPS_SPI_ARBITER             0xF0
  89 +
  90 +/* SPISTAT register bit field */
  91 +#define SPISTAT_BUSY                   BIT(0)
  92 +
  93 +/* SPICFG register bit field */
  94 +#define SPICFG_ADDRMODE                        BIT(12)
  95 +#define SPICFG_RXENVDIS                        BIT(11)
  96 +#define SPICFG_RXCAP                   BIT(10)
  97 +#define SPICFG_SPIENMODE               BIT(9)
  98 +#define SPICFG_MSBFIRST                        BIT(8)
  99 +#define SPICFG_SPICLKPOL               BIT(6)
 100 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
 101 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
 102 +#define SPICFG_HIZSPI                  BIT(3)
 103 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
 104 +#define SPICFG_SPICLK_DIV2             0
 105 +#define SPICFG_SPICLK_DIV4             1
 106 +#define SPICFG_SPICLK_DIV8             2
 107 +#define SPICFG_SPICLK_DIV16            3
 108 +#define SPICFG_SPICLK_DIV32            4
 109 +#define SPICFG_SPICLK_DIV64            5
 110 +#define SPICFG_SPICLK_DIV128           6
 111 +#define SPICFG_SPICLK_DISABLE          7
 112 +
 113 +/* SPICTL register bit field */
 114 +#define SPICTL_START                   BIT(4)
 115 +#define SPICTL_HIZSDO                  BIT(3)
 116 +#define SPICTL_STARTWR                 BIT(2)
 117 +#define SPICTL_STARTRD                 BIT(1)
 118 +#define SPICTL_SPIENA                  BIT(0)
 119 +
 120 +/* SPIUSER register bit field */
 121 +#define SPIUSER_USERMODE               BIT(21)
 122 +#define SPIUSER_INSTR_PHASE            BIT(20)
 123 +#define SPIUSER_ADDR_PHASE_MASK                0x7
 124 +#define SPIUSER_ADDR_PHASE_OFFSET      17
 125 +#define SPIUSER_MODE_PHASE             BIT(16)
 126 +#define SPIUSER_DUMMY_PHASE_MASK       0x3
 127 +#define SPIUSER_DUMMY_PHASE_OFFSET     14
 128 +#define SPIUSER_DATA_PHASE_MASK                0x3
 129 +#define SPIUSER_DATA_PHASE_OFFSET      12
 130 +#define SPIUSER_DATA_READ              (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
 131 +#define SPIUSER_DATA_WRITE             (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
 132 +#define SPIUSER_ADDR_TYPE_OFFSET       9
 133 +#define SPIUSER_MODE_TYPE_OFFSET       6
 134 +#define SPIUSER_DUMMY_TYPE_OFFSET      3
 135 +#define SPIUSER_DATA_TYPE_OFFSET       0
 136 +#define SPIUSER_TRANSFER_MASK          0x7
 137 +#define SPIUSER_TRANSFER_SINGLE                BIT(0)
 138 +#define SPIUSER_TRANSFER_DUAL          BIT(1)
 139 +#define SPIUSER_TRANSFER_QUAD          BIT(2)
 140 +
 141 +#define SPIUSER_TRANSFER_TYPE(type) ( \
 142 +       (type << SPIUSER_ADDR_TYPE_OFFSET) | \
 143 +       (type << SPIUSER_MODE_TYPE_OFFSET) | \
 144 +       (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
 145 +       (type << SPIUSER_DATA_TYPE_OFFSET) \
 146 +)
 147 +
 148 +/* SPIFIFOSTAT register bit field */
 149 +#define SPIFIFOSTAT_TXEMPTY            BIT(19)
 150 +#define SPIFIFOSTAT_RXEMPTY            BIT(18)
 151 +#define SPIFIFOSTAT_TXFULL             BIT(17)
 152 +#define SPIFIFOSTAT_RXFULL             BIT(16)
 153 +#define SPIFIFOSTAT_FIFO_MASK          0xff
 154 +#define SPIFIFOSTAT_TX_OFFSET          8
 155 +#define SPIFIFOSTAT_RX_OFFSET          0
 156 +
 157 +#define SPI_FIFO_DEPTH                 16
 158 +
 159 +/* SPIMODE register bit field */
 160 +#define SPIMODE_MODE_OFFSET            24
 161 +#define SPIMODE_DUMMY_OFFSET           0
 162 +
 163 +/* SPIARB register bit field */
 164 +#define SPICTL_ARB_EN                  BIT(31)
 165 +#define SPICTL_CSCTL1                  BIT(16)
 166 +#define SPI1_POR                       BIT(1)
 167 +#define SPI0_POR                       BIT(0)
 168 +
 169 +#define RT2880_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
 170 +               SPI_CS_HIGH)
 171 +
 172 +struct rt2880_spi {
 173 +       struct spi_master       *master;
 174 +       void __iomem            *base;
 175 +       u32                     speed;
 176 +       u16                     wait_loops;
 177 +       u16                     mode;
 178 +       struct clk              *clk;
 179 +};
 180 +
 181 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 182 +{
 183 +       return spi_master_get_devdata(spi->master);
 184 +}
 185 +
 186 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 187 +{
 188 +       return ioread32(rs->base + reg);
 189 +}
 190 +
 191 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
 192 +               const u32 val)
 193 +{
 194 +       iowrite32(val, rs->base + reg);
 195 +}
 196 +
 197 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 198 +{
 199 +       void __iomem *addr = rs->base + reg;
 200 +
 201 +       iowrite32((ioread32(addr) | mask), addr);
 202 +}
 203 +
 204 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 205 +{
 206 +       void __iomem *addr = rs->base + reg;
 207 +
 208 +       iowrite32((ioread32(addr) & ~mask), addr);
 209 +}
 210 +
 211 +static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
 212 +{
 213 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 214 +       u32 rate;
 215 +       u32 prescale;
 216 +
 217 +       /*
 218 +        * the supported rates are: 2, 4, 8, ... 128
 219 +        * round up as we look for equal or less speed
 220 +        */
 221 +       rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
 222 +       rate = roundup_pow_of_two(rate);
 223 +
 224 +       /* Convert the rate to SPI clock divisor value. */
 225 +       prescale = ilog2(rate / 2);
 226 +
 227 +       /* some tolerance. double and add 100 */
 228 +       rs->wait_loops = (8 * HZ * loops_per_jiffy) /
 229 +               (clk_get_rate(rs->clk) / rate);
 230 +       rs->wait_loops = (rs->wait_loops << 1) + 100;
 231 +       rs->speed = speed;
 232 +
 233 +       dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
 234 +                       clk_get_rate(rs->clk) / rate, speed, rate, prescale,
 235 +                       rs->wait_loops);
 236 +
 237 +       return prescale;
 238 +}
 239 +
 240 +static u32 get_arbiter_offset(struct spi_master *master)
 241 +{
 242 +       u32 offset;
 243 +
 244 +       offset = RAMIPS_SPI_ARBITER;
 245 +       if (master->bus_num == 1)
 246 +               offset -= RAMIPS_SPI_DEV_OFFSET;
 247 +
 248 +       return offset;
 249 +}
 250 +
 251 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
 252 +{
 253 +       if (enable)
 254 +               rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 255 +       else
 256 +               rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 257 +}
 258 +
 259 +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
 260 +{
 261 +       int loop = rs->wait_loops * len;
 262 +
 263 +       while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
 264 +               cpu_relax();
 265 +
 266 +       if (loop)
 267 +               return 0;
 268 +
 269 +       return -ETIMEDOUT;
 270 +}
 271 +
 272 +static unsigned int
 273 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 274 +{
 275 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 276 +       unsigned count = 0;
 277 +       u8 *rx = xfer->rx_buf;
 278 +       const u8 *tx = xfer->tx_buf;
 279 +       int err;
 280 +
 281 +       dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
 282 +                 (tx != NULL) ? "tx" : "  ",
 283 +                 (rx != NULL) ? "rx" : "  ");
 284 +
 285 +       if (tx) {
 286 +               for (count = 0; count < xfer->len; count++) {
 287 +                       rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 288 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 289 +                       err = rt2880_spi_wait_ready(rs, 1);
 290 +                       if (err) {
 291 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 292 +                               goto out;
 293 +                       }
 294 +               }
 295 +       }
 296 +
 297 +       if (rx) {
 298 +               for (count = 0; count < xfer->len; count++) {
 299 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 300 +                       err = rt2880_spi_wait_ready(rs, 1);
 301 +                       if (err) {
 302 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 303 +                               goto out;
 304 +                       }
 305 +                       rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 306 +               }
 307 +       }
 308 +
 309 +out:
 310 +       return count;
 311 +}
 312 +
 313 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
 314 +                                          struct spi_message *m)
 315 +{
 316 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 317 +       struct spi_device *spi = m->spi;
 318 +       struct spi_transfer *t = NULL;
 319 +       int status = 0;
 320 +       int cs_active = 0;
 321 +
 322 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 323 +               if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 324 +                       dev_err(&spi->dev,
 325 +                               "message rejected: invalid transfer data buffers\n");
 326 +                       status = -EIO;
 327 +                       goto msg_done;
 328 +               }
 329 +
 330 +               if (!cs_active) {
 331 +                       rt2880_spi_set_cs(rs, 1);
 332 +                       cs_active = 1;
 333 +               }
 334 +
 335 +               if (t->len)
 336 +                       m->actual_length += rt2880_spi_write_read(spi, t);
 337 +
 338 +               if (t->delay_usecs)
 339 +                       udelay(t->delay_usecs);
 340 +
 341 +               if (t->cs_change) {
 342 +                       rt2880_spi_set_cs(rs, 0);
 343 +                       cs_active = 0;
 344 +               }
 345 +       }
 346 +
 347 +msg_done:
 348 +       if (cs_active)
 349 +               rt2880_spi_set_cs(rs, 0);
 350 +
 351 +       m->status = status;
 352 +       spi_finalize_current_message(master);
 353 +
 354 +       return 0;
 355 +}
 356 +
 357 +static int rt2880_spi_setup(struct spi_device *spi)
 358 +{
 359 +       struct spi_master *master = spi->master;
 360 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 361 +       u32 reg, old_reg, arbit_off;
 362 +
 363 +       if ((spi->max_speed_hz > master->max_speed_hz) ||
 364 +                       (spi->max_speed_hz < master->min_speed_hz)) {
 365 +               dev_err(&spi->dev, "invalide requested speed %d Hz\n",
 366 +                               spi->max_speed_hz);
 367 +               return -EINVAL;
 368 +       }
 369 +
 370 +       if (!(master->bits_per_word_mask &
 371 +                               BIT(spi->bits_per_word - 1))) {
 372 +               dev_err(&spi->dev, "invalide bits_per_word %d\n",
 373 +                               spi->bits_per_word);
 374 +               return -EINVAL;
 375 +       }
 376 +
 377 +       /* the hardware seems can't work on mode0 force it to mode3 */
 378 +       if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
 379 +               dev_warn(&spi->dev, "force spi mode3\n");
 380 +               spi->mode |= SPI_MODE_3;
 381 +       }
 382 +
 383 +       /* chip polarity */
 384 +       arbit_off = get_arbiter_offset(master);
 385 +       reg = old_reg = rt2880_spi_read(rs, arbit_off);
 386 +       if (spi->mode & SPI_CS_HIGH) {
 387 +               switch (master->bus_num) {
 388 +               case 1:
 389 +                       reg |= SPI1_POR;
 390 +                       break;
 391 +               default:
 392 +                       reg |= SPI0_POR;
 393 +                       break;
 394 +               }
 395 +       } else {
 396 +               switch (master->bus_num) {
 397 +               case 1:
 398 +                       reg &= ~SPI1_POR;
 399 +                       break;
 400 +               default:
 401 +                       reg &= ~SPI0_POR;
 402 +                       break;
 403 +               }
 404 +       }
 405 +
 406 +       /* enable spi1 */
 407 +       if (master->bus_num == 1)
 408 +               reg |= SPICTL_ARB_EN;
 409 +
 410 +       if (reg != old_reg)
 411 +               rt2880_spi_write(rs, arbit_off, reg);
 412 +
 413 +       return 0;
 414 +}
 415 +
 416 +static int rt2880_spi_prepare_message(struct spi_master *master,
 417 +               struct spi_message *msg)
 418 +{
 419 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 420 +       struct spi_device *spi = msg->spi;
 421 +       u32 reg;
 422 +
 423 +       if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
 424 +               return 0;
 425 +
 426 +#if 0
 427 +       /* set spido to tri-state */
 428 +       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
 429 +#endif
 430 +
 431 +       reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 432 +
 433 +       reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
 434 +                       SPICFG_RXCLKEDGE_FALLING |
 435 +                       SPICFG_TXCLKEDGE_FALLING |
 436 +                       SPICFG_SPICLK_PRESCALE_MASK);
 437 +
 438 +       /* MSB */
 439 +       if (!(spi->mode & SPI_LSB_FIRST))
 440 +               reg |= SPICFG_MSBFIRST;
 441 +
 442 +       /* spi mode */
 443 +       switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 444 +       case SPI_MODE_0:
 445 +               reg |= SPICFG_TXCLKEDGE_FALLING;
 446 +               break;
 447 +       case SPI_MODE_1:
 448 +               reg |= SPICFG_RXCLKEDGE_FALLING;
 449 +               break;
 450 +       case SPI_MODE_2:
 451 +               reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
 452 +               break;
 453 +       case SPI_MODE_3:
 454 +               reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
 455 +               break;
 456 +       }
 457 +       rs->mode = spi->mode;
 458 +
 459 +#if 0
 460 +       /* set spiclk and spiena to tri-state */
 461 +       reg |= SPICFG_HIZSPI;
 462 +#endif
 463 +
 464 +       /* clock divide */
 465 +       reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
 466 +
 467 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 468 +
 469 +       return 0;
 470 +}
 471 +
 472 +static int rt2880_spi_probe(struct platform_device *pdev)
 473 +{
 474 +       struct spi_master *master;
 475 +       struct rt2880_spi *rs;
 476 +       void __iomem *base;
 477 +       struct resource *r;
 478 +       struct clk *clk;
 479 +       int ret;
 480 +
 481 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 482 +       base = devm_ioremap_resource(&pdev->dev, r);
 483 +       if (IS_ERR(base))
 484 +               return PTR_ERR(base);
 485 +
 486 +       clk = devm_clk_get(&pdev->dev, NULL);
 487 +       if (IS_ERR(clk)) {
 488 +               dev_err(&pdev->dev, "unable to get SYS clock\n");
 489 +               return PTR_ERR(clk);
 490 +       }
 491 +
 492 +       ret = clk_prepare_enable(clk);
 493 +       if (ret)
 494 +               goto err_clk;
 495 +
 496 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 497 +       if (master == NULL) {
 498 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 499 +               ret = -ENOMEM;
 500 +               goto err_clk;
 501 +       }
 502 +
 503 +       master->dev.of_node = pdev->dev.of_node;
 504 +       master->mode_bits = RT2880_SPI_MODE_BITS;
 505 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 506 +       master->min_speed_hz = clk_get_rate(clk) / 128;
 507 +       master->max_speed_hz = clk_get_rate(clk) / 2;
 508 +       master->flags = SPI_MASTER_HALF_DUPLEX;
 509 +       master->setup = rt2880_spi_setup;
 510 +       master->prepare_message = rt2880_spi_prepare_message;
 511 +       master->transfer_one_message = rt2880_spi_transfer_one_message;
 512 +       master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 513 +
 514 +       dev_set_drvdata(&pdev->dev, master);
 515 +
 516 +       rs = spi_master_get_devdata(master);
 517 +       rs->master = master;
 518 +       rs->base = base;
 519 +       rs->clk = clk;
 520 +
 521 +       device_reset(&pdev->dev);
 522 +
 523 +
 524 +       ret = devm_spi_register_master(&pdev->dev, master);
 525 +       if (ret < 0) {
 526 +               dev_err(&pdev->dev, "devm_spi_register_master error.\n");
 527 +               goto err_master;
 528 +       }
 529 +
 530 +       return ret;
 531 +
 532 +err_master:
 533 +       spi_master_put(master);
 534 +       kfree(master);
 535 +err_clk:
 536 +       clk_disable_unprepare(clk);
 537 +
 538 +       return ret;
 539 +}
 540 +
 541 +static int rt2880_spi_remove(struct platform_device *pdev)
 542 +{
 543 +       struct spi_master *master;
 544 +       struct rt2880_spi *rs;
 545 +
 546 +       master = dev_get_drvdata(&pdev->dev);
 547 +       rs = spi_master_get_devdata(master);
 548 +
 549 +       clk_disable_unprepare(rs->clk);
 550 +
 551 +       return 0;
 552 +}
 553 +
 554 +MODULE_ALIAS("platform:" DRIVER_NAME);
 555 +
 556 +static const struct of_device_id rt2880_spi_match[] = {
 557 +       { .compatible = "ralink,rt2880-spi" },
 558 +       {},
 559 +};
 560 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 561 +
 562 +static struct platform_driver rt2880_spi_driver = {
 563 +       .driver = {
 564 +               .name = DRIVER_NAME,
 565 +               .owner = THIS_MODULE,
 566 +               .of_match_table = rt2880_spi_match,
 567 +       },
 568 +       .probe = rt2880_spi_probe,
 569 +       .remove = rt2880_spi_remove,
 570 +};
 571 +
 572 +module_platform_driver(rt2880_spi_driver);
 573 +
 574 +MODULE_DESCRIPTION("Ralink SPI driver");
 575 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 576 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 577 +MODULE_LICENSE("GPL");