1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:15:12 +0100
4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
6 Add the driver needed to make SPI work on Ralink SoC.
8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 Acked-by: John Crispin <blogic@openwrt.org>
11 drivers/spi/Kconfig | 6 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 439 insertions(+)
15 create mode 100644 drivers/spi/spi-rt2880.c
17 --- a/drivers/spi/Kconfig
18 +++ b/drivers/spi/Kconfig
19 @@ -433,6 +433,12 @@ config SPI_QUP
20 This driver can also be built as a module. If so, the module
21 will be called spi_qup.
24 + tristate "Ralink RT288x SPI Controller"
27 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
30 tristate "Samsung S3C24XX series SPI"
31 depends on ARCH_S3C24XX
32 --- a/drivers/spi/Makefile
33 +++ b/drivers/spi/Makefile
34 @@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa
35 obj-$(CONFIG_SPI_QUP) += spi-qup.o
36 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
37 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
38 +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
39 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
40 spi-s3c24xx-hw-y := spi-s3c24xx.o
41 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
43 +++ b/drivers/spi/spi-rt2880.c
46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
51 + * Some parts are based on spi-orion.c:
52 + * Author: Shadi Ammouri <shadi@marvell.com>
53 + * Copyright (C) 2007-2008 Marvell Ltd.
55 + * This program is free software; you can redistribute it and/or modify
56 + * it under the terms of the GNU General Public License version 2 as
57 + * published by the Free Software Foundation.
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/clk.h>
63 +#include <linux/err.h>
64 +#include <linux/delay.h>
65 +#include <linux/io.h>
66 +#include <linux/reset.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/platform_device.h>
70 +#define DRIVER_NAME "spi-rt2880"
71 +/* only one slave is supported*/
72 +#define RALINK_NUM_CHIPSELECTS 1
74 +#define RAMIPS_SPI_STAT 0x00
75 +#define RAMIPS_SPI_CFG 0x10
76 +#define RAMIPS_SPI_CTL 0x14
77 +#define RAMIPS_SPI_DATA 0x20
78 +#define RAMIPS_SPI_ADDR 0x24
79 +#define RAMIPS_SPI_BS 0x28
80 +#define RAMIPS_SPI_USER 0x2C
81 +#define RAMIPS_SPI_TXFIFO 0x30
82 +#define RAMIPS_SPI_RXFIFO 0x34
83 +#define RAMIPS_SPI_FIFO_STAT 0x38
84 +#define RAMIPS_SPI_MODE 0x3C
85 +#define RAMIPS_SPI_DEV_OFFSET 0x40
86 +#define RAMIPS_SPI_DMA 0x80
87 +#define RAMIPS_SPI_DMASTAT 0x84
88 +#define RAMIPS_SPI_ARBITER 0xF0
90 +/* SPISTAT register bit field */
91 +#define SPISTAT_BUSY BIT(0)
93 +/* SPICFG register bit field */
94 +#define SPICFG_ADDRMODE BIT(12)
95 +#define SPICFG_RXENVDIS BIT(11)
96 +#define SPICFG_RXCAP BIT(10)
97 +#define SPICFG_SPIENMODE BIT(9)
98 +#define SPICFG_MSBFIRST BIT(8)
99 +#define SPICFG_SPICLKPOL BIT(6)
100 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
101 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
102 +#define SPICFG_HIZSPI BIT(3)
103 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
104 +#define SPICFG_SPICLK_DIV2 0
105 +#define SPICFG_SPICLK_DIV4 1
106 +#define SPICFG_SPICLK_DIV8 2
107 +#define SPICFG_SPICLK_DIV16 3
108 +#define SPICFG_SPICLK_DIV32 4
109 +#define SPICFG_SPICLK_DIV64 5
110 +#define SPICFG_SPICLK_DIV128 6
111 +#define SPICFG_SPICLK_DISABLE 7
113 +/* SPICTL register bit field */
114 +#define SPICTL_START BIT(4)
115 +#define SPICTL_HIZSDO BIT(3)
116 +#define SPICTL_STARTWR BIT(2)
117 +#define SPICTL_STARTRD BIT(1)
118 +#define SPICTL_SPIENA BIT(0)
120 +/* SPIUSER register bit field */
121 +#define SPIUSER_USERMODE BIT(21)
122 +#define SPIUSER_INSTR_PHASE BIT(20)
123 +#define SPIUSER_ADDR_PHASE_MASK 0x7
124 +#define SPIUSER_ADDR_PHASE_OFFSET 17
125 +#define SPIUSER_MODE_PHASE BIT(16)
126 +#define SPIUSER_DUMMY_PHASE_MASK 0x3
127 +#define SPIUSER_DUMMY_PHASE_OFFSET 14
128 +#define SPIUSER_DATA_PHASE_MASK 0x3
129 +#define SPIUSER_DATA_PHASE_OFFSET 12
130 +#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
131 +#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
132 +#define SPIUSER_ADDR_TYPE_OFFSET 9
133 +#define SPIUSER_MODE_TYPE_OFFSET 6
134 +#define SPIUSER_DUMMY_TYPE_OFFSET 3
135 +#define SPIUSER_DATA_TYPE_OFFSET 0
136 +#define SPIUSER_TRANSFER_MASK 0x7
137 +#define SPIUSER_TRANSFER_SINGLE BIT(0)
138 +#define SPIUSER_TRANSFER_DUAL BIT(1)
139 +#define SPIUSER_TRANSFER_QUAD BIT(2)
141 +#define SPIUSER_TRANSFER_TYPE(type) ( \
142 + (type << SPIUSER_ADDR_TYPE_OFFSET) | \
143 + (type << SPIUSER_MODE_TYPE_OFFSET) | \
144 + (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
145 + (type << SPIUSER_DATA_TYPE_OFFSET) \
148 +/* SPIFIFOSTAT register bit field */
149 +#define SPIFIFOSTAT_TXEMPTY BIT(19)
150 +#define SPIFIFOSTAT_RXEMPTY BIT(18)
151 +#define SPIFIFOSTAT_TXFULL BIT(17)
152 +#define SPIFIFOSTAT_RXFULL BIT(16)
153 +#define SPIFIFOSTAT_FIFO_MASK 0xff
154 +#define SPIFIFOSTAT_TX_OFFSET 8
155 +#define SPIFIFOSTAT_RX_OFFSET 0
157 +#define SPI_FIFO_DEPTH 16
159 +/* SPIMODE register bit field */
160 +#define SPIMODE_MODE_OFFSET 24
161 +#define SPIMODE_DUMMY_OFFSET 0
163 +/* SPIARB register bit field */
164 +#define SPICTL_ARB_EN BIT(31)
165 +#define SPICTL_CSCTL1 BIT(16)
166 +#define SPI1_POR BIT(1)
167 +#define SPI0_POR BIT(0)
169 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
173 + struct spi_master *master;
174 + void __iomem *base;
175 + unsigned int sys_freq;
176 + unsigned int speed;
182 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
184 + return spi_master_get_devdata(spi->master);
187 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
189 + return ioread32(rs->base + reg);
192 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
195 + iowrite32(val, rs->base + reg);
198 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
200 + void __iomem *addr = rs->base + reg;
202 + iowrite32((ioread32(addr) | mask), addr);
205 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
207 + void __iomem *addr = rs->base + reg;
209 + iowrite32((ioread32(addr) & ~mask), addr);
212 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
214 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
219 + dev_dbg(&spi->dev, "speed:%u\n", speed);
222 + * the supported rates are: 2, 4, 8, ... 128
223 + * round up as we look for equal or less speed
225 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
226 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
227 + rate = roundup_pow_of_two(rate);
228 + dev_dbg(&spi->dev, "rate-2:%u\n", rate);
230 + /* Convert the rate to SPI clock divisor value. */
231 + prescale = ilog2(rate / 2);
232 + dev_dbg(&spi->dev, "prescale:%u\n", prescale);
234 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
235 + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
236 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
238 + /* some tolerance. double and add 100 */
239 + rs->wait_loops = (8 * HZ * loops_per_jiffy) /
240 + (clk_get_rate(rs->clk) / rate);
241 + rs->wait_loops = (rs->wait_loops << 1) + 100;
247 + * called only when no transfer is active on the bus
250 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
252 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
253 + unsigned int speed = spi->max_speed_hz;
256 + if ((t != NULL) && t->speed_hz)
257 + speed = t->speed_hz;
259 + if (rs->speed != speed) {
260 + dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
261 + rc = rt2880_spi_baudrate_set(spi, speed);
269 +static u32 get_arbiter_offset(struct spi_master *master)
273 + offset = RAMIPS_SPI_ARBITER;
274 + if (master->bus_num == 1)
275 + offset -= RAMIPS_SPI_DEV_OFFSET;
280 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
283 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
285 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
288 +static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
290 + int loop = rs->wait_loops * len;
292 + while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
302 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
304 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
305 + unsigned count = 0;
306 + u8 *rx = xfer->rx_buf;
307 + const u8 *tx = xfer->tx_buf;
310 + dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
311 + (tx != NULL) ? "tx" : " ",
312 + (rx != NULL) ? "rx" : " ");
315 + for (count = 0; count < xfer->len; count++) {
316 + rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
317 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
318 + err = rt2880_spi_wait_ready(rs, 1);
320 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
327 + for (count = 0; count < xfer->len; count++) {
328 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
329 + err = rt2880_spi_wait_ready(rs, 1);
331 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
334 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
342 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
343 + struct spi_message *m)
345 + struct rt2880_spi *rs = spi_master_get_devdata(master);
346 + struct spi_device *spi = m->spi;
347 + struct spi_transfer *t = NULL;
348 + int par_override = 0;
352 + /* Load defaults */
353 + status = rt2880_spi_setup_transfer(spi, NULL);
357 + list_for_each_entry(t, &m->transfers, transfer_list) {
358 + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
360 + "message rejected: invalid transfer data buffers\n");
365 + if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
367 + "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
368 + (rs->sys_freq / 128), t->speed_hz);
373 + if (par_override || t->speed_hz || t->bits_per_word) {
375 + status = rt2880_spi_setup_transfer(spi, t);
378 + if (!t->speed_hz && !t->bits_per_word)
383 + rt2880_spi_set_cs(rs, 1);
388 + m->actual_length += rt2880_spi_write_read(spi, t);
390 + if (t->delay_usecs)
391 + udelay(t->delay_usecs);
393 + if (t->cs_change) {
394 + rt2880_spi_set_cs(rs, 0);
401 + rt2880_spi_set_cs(rs, 0);
403 + m->status = status;
404 + spi_finalize_current_message(master);
409 +static int rt2880_spi_setup(struct spi_device *spi)
411 + struct spi_master *master = spi->master;
412 + struct rt2880_spi *rs = spi_master_get_devdata(master);
413 + u32 reg, old_reg, arbit_off;
415 + if ((spi->max_speed_hz > master->max_speed_hz) ||
416 + (spi->max_speed_hz < master->min_speed_hz)) {
417 + dev_err(&spi->dev, "invalide requested speed %d Hz\n",
418 + spi->max_speed_hz);
422 + if (!(master->bits_per_word_mask &
423 + BIT(spi->bits_per_word - 1))) {
424 + dev_err(&spi->dev, "invalide bits_per_word %d\n",
425 + spi->bits_per_word);
429 + /* the hardware seems can't work on mode0 force it to mode3 */
430 + if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
431 + dev_warn(&spi->dev, "force spi mode3\n");
432 + spi->mode |= SPI_MODE_3;
435 + /* chip polarity */
436 + arbit_off = get_arbiter_offset(master);
437 + reg = old_reg = rt2880_spi_read(rs, arbit_off);
438 + if (spi->mode & SPI_CS_HIGH) {
439 + switch (master->bus_num) {
448 + switch (master->bus_num) {
459 + if (master->bus_num == 1)
460 + reg |= SPICTL_ARB_EN;
462 + if (reg != old_reg)
463 + rt2880_spi_write(rs, arbit_off, reg);
468 +static void rt2880_spi_reset(struct rt2880_spi *rs)
470 + rt2880_spi_write(rs, RAMIPS_SPI_CFG,
471 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
472 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
473 + rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
476 +static int rt2880_spi_probe(struct platform_device *pdev)
478 + struct spi_master *master;
479 + struct rt2880_spi *rs;
480 + void __iomem *base;
481 + struct resource *r;
485 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
486 + base = devm_ioremap_resource(&pdev->dev, r);
488 + return PTR_ERR(base);
490 + clk = devm_clk_get(&pdev->dev, NULL);
492 + dev_err(&pdev->dev, "unable to get SYS clock\n");
493 + return PTR_ERR(clk);
496 + ret = clk_prepare_enable(clk);
500 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
501 + if (master == NULL) {
502 + dev_dbg(&pdev->dev, "master allocation failed\n");
507 + master->dev.of_node = pdev->dev.of_node;
508 + master->mode_bits = RT2880_SPI_MODE_BITS;
509 + master->bits_per_word_mask = SPI_BPW_MASK(8);
510 + master->min_speed_hz = clk_get_rate(clk) / 128;
511 + master->max_speed_hz = clk_get_rate(clk) / 2;
512 + master->flags = SPI_MASTER_HALF_DUPLEX;
513 + master->setup = rt2880_spi_setup;
514 + master->transfer_one_message = rt2880_spi_transfer_one_message;
515 + master->num_chipselect = RALINK_NUM_CHIPSELECTS;
517 + dev_set_drvdata(&pdev->dev, master);
519 + rs = spi_master_get_devdata(master);
520 + rs->master = master;
523 + rs->sys_freq = clk_get_rate(rs->clk);
524 + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
526 + device_reset(&pdev->dev);
528 + rt2880_spi_reset(rs);
530 + ret = devm_spi_register_master(&pdev->dev, master);
532 + dev_err(&pdev->dev, "devm_spi_register_master error.\n");
539 + spi_master_put(master);
542 + clk_disable_unprepare(clk);
547 +static int rt2880_spi_remove(struct platform_device *pdev)
549 + struct spi_master *master;
550 + struct rt2880_spi *rs;
552 + master = dev_get_drvdata(&pdev->dev);
553 + rs = spi_master_get_devdata(master);
555 + clk_disable_unprepare(rs->clk);
560 +MODULE_ALIAS("platform:" DRIVER_NAME);
562 +static const struct of_device_id rt2880_spi_match[] = {
563 + { .compatible = "ralink,rt2880-spi" },
566 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
568 +static struct platform_driver rt2880_spi_driver = {
570 + .name = DRIVER_NAME,
571 + .owner = THIS_MODULE,
572 + .of_match_table = rt2880_spi_match,
574 + .probe = rt2880_spi_probe,
575 + .remove = rt2880_spi_remove,
578 +module_platform_driver(rt2880_spi_driver);
580 +MODULE_DESCRIPTION("Ralink SPI driver");
581 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
582 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
583 +MODULE_LICENSE("GPL");