1 From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:00:32 +0100
4 Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/Kconfig | 3 +
9 drivers/gpio/Kconfig | 6 ++
10 drivers/gpio/Makefile | 1 +
11 drivers/gpio/gpio-mt7621.c | 177 ++++++++++++++++++++++++++++++++++++++++++++
12 4 files changed, 187 insertions(+)
13 create mode 100644 drivers/gpio/gpio-mt7621.c
15 --- a/arch/mips/Kconfig
16 +++ b/arch/mips/Kconfig
17 @@ -455,6 +455,9 @@ config RALINK
18 select RESET_CONTROLLER
21 + select ARCH_HAS_RESET_CONTROLLER
22 + select RESET_CONTROLLER
23 + select ARCH_REQUIRE_GPIOLIB
26 bool "SGI IP22 (Indy/Indigo2)"
27 --- a/drivers/gpio/Kconfig
28 +++ b/drivers/gpio/Kconfig
29 @@ -898,6 +898,12 @@ config GPIO_BCM_KONA
31 Turn on GPIO support for Broadcom "Kona" chips.
34 + bool "Mediatek GPIO Support"
35 + depends on SOC_MT7620 || SOC_MT7621
37 + Say yes here to support the Mediatek SoC GPIO device
39 comment "USB GPIO expanders:"
41 config GPIO_VIPERBOARD
42 --- a/drivers/gpio/Makefile
43 +++ b/drivers/gpio/Makefile
44 @@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx
45 obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
46 obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
47 obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
48 +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
51 +++ b/drivers/gpio/gpio-mt7621.c
54 + * This program is free software; you can redistribute it and/or modify it
55 + * under the terms of the GNU General Public License version 2 as published
56 + * by the Free Software Foundation.
58 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
59 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
62 +#include <linux/io.h>
63 +#include <linux/err.h>
64 +#include <linux/gpio.h>
65 +#include <linux/module.h>
66 +#include <linux/of_irq.h>
67 +#include <linux/spinlock.h>
68 +#include <linux/irqdomain.h>
69 +#include <linux/interrupt.h>
70 +#include <linux/platform_device.h>
72 +#define MTK_MAX_BANK 3
73 +#define MTK_BANK_WIDTH 32
75 +enum mediatek_gpio_reg {
89 +static void __iomem *mediatek_gpio_membase;
90 +static int mediatek_gpio_irq;
91 +static struct irq_domain *mediatek_gpio_irq_domain;
92 +static atomic_t irq_refcount = ATOMIC_INIT(0);
95 + struct gpio_chip chip;
100 +} *gc_map[MTK_MAX_BANK];
102 +static inline struct mtk_gc
103 +*to_mediatek_gpio(struct gpio_chip *chip)
105 + struct mtk_gc *mgc;
107 + mgc = container_of(chip, struct mtk_gc, chip);
113 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
115 + iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
119 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
121 + return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
125 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127 + struct mtk_gc *rg = to_mediatek_gpio(chip);
129 + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
133 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
135 + struct mtk_gc *rg = to_mediatek_gpio(chip);
137 + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
141 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
143 + struct mtk_gc *rg = to_mediatek_gpio(chip);
144 + unsigned long flags;
147 + spin_lock_irqsave(&rg->lock, flags);
148 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
150 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
151 + spin_unlock_irqrestore(&rg->lock, flags);
157 +mediatek_gpio_direction_output(struct gpio_chip *chip,
158 + unsigned offset, int value)
160 + struct mtk_gc *rg = to_mediatek_gpio(chip);
161 + unsigned long flags;
164 + spin_lock_irqsave(&rg->lock, flags);
165 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
167 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
168 + mediatek_gpio_set(chip, offset, value);
169 + spin_unlock_irqrestore(&rg->lock, flags);
175 +mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
177 + struct mtk_gc *rg = to_mediatek_gpio(chip);
178 + unsigned long flags;
181 + spin_lock_irqsave(&rg->lock, flags);
182 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
183 + spin_unlock_irqrestore(&rg->lock, flags);
185 + if (t & BIT(offset))
192 +mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
194 + struct mtk_gc *rg = to_mediatek_gpio(chip);
196 + return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
200 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
202 + const __be32 *id = of_get_property(bank, "reg", NULL);
203 + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
204 + sizeof(struct mtk_gc), GFP_KERNEL);
206 + if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
209 + gc_map[be32_to_cpu(*id)] = rg;
211 + memset(rg, 0, sizeof(struct mtk_gc));
213 + spin_lock_init(&rg->lock);
215 + rg->chip.dev = &pdev->dev;
216 + rg->chip.label = dev_name(&pdev->dev);
217 + rg->chip.of_node = bank;
218 + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
219 + rg->chip.ngpio = MTK_BANK_WIDTH;
220 + rg->chip.direction_input = mediatek_gpio_direction_input;
221 + rg->chip.direction_output = mediatek_gpio_direction_output;
222 + rg->chip.get_direction = mediatek_gpio_get_direction;
223 + rg->chip.get = mediatek_gpio_get;
224 + rg->chip.set = mediatek_gpio_set;
225 + if (mediatek_gpio_irq_domain)
226 + rg->chip.to_irq = mediatek_gpio_to_irq;
227 + rg->bank = be32_to_cpu(*id);
229 + /* set polarity to low for all gpios */
230 + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
232 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
234 + return gpiochip_add(&rg->chip);
238 +mediatek_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
242 + for (i = 0; i < MTK_MAX_BANK; i++) {
243 + struct mtk_gc *rg = gc_map[i];
244 + unsigned long pending;
250 + pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
252 + for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
253 + u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
255 + generic_handle_irq(map);
256 + mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
262 +mediatek_gpio_irq_unmask(struct irq_data *d)
264 + int pin = d->hwirq;
265 + int bank = pin / 32;
266 + struct mtk_gc *rg = gc_map[bank];
267 + unsigned long flags;
273 + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
274 + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
276 + spin_lock_irqsave(&rg->lock, flags);
277 + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
278 + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
279 + spin_unlock_irqrestore(&rg->lock, flags);
283 +mediatek_gpio_irq_mask(struct irq_data *d)
285 + int pin = d->hwirq;
286 + int bank = pin / 32;
287 + struct mtk_gc *rg = gc_map[bank];
288 + unsigned long flags;
294 + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
295 + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
297 + spin_lock_irqsave(&rg->lock, flags);
298 + mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
299 + mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
300 + spin_unlock_irqrestore(&rg->lock, flags);
304 +mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
306 + int pin = d->hwirq;
307 + int bank = pin / 32;
308 + struct mtk_gc *rg = gc_map[bank];
309 + u32 mask = BIT(d->hwirq);
314 + if (type == IRQ_TYPE_PROBE) {
315 + if ((rg->rising | rg->falling) & mask)
318 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
321 + if (type & IRQ_TYPE_EDGE_RISING)
322 + rg->rising |= mask;
324 + rg->rising &= ~mask;
326 + if (type & IRQ_TYPE_EDGE_FALLING)
327 + rg->falling |= mask;
329 + rg->falling &= ~mask;
334 +static struct irq_chip mediatek_gpio_irq_chip = {
336 + .irq_unmask = mediatek_gpio_irq_unmask,
337 + .irq_mask = mediatek_gpio_irq_mask,
338 + .irq_mask_ack = mediatek_gpio_irq_mask,
339 + .irq_set_type = mediatek_gpio_irq_type,
343 +mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
345 + irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
346 + irq_set_handler_data(irq, d);
351 +static const struct irq_domain_ops irq_domain_ops = {
352 + .xlate = irq_domain_xlate_onecell,
353 + .map = mediatek_gpio_gpio_map,
357 +mediatek_gpio_probe(struct platform_device *pdev)
359 + struct device_node *bank, *np = pdev->dev.of_node;
360 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
362 + mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
363 + if (IS_ERR(mediatek_gpio_membase))
364 + return PTR_ERR(mediatek_gpio_membase);
366 + mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
367 + if (mediatek_gpio_irq) {
368 + mediatek_gpio_irq_domain = irq_domain_add_linear(np,
369 + MTK_MAX_BANK * MTK_BANK_WIDTH,
370 + &irq_domain_ops, NULL);
371 + if (!mediatek_gpio_irq_domain)
372 + dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
375 + for_each_child_of_node(np, bank)
376 + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
377 + mediatek_gpio_bank_probe(pdev, bank);
379 + if (mediatek_gpio_irq_domain)
380 + irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
385 +static const struct of_device_id mediatek_gpio_match[] = {
386 + { .compatible = "mtk,mt7621-gpio" },
389 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
391 +static struct platform_driver mediatek_gpio_driver = {
392 + .probe = mediatek_gpio_probe,
394 + .name = "mt7621_gpio",
395 + .owner = THIS_MODULE,
396 + .of_match_table = mediatek_gpio_match,
401 +mediatek_gpio_init(void)
403 + return platform_driver_register(&mediatek_gpio_driver);
406 +subsys_initcall(mediatek_gpio_init);