1 From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Aug 2014 10:53:40 +0200
4 Subject: [PATCH 51/57] SPI: MIPS: ralink: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
9 1 file changed, 205 insertions(+), 13 deletions(-)
11 diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c
12 index ac9de67..1c6b72d 100644
13 --- a/drivers/spi/spi-rt2880.c
14 +++ b/drivers/spi/spi-rt2880.c
17 #include <linux/reset.h>
18 #include <linux/spi/spi.h>
19 +#include <linux/of_device.h>
20 #include <linux/platform_device.h>
22 +#include <ralink_regs.h>
24 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
26 #define DRIVER_NAME "spi-rt2880"
27 /* only one slave is supported*/
28 #define RALINK_NUM_CHIPSELECTS 1
30 /* SPIFIFOSTAT register bit field */
31 #define SPIFIFOSTAT_TXFULL BIT(17)
33 +#define MT7621_SPI_TRANS 0x00
34 +#define SPITRANS_BUSY BIT(16)
35 +#define MT7621_SPI_OPCODE 0x04
36 +#define MT7621_SPI_DATA0 0x08
37 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
38 +#define SPI_CTL_START BIT(8)
39 +#define MT7621_SPI_POLAR 0x38
40 +#define MT7621_SPI_MASTER 0x28
41 +#define MT7621_SPI_SPACE 0x3c
45 +struct rt2880_spi_ops {
46 + void (*init_hw)(struct rt2880_spi *rs);
47 + void (*set_cs)(struct rt2880_spi *rs, int enable);
48 + int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
49 + unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
53 struct spi_master *master;
55 @@ -70,6 +94,8 @@ struct rt2880_spi {
60 + struct rt2880_spi_ops *ops;
63 static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
64 @@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
68 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
70 +/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
72 + // set default clock to hclk/5
73 + master &= ~(0xfff << 16);
74 + master |= 0x3 << 16;
80 * called only when no transfer is active on the bus
82 @@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
84 if (rs->speed != speed) {
85 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
86 - rc = rt2880_spi_baudrate_set(spi, speed);
87 + rc = rs->ops->baudrate_set(spi, speed);
91 @@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
92 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
95 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
97 + u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
103 + rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
106 static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
109 @@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
113 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
117 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
120 + status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
121 + if ((status & SPITRANS_BUSY) == 0) {
132 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
133 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
135 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
137 @@ -239,6 +305,100 @@ out:
142 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
144 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
145 + struct spi_transfer *next = NULL;
146 + const u8 *tx = xfer->tx_buf;
149 + int len = xfer->len;
154 + if (!list_is_last(&xfer->transfer_list, list)) {
155 + next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
159 + trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
160 + trans &= ~SPI_CTL_TX_RX_CNT_MASK;
163 + u32 data0 = 0, opcode = 0;
165 + switch (xfer->len) {
167 + data0 |= tx[7] << 24;
169 + data0 |= tx[6] << 16;
171 + data0 |= tx[5] << 8;
175 + opcode |= tx[3] << 8;
177 + opcode |= tx[2] << 16;
179 + opcode |= tx[1] << 24;
185 + dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
189 + rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
190 + rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
191 + trans |= xfer->len;
195 + trans |= (next->len << 4);
196 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
197 + trans |= SPI_CTL_START;
198 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
200 + mt7621_spi_wait_till_ready(rs);
203 + u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
204 + u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
206 + switch (next->len) {
208 + rx[7] = (opcode >> 24) & 0xff;
210 + rx[6] = (opcode >> 16) & 0xff;
212 + rx[5] = (opcode >> 8) & 0xff;
214 + rx[4] = opcode & 0xff;
216 + rx[3] = (data0 >> 24) & 0xff;
218 + rx[2] = (data0 >> 16) & 0xff;
220 + rx[1] = (data0 >> 8) & 0xff;
222 + rx[0] = data0 & 0xff;
226 + dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
235 static int rt2880_spi_transfer_one_message(struct spi_master *master,
236 struct spi_message *m)
238 @@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_message(struct spi_master *master,
242 - rt2880_spi_set_cs(rs, 1);
243 + rs->ops->set_cs(rs, 1);
248 - m->actual_length += rt2880_spi_write_read(spi, t);
249 + m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
252 udelay(t->delay_usecs);
255 - rt2880_spi_set_cs(rs, 0);
256 + rs->ops->set_cs(rs, 0);
263 - rt2880_spi_set_cs(rs, 0);
264 + rs->ops->set_cs(rs, 0);
267 spi_finalize_current_message(master);
268 @@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt2880_spi *rs)
269 rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
272 +static void mt7621_spi_reset(struct rt2880_spi *rs)
274 + u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
276 + master &= ~(0xfff << 16);
280 + rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
283 +static struct rt2880_spi_ops spi_ops[] = {
285 + .init_hw = rt2880_spi_reset,
286 + .set_cs = rt2880_spi_set_cs,
287 + .baudrate_set = rt2880_spi_baudrate_set,
288 + .write_read = rt2880_spi_write_read,
290 + .init_hw = mt7621_spi_reset,
291 + .set_cs = mt7621_spi_set_cs,
292 + .baudrate_set = mt7621_spi_baudrate_set,
293 + .write_read = mt7621_spi_write_read,
297 +static const struct of_device_id rt2880_spi_match[] = {
298 + { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
299 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
302 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
304 static int rt2880_spi_probe(struct platform_device *pdev)
306 + const struct of_device_id *match;
307 struct spi_master *master;
308 struct rt2880_spi *rs;
310 @@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platform_device *pdev)
314 + match = of_match_device(rt2880_spi_match, &pdev->dev);
318 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
319 base = devm_ioremap_resource(&pdev->dev, r);
321 @@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platform_device *pdev)
324 rs->sys_freq = clk_get_rate(rs->clk);
325 + rs->ops = (struct rt2880_spi_ops *) match->data;
326 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
327 spin_lock_irqsave(&rs->lock, flags);
329 device_reset(&pdev->dev);
331 - rt2880_spi_reset(rs);
332 + rs->ops->init_hw(rs);
334 return spi_register_master(master);
336 @@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct platform_device *pdev)
338 MODULE_ALIAS("platform:" DRIVER_NAME);
340 -static const struct of_device_id rt2880_spi_match[] = {
341 - { .compatible = "ralink,rt2880-spi" },
344 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
346 static struct platform_driver rt2880_spi_driver = {