1 From 810c2afe0c7e1be9352ad512b337110b100bfe3a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 36/57] NET: add mt7621 ethernet driver
7 arch/mips/include/asm/rt2880/board-custom.h | 153 +++
8 arch/mips/include/asm/rt2880/eureka_ep430.h | 204 ++++
9 arch/mips/include/asm/rt2880/generic.h | 42 +
10 arch/mips/include/asm/rt2880/lm.h | 32 +
11 arch/mips/include/asm/rt2880/prom.h | 50 +
12 arch/mips/include/asm/rt2880/rt_mmap.h | 796 ++++++++++++++++
13 arch/mips/include/asm/rt2880/serial_rt2880.h | 443 +++++++++
14 arch/mips/include/asm/rt2880/sizes.h | 52 +
15 arch/mips/include/asm/rt2880/surfboard.h | 70 ++
16 arch/mips/include/asm/rt2880/surfboardint.h | 190 ++++
17 arch/mips/include/asm/rt2880/war.h | 25 +
18 drivers/net/ethernet/Kconfig | 1 +
19 drivers/net/ethernet/Makefile | 1 +
20 drivers/net/ethernet/raeth/Kconfig | 344 +++++++
21 drivers/net/ethernet/raeth/Makefile | 7 +
22 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
23 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
24 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
25 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
26 drivers/net/ethernet/raeth/ra_mac.c | 98 ++
27 drivers/net/ethernet/raeth/ra_mac.h | 35 +
28 drivers/net/ethernet/raeth/raether.c | 693 ++++++++++++++
29 drivers/net/ethernet/raeth/raether.h | 92 ++
30 drivers/net/ethernet/raeth/raether_pdma.c | 212 +++++
31 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
32 25 files changed, 5915 insertions(+)
33 create mode 100644 arch/mips/include/asm/rt2880/board-custom.h
34 create mode 100644 arch/mips/include/asm/rt2880/eureka_ep430.h
35 create mode 100644 arch/mips/include/asm/rt2880/generic.h
36 create mode 100644 arch/mips/include/asm/rt2880/lm.h
37 create mode 100644 arch/mips/include/asm/rt2880/prom.h
38 create mode 100644 arch/mips/include/asm/rt2880/rt_mmap.h
39 create mode 100644 arch/mips/include/asm/rt2880/serial_rt2880.h
40 create mode 100644 arch/mips/include/asm/rt2880/sizes.h
41 create mode 100644 arch/mips/include/asm/rt2880/surfboard.h
42 create mode 100644 arch/mips/include/asm/rt2880/surfboardint.h
43 create mode 100644 arch/mips/include/asm/rt2880/war.h
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
47 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
48 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
49 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
50 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
51 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
52 create mode 100644 drivers/net/ethernet/raeth/raether.c
53 create mode 100644 drivers/net/ethernet/raeth/raether.h
54 create mode 100644 drivers/net/ethernet/raeth/raether_pdma.c
55 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
58 +++ b/arch/mips/include/asm/rt2880/board-custom.h
60 +/* Copyright Statement:
62 + * This software/firmware and related documentation ("MediaTek Software") are
63 + * protected under relevant copyright laws. The information contained herein
64 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
65 + * Without the prior written permission of MediaTek inc. and/or its licensors,
66 + * any reproduction, modification, use or disclosure of MediaTek Software,
67 + * and information contained herein, in whole or in part, shall be strictly prohibited.
69 +/* MediaTek Inc. (C) 2010. All rights reserved.
71 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
72 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
73 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
74 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
75 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
76 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
77 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
78 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
79 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
80 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
81 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
82 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
83 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
84 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
85 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
86 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
87 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
88 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
90 + * The following software/firmware and/or related documentation ("MediaTek Software")
91 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
92 + * applicable license agreements with MediaTek Inc.
95 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
96 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
98 +#include <linux/autoconf.h>
100 +/*=======================================================================*/
102 +/*=======================================================================*/
103 +#ifdef MTK_EMMC_SUPPORT
104 +#define CFG_DEV_MSDC0
106 +#define CFG_DEV_MSDC1
107 +#define CFG_DEV_MSDC2
108 +#define CFG_DEV_MSDC3
109 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
111 +SDIO slot index number used by connectivity combo chip:
112 +0: invalid (used by memory card)
116 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
118 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
122 +/*=======================================================================*/
124 +/*=======================================================================*/
125 +#define CFG_DEV_UART1
126 +#define CFG_DEV_UART2
127 +#define CFG_DEV_UART3
128 +#define CFG_DEV_UART4
130 +#define CFG_UART_PORTS (4)
132 +/*=======================================================================*/
134 +/*=======================================================================*/
136 +//#define CFG_I2C_HIGH_SPEED_MODE
137 +//#define CFG_I2C_DMA_MODE
139 +/*=======================================================================*/
141 +/*=======================================================================*/
142 +#define ADB_SERIAL "E1K"
146 +/*=======================================================================*/
147 +/* MT6575 NAND FLASH */
148 +/*=======================================================================*/
150 +#define RAMDOM_READ 1<<0
151 +#define CACHE_READ 1<<1
152 +/*******************************************************************************
153 + * NFI & ECC Configuration
154 + *******************************************************************************/
157 + u16 id; //deviceid+menuid
163 + u32 timmingsetting;
164 + char devciename[14];
165 + u32 advancedmode; //
166 +}flashdev_info,*pflashdev_info;
168 +static const flashdev_info g_FlashTable[]={
170 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
171 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
172 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
173 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
174 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
176 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
177 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
178 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
179 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
180 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
182 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
183 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
184 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
185 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
187 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
188 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
189 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
190 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
192 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
195 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
196 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
201 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
203 +//uboot only support 1 cs
204 +#define NFI_CS_NUM (2)
205 +#define NFI_DEFAULT_CS (0)
207 +#define USE_AHB_MODE (1)
209 +#define PLATFORM_EVB (1)
211 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
214 +++ b/arch/mips/include/asm/rt2880/eureka_ep430.h
216 +/**************************************************************************
218 + * This program is free software; you can redistribute it and/or modify it
219 + * under the terms of the GNU General Public License as published by the
220 + * Free Software Foundation; either version 2 of the License, or (at your
221 + * option) any later version.
223 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
224 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
225 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
226 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
227 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
228 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
229 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
230 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
231 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
232 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
234 + * You should have received a copy of the GNU General Public License along
235 + * with this program; if not, write to the Free Software Foundation, Inc.,
236 + * 675 Mass Ave, Cambridge, MA 02139, USA.
239 + **************************************************************************
242 +#ifndef _EUREKA_EP430_H
243 +#define _EUREKA_EP430_H
246 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
247 +#include <asm/byteorder.h> /* for cpu_to_le32() */
248 +#include <asm/mach-ralink/rt_mmap.h>
252 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
253 + * bytes when running bigendian.
256 +#define MV_WRITE(ofs, data) \
257 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
258 +#define MV_READ(ofs, data) \
259 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
260 +#define MV_READ_DATA(ofs) \
261 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
263 +#define MV_WRITE_16(ofs, data) \
264 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
265 +#define MV_READ_16(ofs, data) \
266 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
268 +#define MV_WRITE_8(ofs, data) \
269 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
270 +#define MV_READ_8(ofs, data) \
271 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
273 +#define MV_SET_REG_BITS(ofs,bits) \
274 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
275 +#define MV_RESET_REG_BITS(ofs,bits) \
276 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
278 +#define RALINK_PCI_CONFIG_ADDR 0x20
279 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
281 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
282 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
283 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
284 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
285 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
286 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
287 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
288 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
289 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
290 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
291 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
292 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
293 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
294 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
295 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
297 +#elif defined(CONFIG_RALINK_RT3883)
299 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
300 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
301 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
302 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
303 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
304 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
305 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
306 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
312 +#define RT3883_PCI_OFFSET 0x1000
313 +#define RT3883_PCIE_OFFSET 0x2000
315 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
316 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
317 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
318 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
319 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
321 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
322 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
323 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
324 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
325 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
326 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
328 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
330 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
331 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
332 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
333 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
334 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
335 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
336 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
337 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
343 +#define RT6855_PCIE0_OFFSET 0x2000
344 +#define RT6855_PCIE1_OFFSET 0x3000
346 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
347 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
348 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
349 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
350 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
351 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
352 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
353 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
355 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
356 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
357 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
358 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
359 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
360 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
361 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
362 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
364 +#elif defined (CONFIG_RALINK_MT7621)
366 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
367 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
368 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
369 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
370 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
371 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
372 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
373 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
380 +#define RT6855_PCIE0_OFFSET 0x2000
381 +#define RT6855_PCIE1_OFFSET 0x3000
382 +#define RT6855_PCIE2_OFFSET 0x4000
384 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
385 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
386 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
387 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
388 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
389 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
390 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
391 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
393 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
394 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
395 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
396 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
397 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
398 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
399 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
400 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
402 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
403 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
404 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
405 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
406 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
407 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
408 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
409 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
411 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
412 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
414 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
416 +#error "undefined in PCI"
421 +++ b/arch/mips/include/asm/rt2880/generic.h
424 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
426 + * This program is free software; you can distribute it and/or modify it
427 + * under the terms of the GNU General Public License (Version 2) as
428 + * published by the Free Software Foundation.
430 + * This program is distributed in the hope it will be useful, but WITHOUT
431 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
432 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
433 + * for more details.
435 + * You should have received a copy of the GNU General Public License along
436 + * with this program; if not, write to the Free Software Foundation, Inc.,
437 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
439 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
441 +#ifndef __ASM_SURFBOARD_GENERIC_H
442 +#define __ASM_SURFBOARD_GENERIC_H
444 +#include <asm/addrspace.h>
445 +#include <asm/byteorder.h>
446 +#include <asm/mach-ralink/rt_mmap.h>
451 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
452 +#define GORESET (0x1)
455 + * Power-off register
457 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
458 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
459 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
460 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
461 +#define POWEROFF (0x0) /* drive low */
464 +#endif /* __ASM_SURFBOARD_GENERIC_H */
466 +++ b/arch/mips/include/asm/rt2880/lm.h
468 +#include <linux/version.h>
472 + struct resource resource;
475 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
481 + struct device_driver drv;
482 + int (*probe)(struct lm_device *);
483 + void (*remove)(struct lm_device *);
484 + int (*suspend)(struct lm_device *, u32);
485 + int (*resume)(struct lm_device *);
488 +int lm_driver_register(struct lm_driver *drv);
489 +void lm_driver_unregister(struct lm_driver *drv);
491 +int lm_device_register(struct lm_device *dev);
493 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
494 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
495 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
497 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
498 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
501 +++ b/arch/mips/include/asm/rt2880/prom.h
504 + * Carsten Langgaard, carstenl@mips.com
505 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
507 + * ########################################################################
509 + * This program is free software; you can distribute it and/or modify it
510 + * under the terms of the GNU General Public License (Version 2) as
511 + * published by the Free Software Foundation.
513 + * This program is distributed in the hope it will be useful, but WITHOUT
514 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
515 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
516 + * for more details.
518 + * You should have received a copy of the GNU General Public License along
519 + * with this program; if not, write to the Free Software Foundation, Inc.,
520 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
522 + * ########################################################################
524 + * MIPS boards bootprom interface for the Linux kernel.
528 +#ifndef _MIPS_PROM_H
529 +#define _MIPS_PROM_H
531 +extern char *prom_getcmdline(void);
532 +extern char *prom_getenv(char *name);
533 +extern void setup_prom_printf(int tty_no);
534 +extern void prom_setup_printf(int tty_no);
535 +extern void prom_printf(char *fmt, ...);
536 +extern void prom_init_cmdline(void);
537 +extern void prom_meminit(void);
538 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
539 +extern void prom_free_prom_memory (void);
540 +extern void mips_display_message(const char *str);
541 +extern void mips_display_word(unsigned int num);
542 +extern int get_ethernet_addr(char *ethernet_addr);
544 +/* Memory descriptor management. */
545 +#define PROM_MAX_PMEMBLOCKS 32
546 +struct prom_pmemblock {
547 + unsigned long base; /* Within KSEG0. */
548 + unsigned int size; /* In bytes. */
549 + unsigned int type; /* free or prom memory */
552 +#endif /* !(_MIPS_PROM_H) */
554 +++ b/arch/mips/include/asm/rt2880/rt_mmap.h
556 +/**************************************************************************
558 + * BRIEF MODULE DESCRIPTION
559 + * register definition for Ralink RT-series SoC
561 + * Copyright 2007 Ralink Inc.
563 + * This program is free software; you can redistribute it and/or modify it
564 + * under the terms of the GNU General Public License as published by the
565 + * Free Software Foundation; either version 2 of the License, or (at your
566 + * option) any later version.
568 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
569 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
570 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
571 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
572 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
573 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
574 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
575 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
576 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
577 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
579 + * You should have received a copy of the GNU General Public License along
580 + * with this program; if not, write to the Free Software Foundation, Inc.,
581 + * 675 Mass Ave, Cambridge, MA 02139, USA.
584 + **************************************************************************
587 +#ifndef __RALINK_MMAP__
588 +#define __RALINK_MMAP__
590 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
592 +#define RALINK_SYSCTL_BASE 0xA0300000
593 +#define RALINK_TIMER_BASE 0xA0300100
594 +#define RALINK_INTCL_BASE 0xA0300200
595 +#define RALINK_MEMCTRL_BASE 0xA0300300
596 +#define RALINK_UART_BASE 0xA0300500
597 +#define RALINK_PIO_BASE 0xA0300600
598 +#define RALINK_I2C_BASE 0xA0300900
599 +#define RALINK_SPI_BASE 0xA0300B00
600 +#define RALINK_UART_LITE_BASE 0xA0300C00
601 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
602 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
603 +#define RALINK_PCI_BASE 0xA0500000
604 +#define RALINK_11N_MAC_BASE 0xA0600000
606 +//Interrupt Controller
607 +#define RALINK_INTCTL_TIMER0 (1<<0)
608 +#define RALINK_INTCTL_WDTIMER (1<<1)
609 +#define RALINK_INTCTL_UART (1<<2)
610 +#define RALINK_INTCTL_PIO (1<<3)
611 +#define RALINK_INTCTL_PCM (1<<4)
612 +#define RALINK_INTCTL_UARTLITE (1<<8)
613 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
615 +//Reset Control Register
616 +#define RALINK_TIMER_RST (1<<1)
617 +#define RALINK_INTC_RST (1<<2)
618 +#define RALINK_MC_RST (1<<3)
619 +#define RALINK_CPU_RST (1<<4)
620 +#define RALINK_UART_RST (1<<5)
621 +#define RALINK_PIO_RST (1<<6)
622 +#define RALINK_I2C_RST (1<<9)
623 +#define RALINK_SPI_RST (1<<11)
624 +#define RALINK_UART2_RST (1<<12)
625 +#define RALINK_PCI_RST (1<<16)
626 +#define RALINK_2860_RST (1<<17)
627 +#define RALINK_FE_RST (1<<18)
628 +#define RALINK_PCM_RST (1<<19)
631 +#elif defined (CONFIG_RALINK_RT2880_MP)
633 +#define RALINK_SYSCTL_BASE 0xA0300000
634 +#define RALINK_TIMER_BASE 0xA0300100
635 +#define RALINK_INTCL_BASE 0xA0300200
636 +#define RALINK_MEMCTRL_BASE 0xA0300300
637 +#define RALINK_UART_BASE 0xA0300500
638 +#define RALINK_PIO_BASE 0xA0300600
639 +#define RALINK_I2C_BASE 0xA0300900
640 +#define RALINK_SPI_BASE 0xA0300B00
641 +#define RALINK_UART_LITE_BASE 0x00300C00
642 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
643 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
644 +#define RALINK_PCI_BASE 0xA0440000
645 +#define RALINK_11N_MAC_BASE 0xA0480000
647 +//Interrupt Controller
648 +#define RALINK_INTCTL_TIMER0 (1<<0)
649 +#define RALINK_INTCTL_WDTIMER (1<<1)
650 +#define RALINK_INTCTL_UART (1<<2)
651 +#define RALINK_INTCTL_PIO (1<<3)
652 +#define RALINK_INTCTL_PCM (1<<4)
653 +#define RALINK_INTCTL_UARTLITE (1<<8)
654 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
656 +//Reset Control Register
657 +#define RALINK_TIMER_RST (1<<1)
658 +#define RALINK_INTC_RST (1<<2)
659 +#define RALINK_MC_RST (1<<3)
660 +#define RALINK_CPU_RST (1<<4)
661 +#define RALINK_UART_RST (1<<5)
662 +#define RALINK_PIO_RST (1<<6)
663 +#define RALINK_I2C_RST (1<<9)
664 +#define RALINK_SPI_RST (1<<11)
665 +#define RALINK_UART2_RST (1<<12)
666 +#define RALINK_PCI_RST (1<<16)
667 +#define RALINK_2860_RST (1<<17)
668 +#define RALINK_FE_RST (1<<18)
669 +#define RALINK_PCM_RST (1<<19)
671 +#elif defined (CONFIG_RALINK_RT3052)
673 +#define RALINK_SYSCTL_BASE 0xB0000000
674 +#define RALINK_TIMER_BASE 0xB0000100
675 +#define RALINK_INTCL_BASE 0xB0000200
676 +#define RALINK_MEMCTRL_BASE 0xB0000300
677 +#define RALINK_PCM_BASE 0xB0000400
678 +#define RALINK_UART_BASE 0x10000500
679 +#define RALINK_PIO_BASE 0xB0000600
680 +#define RALINK_GDMA_BASE 0xB0000700
681 +#define RALINK_NAND_CTRL_BASE 0xB0000800
682 +#define RALINK_I2C_BASE 0xB0000900
683 +#define RALINK_I2S_BASE 0xB0000A00
684 +#define RALINK_SPI_BASE 0xB0000B00
685 +#define RALINK_UART_LITE_BASE 0x10000C00
686 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
687 +#define RALINK_ETH_SW_BASE 0xB0110000
688 +#define RALINK_11N_MAC_BASE 0xB0180000
689 +#define RALINK_USB_OTG_BASE 0x101C0000
691 +//Interrupt Controller
692 +#define RALINK_INTCTL_SYSCTL (1<<0)
693 +#define RALINK_INTCTL_TIMER0 (1<<1)
694 +#define RALINK_INTCTL_WDTIMER (1<<2)
695 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
696 +#define RALINK_INTCTL_PCM (1<<4)
697 +#define RALINK_INTCTL_UART (1<<5)
698 +#define RALINK_INTCTL_PIO (1<<6)
699 +#define RALINK_INTCTL_DMA (1<<7)
700 +#define RALINK_INTCTL_NAND (1<<8)
701 +#define RALINK_INTCTL_PC (1<<9)
702 +#define RALINK_INTCTL_I2S (1<<10)
703 +#define RALINK_INTCTL_UARTLITE (1<<12)
704 +#define RALINK_INTCTL_ESW (1<<17)
705 +#define RALINK_INTCTL_OTG (1<<18)
706 +#define RALINK_INTCTL_OTG_IRQN 18
707 +#define RALINK_INTCTL_GLOBAL (1<<31)
709 +//Reset Control Register
710 +#define RALINK_SYS_RST (1<<0)
711 +#define RALINK_CPU_RST (1<<1)
712 +#define RALINK_TIMER_RST (1<<8)
713 +#define RALINK_INTC_RST (1<<9)
714 +#define RALINK_MC_RST (1<<10)
715 +#define RALINK_PCM_RST (1<<11)
716 +#define RALINK_UART_RST (1<<12)
717 +#define RALINK_PIO_RST (1<<13)
718 +#define RALINK_DMA_RST (1<<14)
719 +#define RALINK_I2C_RST (1<<16)
720 +#define RALINK_I2S_RST (1<<17)
721 +#define RALINK_SPI_RST (1<<18)
722 +#define RALINK_UARTL_RST (1<<19)
723 +#define RALINK_RT2872_RST (1<<20)
724 +#define RALINK_FE_RST (1<<21)
725 +#define RALINK_OTG_RST (1<<22)
726 +#define RALINK_SW_RST (1<<23)
727 +#define RALINK_EPHY_RST (1<<24)
729 +#elif defined (CONFIG_RALINK_RT3352)
731 +#define RALINK_SYSCTL_BASE 0xB0000000
732 +#define RALINK_TIMER_BASE 0xB0000100
733 +#define RALINK_INTCL_BASE 0xB0000200
734 +#define RALINK_MEMCTRL_BASE 0xB0000300
735 +#define RALINK_UART_BASE 0x10000500
736 +#define RALINK_PIO_BASE 0xB0000600
737 +#define RALINK_I2C_BASE 0xB0000900
738 +#define RALINK_I2S_BASE 0xB0000A00
739 +#define RALINK_SPI_BASE 0xB0000B00
740 +#define RALINK_NAND_CTRL_BASE 0xB0000800
741 +#define RALINK_UART_LITE_BASE 0x10000C00
742 +#define RALINK_PCM_BASE 0xB0002000
743 +#define RALINK_GDMA_BASE 0xB0002800
744 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
745 +#define RALINK_ETH_SW_BASE 0xB0110000
746 +#define RALINK_USB_DEV_BASE 0x10120000
747 +#define RALINK_11N_MAC_BASE 0xB0180000
748 +#define RALINK_USB_HOST_BASE 0x101C0000
750 +#define RALINK_MCNT_CFG 0xB0000D00
751 +#define RALINK_COMPARE 0xB0000D04
752 +#define RALINK_COUNT 0xB0000D08
754 +//Interrupt Controller
755 +#define RALINK_INTCTL_SYSCTL (1<<0)
756 +#define RALINK_INTCTL_TIMER0 (1<<1)
757 +#define RALINK_INTCTL_WDTIMER (1<<2)
758 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
759 +#define RALINK_INTCTL_PCM (1<<4)
760 +#define RALINK_INTCTL_UART (1<<5)
761 +#define RALINK_INTCTL_PIO (1<<6)
762 +#define RALINK_INTCTL_DMA (1<<7)
763 +#define RALINK_INTCTL_PC (1<<9)
764 +#define RALINK_INTCTL_I2S (1<<10)
765 +#define RALINK_INTCTL_UARTLITE (1<<12)
766 +#define RALINK_INTCTL_ESW (1<<17)
767 +#define RALINK_INTCTL_OTG (1<<18)
768 +#define RALINK_INTCTL_GLOBAL (1<<31)
770 +//Reset Control Register
771 +#define RALINK_SYS_RST (1<<0)
772 +#define RALINK_TIMER_RST (1<<8)
773 +#define RALINK_INTC_RST (1<<9)
774 +#define RALINK_MC_RST (1<<10)
775 +#define RALINK_PCM_RST (1<<11)
776 +#define RALINK_UART_RST (1<<12)
777 +#define RALINK_PIO_RST (1<<13)
778 +#define RALINK_DMA_RST (1<<14)
779 +#define RALINK_I2C_RST (1<<16)
780 +#define RALINK_I2S_RST (1<<17)
781 +#define RALINK_SPI_RST (1<<18)
782 +#define RALINK_UARTL_RST (1<<19)
783 +#define RALINK_WLAN_RST (1<<20)
784 +#define RALINK_FE_RST (1<<21)
785 +#define RALINK_UHST_RST (1<<22)
786 +#define RALINK_ESW_RST (1<<23)
787 +#define RALINK_EPHY_RST (1<<24)
788 +#define RALINK_UDEV_RST (1<<25)
791 +//Clock Conf Register
792 +#define RALINK_UPHY1_CLK_EN (1<<20)
793 +#define RALINK_UPHY0_CLK_EN (1<<18)
794 +#define RALINK_GE1_CLK_EN (1<<16)
797 +#elif defined (CONFIG_RALINK_RT5350)
799 +#define RALINK_SYSCTL_BASE 0xB0000000
800 +#define RALINK_TIMER_BASE 0xB0000100
801 +#define RALINK_INTCL_BASE 0xB0000200
802 +#define RALINK_MEMCTRL_BASE 0xB0000300
803 +#define RALINK_UART_BASE 0x10000500
804 +#define RALINK_PIO_BASE 0xB0000600
805 +#define RALINK_I2C_BASE 0xB0000900
806 +#define RALINK_I2S_BASE 0xB0000A00
807 +#define RALINK_SPI_BASE 0xB0000B00
808 +#define RALINK_UART_LITE_BASE 0x10000C00
809 +#define RALINK_PCM_BASE 0xB0002000
810 +#define RALINK_GDMA_BASE 0xB0002800
811 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
812 +#define RALINK_ETH_SW_BASE 0xB0110000
813 +#define RALINK_USB_DEV_BASE 0x10120000
814 +#define RALINK_11N_MAC_BASE 0xB0180000
815 +#define RALINK_USB_HOST_BASE 0x101C0000
817 +#define RALINK_MCNT_CFG 0xB0000D00
818 +#define RALINK_COMPARE 0xB0000D04
819 +#define RALINK_COUNT 0xB0000D08
821 +//Interrupt Controller
822 +#define RALINK_INTCTL_SYSCTL (1<<0)
823 +#define RALINK_INTCTL_TIMER0 (1<<1)
824 +#define RALINK_INTCTL_WDTIMER (1<<2)
825 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
826 +#define RALINK_INTCTL_PCM (1<<4)
827 +#define RALINK_INTCTL_UART (1<<5)
828 +#define RALINK_INTCTL_PIO (1<<6)
829 +#define RALINK_INTCTL_DMA (1<<7)
830 +#define RALINK_INTCTL_PC (1<<9)
831 +#define RALINK_INTCTL_I2S (1<<10)
832 +#define RALINK_INTCTL_UARTLITE (1<<12)
833 +#define RALINK_INTCTL_ESW (1<<17)
834 +#define RALINK_INTCTL_USB_HOST (1<<18)
835 +#define RALINK_INTCTL_USB_DEV (1<<19)
836 +#define RALINK_INTCTL_GLOBAL (1<<31)
838 +//Reset Control Register
839 +#define RALINK_SYS_RST (1<<0)
840 +#define RALINK_TIMER_RST (1<<8)
841 +#define RALINK_INTC_RST (1<<9)
842 +#define RALINK_MC_RST (1<<10)
843 +#define RALINK_PCM_RST (1<<11)
844 +#define RALINK_UART_RST (1<<12)
845 +#define RALINK_PIO_RST (1<<13)
846 +#define RALINK_DMA_RST (1<<14)
847 +#define RALINK_I2C_RST (1<<16)
848 +#define RALINK_I2S_RST (1<<17)
849 +#define RALINK_SPI_RST (1<<18)
850 +#define RALINK_UARTL_RST (1<<19)
851 +#define RALINK_WLAN_RST (1<<20)
852 +#define RALINK_FE_RST (1<<21)
853 +#define RALINK_UHST_RST (1<<22)
854 +#define RALINK_ESW_RST (1<<23)
855 +#define RALINK_EPHY_RST (1<<24)
856 +#define RALINK_UDEV_RST (1<<25)
857 +#define RALINK_MIPSC_RST (1<<28)
859 +//Clock Conf Register
860 +#define RALINK_UPHY0_CLK_EN (1<<18)
861 +#define RALINK_GE1_CLK_EN (1<<16)
863 +#elif defined (CONFIG_RALINK_RT2883)
865 +#define RALINK_SYSCTL_BASE 0xB0000000
866 +#define RALINK_TIMER_BASE 0xB0000100
867 +#define RALINK_INTCL_BASE 0xB0000200
868 +#define RALINK_MEMCTRL_BASE 0xB0000300
869 +#define RALINK_PCM_BASE 0xB0000400
870 +#define RALINK_UART_BASE 0x10000500
871 +#define RALINK_PIO_BASE 0xB0000600
872 +#define RALINK_GDMA_BASE 0xB0000700
873 +#define RALINK_NAND_CTRL_BASE 0xB0000800
874 +#define RALINK_I2C_BASE 0xB0000900
875 +#define RALINK_I2S_BASE 0xB0000A00
876 +#define RALINK_SPI_BASE 0xB0000B00
877 +#define RALINK_UART_LITE_BASE 0x10000C00
878 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
879 +#define RALINK_PCI_BASE 0xB0140000
880 +#define RALINK_11N_MAC_BASE 0xB0180000
881 +#define RALINK_USB_OTG_BASE 0x101C0000
883 +//Interrupt Controller
884 +#define RALINK_INTCTL_SYSCTL (1<<0)
885 +#define RALINK_INTCTL_TIMER0 (1<<1)
886 +#define RALINK_INTCTL_WDTIMER (1<<2)
887 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
888 +#define RALINK_INTCTL_PCM (1<<4)
889 +#define RALINK_INTCTL_UART (1<<5)
890 +#define RALINK_INTCTL_PIO (1<<6)
891 +#define RALINK_INTCTL_DMA (1<<7)
892 +#define RALINK_INTCTL_NAND (1<<8)
893 +#define RALINK_INTCTL_PC (1<<9)
894 +#define RALINK_INTCTL_I2S (1<<10)
895 +#define RALINK_INTCTL_UARTLITE (1<<12)
896 +#define RALINK_INTCTL_OTG (1<<18)
897 +#define RALINK_INTCTL_OTG_IRQN 18
898 +#define RALINK_INTCTL_GLOBAL (1<<31)
900 +//Reset Control Register
901 +#define RALINK_SYS_RST (1<<0)
902 +#define RALINK_CPU_RST (1<<1)
903 +#define RALINK_TIMER_RST (1<<8)
904 +#define RALINK_INTC_RST (1<<9)
905 +#define RALINK_MC_RST (1<<10)
906 +#define RALINK_PCM_RST (1<<11)
907 +#define RALINK_UART_RST (1<<12)
908 +#define RALINK_PIO_RST (1<<13)
909 +#define RALINK_DMA_RST (1<<14)
910 +#define RALINK_I2C_RST (1<<16)
911 +#define RALINK_I2S_RST (1<<17)
912 +#define RALINK_SPI_RST (1<<18)
913 +#define RALINK_UARTL_RST (1<<19)
914 +#define RALINK_WLAN_RST (1<<20)
915 +#define RALINK_FE_RST (1<<21)
916 +#define RALINK_OTG_RST (1<<22)
917 +#define RALINK_PCIE_RST (1<<23)
919 +#elif defined (CONFIG_RALINK_RT3883)
921 +#define RALINK_SYSCTL_BASE 0xB0000000
922 +#define RALINK_TIMER_BASE 0xB0000100
923 +#define RALINK_INTCL_BASE 0xB0000200
924 +#define RALINK_MEMCTRL_BASE 0xB0000300
925 +#define RALINK_UART_BASE 0x10000500
926 +#define RALINK_PIO_BASE 0xB0000600
927 +#define RALINK_NOR_CTRL_BASE 0xB0000700
928 +#define RALINK_NAND_CTRL_BASE 0xB0000810
929 +#define RALINK_I2C_BASE 0xB0000900
930 +#define RALINK_I2S_BASE 0xB0000A00
931 +#define RALINK_SPI_BASE 0xB0000B00
932 +#define RALINK_UART_LITE_BASE 0x10000C00
933 +#define RALINK_PCM_BASE 0xB0002000
934 +#define RALINK_GDMA_BASE 0xB0002800
935 +#define RALINK_CODEC1_BASE 0xB0003000
936 +#define RALINK_CODEC2_BASE 0xB0003800
937 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
938 +#define RALINK_USB_DEV_BASE 0x10120000
939 +#define RALINK_PCI_BASE 0xB0140000
940 +#define RALINK_11N_MAC_BASE 0xB0180000
941 +#define RALINK_USB_HOST_BASE 0x101C0000
942 +#define RALINK_PCIE_BASE 0xB0200000
944 +//Interrupt Controller
945 +#define RALINK_INTCTL_SYSCTL (1<<0)
946 +#define RALINK_INTCTL_TIMER0 (1<<1)
947 +#define RALINK_INTCTL_WDTIMER (1<<2)
948 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
949 +#define RALINK_INTCTL_PCM (1<<4)
950 +#define RALINK_INTCTL_UART (1<<5)
951 +#define RALINK_INTCTL_PIO (1<<6)
952 +#define RALINK_INTCTL_DMA (1<<7)
953 +#define RALINK_INTCTL_NAND (1<<8)
954 +#define RALINK_INTCTL_PC (1<<9)
955 +#define RALINK_INTCTL_I2S (1<<10)
956 +#define RALINK_INTCTL_UARTLITE (1<<12)
957 +#define RALINK_INTCTL_UHST (1<<18)
958 +#define RALINK_INTCTL_UDEV (1<<19)
960 +//Reset Control Register
961 +#define RALINK_SYS_RST (1<<0)
962 +#define RALINK_TIMER_RST (1<<8)
963 +#define RALINK_INTC_RST (1<<9)
964 +#define RALINK_MC_RST (1<<10)
965 +#define RALINK_PCM_RST (1<<11)
966 +#define RALINK_UART_RST (1<<12)
967 +#define RALINK_PIO_RST (1<<13)
968 +#define RALINK_DMA_RST (1<<14)
969 +#define RALINK_NAND_RST (1<<15)
970 +#define RALINK_I2C_RST (1<<16)
971 +#define RALINK_I2S_RST (1<<17)
972 +#define RALINK_SPI_RST (1<<18)
973 +#define RALINK_UARTL_RST (1<<19)
974 +#define RALINK_WLAN_RST (1<<20)
975 +#define RALINK_FE_RST (1<<21)
976 +#define RALINK_UHST_RST (1<<22)
977 +#define RALINK_PCIE_RST (1<<23)
978 +#define RALINK_PCI_RST (1<<24)
979 +#define RALINK_UDEV_RST (1<<25)
980 +#define RALINK_FLASH_RST (1<<26)
982 +//Clock Conf Register
983 +#define RALINK_UPHY1_CLK_EN (1<<20)
984 +#define RALINK_UPHY0_CLK_EN (1<<18)
985 +#define RALINK_GE1_CLK_EN (1<<16)
987 +#elif defined (CONFIG_RALINK_RT6855)
989 +#define RALINK_SYSCTL_BASE 0xB0000000
990 +#define RALINK_TIMER_BASE 0xB0000100
991 +#define RALINK_INTCL_BASE 0xB0000200
992 +#define RALINK_MEMCTRL_BASE 0xB0000300
993 +#define RALINK_UART_BASE 0x10000500
994 +#define RALINK_PIO_BASE 0xB0000600
995 +#define RALINK_I2C_BASE 0xB0000900
996 +#define RALINK_I2S_BASE 0xB0000A00
997 +#define RALINK_SPI_BASE 0xB0000B00
998 +#define RALINK_NAND_CTRL_BASE 0xB0000800
999 +#define RALINK_UART_LITE_BASE 0x10000C00
1000 +#define RALINK_PCM_BASE 0xB0002000
1001 +#define RALINK_GDMA_BASE 0xB0002800
1002 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1003 +#define RALINK_ETH_SW_BASE 0xB0110000
1004 +#define RALINK_PCI_BASE 0xB0140000
1005 +#define RALINK_USB_DEV_BASE 0x10120000
1006 +#define RALINK_11N_MAC_BASE 0xB0180000
1007 +#define RALINK_USB_HOST_BASE 0x101C0000
1009 +#define RALINK_MCNT_CFG 0xB0000D00
1010 +#define RALINK_COMPARE 0xB0000D04
1011 +#define RALINK_COUNT 0xB0000D08
1013 +//Interrupt Controller
1014 +#define RALINK_INTCTL_SYSCTL (1<<0)
1015 +#define RALINK_INTCTL_TIMER0 (1<<1)
1016 +#define RALINK_INTCTL_WDTIMER (1<<2)
1017 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1018 +#define RALINK_INTCTL_PCM (1<<4)
1019 +#define RALINK_INTCTL_UART (1<<5)
1020 +#define RALINK_INTCTL_PIO (1<<6)
1021 +#define RALINK_INTCTL_DMA (1<<7)
1022 +#define RALINK_INTCTL_PC (1<<9)
1023 +#define RALINK_INTCTL_I2S (1<<10)
1024 +#define RALINK_INTCTL_UARTLITE (1<<12)
1025 +#define RALINK_INTCTL_ESW (1<<17)
1026 +#define RALINK_INTCTL_OTG (1<<18)
1027 +#define RALINK_INTCTL_GLOBAL (1<<31)
1029 +//Reset Control Register
1030 +#define RALINK_SYS_RST (1<<0)
1031 +#define RALINK_TIMER_RST (1<<8)
1032 +#define RALINK_INTC_RST (1<<9)
1033 +#define RALINK_MC_RST (1<<10)
1034 +#define RALINK_PCM_RST (1<<11)
1035 +#define RALINK_UART_RST (1<<12)
1036 +#define RALINK_PIO_RST (1<<13)
1037 +#define RALINK_DMA_RST (1<<14)
1038 +#define RALINK_I2C_RST (1<<16)
1039 +#define RALINK_I2S_RST (1<<17)
1040 +#define RALINK_SPI_RST (1<<18)
1041 +#define RALINK_UARTL_RST (1<<19)
1042 +#define RALINK_FE_RST (1<<21)
1043 +#define RALINK_UHST_RST (1<<22)
1044 +#define RALINK_ESW_RST (1<<23)
1045 +#define RALINK_EPHY_RST (1<<24)
1046 +#define RALINK_UDEV_RST (1<<25)
1047 +#define RALINK_PCIE0_RST (1<<26)
1048 +#define RALINK_PCIE1_RST (1<<27)
1050 +//Clock Conf Register
1051 +#define RALINK_UPHY0_CLK_EN (1<<25)
1052 +#define RALINK_PCIE0_CLK_EN (1<<26)
1053 +#define RALINK_PCIE1_CLK_EN (1<<27)
1056 +#elif defined (CONFIG_RALINK_MT7620)
1058 +#define RALINK_SYSCTL_BASE 0xB0000000
1059 +#define RALINK_TIMER_BASE 0xB0000100
1060 +#define RALINK_INTCL_BASE 0xB0000200
1061 +#define RALINK_MEMCTRL_BASE 0xB0000300
1062 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1063 +#define RALINK_UART_BASE 0x10000500
1064 +#define RALINK_PIO_BASE 0xB0000600
1065 +#define RALINK_NAND_CTRL_BASE 0xB0000810
1066 +#define RALINK_I2C_BASE 0xB0000900
1067 +#define RALINK_I2S_BASE 0xB0000A00
1068 +#define RALINK_SPI_BASE 0xB0000B00
1069 +#define RALINK_UART_LITE_BASE 0x10000C00
1070 +#define RALINK_MIPS_CNT_BASE 0x10000D00
1071 +#define RALINK_PCM_BASE 0xB0002000
1072 +#define RALINK_GDMA_BASE 0xB0002800
1073 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
1074 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1075 +#define RALINK_PPE_BASE 0xB0100C00
1076 +#define RALINK_ETH_SW_BASE 0xB0110000
1077 +#define RALINK_USB_DEV_BASE 0x10120000
1078 +#define RALINK_MSDC_BASE 0xB0130000
1079 +#define RALINK_PCI_BASE 0xB0140000
1080 +#define RALINK_11N_MAC_BASE 0xB0180000
1081 +#define RALINK_USB_HOST_BASE 0x101C0000
1083 +#define RALINK_MCNT_CFG 0xB0000D00
1084 +#define RALINK_COMPARE 0xB0000D04
1085 +#define RALINK_COUNT 0xB0000D08
1087 +//Interrupt Controller
1088 +#define RALINK_INTCTL_SYSCTL (1<<0)
1089 +#define RALINK_INTCTL_TIMER0 (1<<1)
1090 +#define RALINK_INTCTL_WDTIMER (1<<2)
1091 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1092 +#define RALINK_INTCTL_PCM (1<<4)
1093 +#define RALINK_INTCTL_UART (1<<5)
1094 +#define RALINK_INTCTL_PIO (1<<6)
1095 +#define RALINK_INTCTL_DMA (1<<7)
1096 +#define RALINK_INTCTL_PC (1<<9)
1097 +#define RALINK_INTCTL_I2S (1<<10)
1098 +#define RALINK_INTCTL_SPI (1<<11)
1099 +#define RALINK_INTCTL_UARTLITE (1<<12)
1100 +#define RALINK_INTCTL_CRYPTO (1<<13)
1101 +#define RALINK_INTCTL_ESW (1<<17)
1102 +#define RALINK_INTCTL_UHST (1<<18)
1103 +#define RALINK_INTCTL_UDEV (1<<19)
1104 +#define RALINK_INTCTL_GLOBAL (1<<31)
1106 +//Reset Control Register
1107 +#define RALINK_SYS_RST (1<<0)
1108 +#define RALINK_TIMER_RST (1<<8)
1109 +#define RALINK_INTC_RST (1<<9)
1110 +#define RALINK_MC_RST (1<<10)
1111 +#define RALINK_PCM_RST (1<<11)
1112 +#define RALINK_UART_RST (1<<12)
1113 +#define RALINK_PIO_RST (1<<13)
1114 +#define RALINK_DMA_RST (1<<14)
1115 +#define RALINK_I2C_RST (1<<16)
1116 +#define RALINK_I2S_RST (1<<17)
1117 +#define RALINK_SPI_RST (1<<18)
1118 +#define RALINK_UARTL_RST (1<<19)
1119 +#define RALINK_FE_RST (1<<21)
1120 +#define RALINK_UHST_RST (1<<22)
1121 +#define RALINK_ESW_RST (1<<23)
1122 +#define RALINK_EPHY_RST (1<<24)
1123 +#define RALINK_UDEV_RST (1<<25)
1124 +#define RALINK_PCIE0_RST (1<<26)
1125 +#define RALINK_PCIE1_RST (1<<27)
1126 +#define RALINK_MIPS_CNT_RST (1<<28)
1127 +#define RALINK_CRYPTO_RST (1<<29)
1129 +//Clock Conf Register
1130 +#define RALINK_UPHY0_CLK_EN (1<<25)
1131 +#define RALINK_UPHY1_CLK_EN (1<<22)
1132 +#define RALINK_PCIE0_CLK_EN (1<<26)
1133 +#define RALINK_PCIE1_CLK_EN (1<<27)
1135 +//CPU PLL CFG Register
1136 +#define CPLL_SW_CONFIG (0x1UL << 31)
1137 +#define CPLL_MULT_RATIO_SHIFT 16
1138 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1139 +#define CPLL_DIV_RATIO_SHIFT 10
1140 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1141 +#define BASE_CLOCK 40 /* Mhz */
1143 +#elif defined (CONFIG_RALINK_MT7621)
1145 +#define RALINK_SYSCTL_BASE 0xBE000000
1146 +#define RALINK_TIMER_BASE 0xBE000100
1147 +#define RALINK_INTCL_BASE 0xBE000200
1148 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
1149 +#define RALINK_MIPS_CNT_BASE 0x1E000500
1150 +#define RALINK_PIO_BASE 0xBE000600
1151 +#define RALINK_SPDIF_BASE 0xBE000700
1152 +#define RALINK_I2C_BASE 0xBE000900
1153 +#define RALINK_I2S_BASE 0xBE000A00
1154 +#define RALINK_SPI_BASE 0xBE000B00
1155 +#define RALINK_UART_LITE1_BASE 0x1E000C00
1156 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1157 +#define RALINK_UART_LITE2_BASE 0x1E000D00
1158 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1159 +#define RALINK_UART_LITE3_BASE 0x1E000E00
1160 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
1161 +#define RALINK_PCM_BASE 0xBE002000
1162 +#define RALINK_GDMA_BASE 0xBE002800
1163 +#define RALINK_NAND_CTRL_BASE 0xBE003000
1164 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
1165 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
1166 +#define RALINK_MEMCTRL_BASE 0xBE005000
1167 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
1168 +#define RALINK_HS_DMA_BASE 0xBE007000
1169 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
1170 +#define RALINK_PPE_BASE 0xBE100C00
1171 +#define RALINK_ETH_SW_BASE 0xBE110000
1172 +#define RALINK_ROM_BASE 0xBE118000
1173 +#define RALINK_MSDC_BASE 0xBE130000
1174 +#define RALINK_PCI_BASE 0xBE140000
1175 +#define RALINK_USB_HOST_BASE 0x1E1C0000
1176 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
1178 +#define RALINK_MCNT_CFG 0xBE000500
1179 +#define RALINK_COMPARE 0xBE000504
1180 +#define RALINK_COUNT 0xBE000508
1182 +//Interrupt Controller
1183 +#define RALINK_INTCTL_FE (1<<3)
1184 +#define RALINK_INTCTL_PCIE0 (1<<4)
1185 +#define RALINK_INTCTL_SYSCTL (1<<6)
1186 +#define RALINK_INTCTL_I2C (1<<8)
1187 +#define RALINK_INTCTL_DRAMC (1<<9)
1188 +#define RALINK_INTCTL_PCM (1<<10)
1189 +#define RALINK_INTCTL_HSDMA (1<<11)
1190 +#define RALINK_INTCTL_PIO (1<<12)
1191 +#define RALINK_INTCTL_DMA (1<<13)
1192 +#define RALINK_INTCTL_NFI (1<<14)
1193 +#define RALINK_INTCTL_NFIECC (1<<15)
1194 +#define RALINK_INTCTL_I2S (1<<16)
1195 +#define RALINK_INTCTL_SPI (1<<17)
1196 +#define RALINK_INTCTL_SPDIF (1<<18)
1197 +#define RALINK_INTCTL_CRYPTO (1<<19)
1198 +#define RALINK_INTCTL_SDXC (1<<20)
1199 +#define RALINK_INTCTL_PCTRL (1<<21)
1200 +#define RALINK_INTCTL_USB (1<<22)
1201 +#define RALINK_INTCTL_SWITCH (1<<23)
1202 +#define RALINK_INTCTL_PCIE1 (1<<24)
1203 +#define RALINK_INTCTL_PCIE2 (1<<25)
1204 +#define RALINK_INTCTL_UART1 (1<<26)
1205 +#define RALINK_INTCTL_UART2 (1<<27)
1206 +#define RALINK_INTCTL_UART3 (1<<28)
1207 +#define RALINK_INTCTL_WDTIMER (1<<29)
1208 +#define RALINK_INTCTL_TIMER0 (1<<30)
1209 +#define RALINK_INTCTL_TIMER1 (1<<31)
1212 +//Reset Control Register
1213 +#define RALINK_SYS_RST (1<<0)
1214 +#define RALINK_MCM_RST (1<<1)
1215 +#define RALINK_HSDMA_RST (1<<2)
1216 +#define RALINK_FE_RST (1<<6)
1217 +#define RALINK_SPDIF_RST (1<<7)
1218 +#define RALINK_TIMER_RST (1<<8)
1219 +#define RALINK_INTC_RST (1<<9)
1220 +#define RALINK_MC_RST (1<<10)
1221 +#define RALINK_PCM_RST (1<<11)
1222 +#define RALINK_PIO_RST (1<<13)
1223 +#define RALINK_DMA_RST (1<<14)
1224 +#define RALINK_NAND_RST (1<<15)
1225 +#define RALINK_I2C_RST (1<<16)
1226 +#define RALINK_I2S_RST (1<<17)
1227 +#define RALINK_SPI_RST (1<<18)
1228 +#define RALINK_UART1_RST (1<<19)
1229 +#define RALINK_UART2_RST (1<<20)
1230 +#define RALINK_UART3_RST (1<<21)
1231 +#define RALINK_ETH_RST (1<<23)
1232 +#define RALINK_PCIE0_RST (1<<24)
1233 +#define RALINK_PCIE1_RST (1<<25)
1234 +#define RALINK_PCIE2_RST (1<<26)
1235 +#define RALINK_AUX_STCK_RST (1<<28)
1236 +#define RALINK_CRYPTO_RST (1<<29)
1237 +#define RALINK_SDXC_RST (1<<30)
1238 +#define RALINK_PPE_RST (1<<31)
1240 +//Clock Conf Register
1241 +#define RALINK_PCIE0_CLK_EN (1<<24)
1242 +#define RALINK_PCIE1_CLK_EN (1<<25)
1243 +#define RALINK_PCIE2_CLK_EN (1<<26)
1244 +//#define RALINK_UPHY0_CLK_EN (1<<27)
1245 +//#define RALINK_UPHY1_CLK_EN (1<<28)
1247 +//CPU PLL CFG Register
1248 +#define CPLL_SW_CONFIG (0x1UL << 31)
1249 +#define CPLL_MULT_RATIO_SHIFT 16
1250 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1251 +#define CPLL_DIV_RATIO_SHIFT 10
1252 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1253 +#define BASE_CLOCK 40 /* Mhz */
1255 +#define RALINK_TESTSTAT 0xBE000018
1256 +#define RALINK_TESTSTAT2 0xBE00001C
1258 +#elif defined (CONFIG_RALINK_MT7628)
1260 +#define RALINK_SYSCTL_BASE 0xB0000000
1261 +#define RALINK_TIMER_BASE 0xB0000100
1262 +#define RALINK_INTCL_BASE 0xB0000200
1263 +#define RALINK_MEMCTRL_BASE 0xB0000300
1264 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1265 +#define RALINK_MIPS_CNT_BASE 0x10000500
1266 +#define RALINK_PIO_BASE 0xB0000600
1267 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
1268 +#define RALINK_I2C_BASE 0xB0000900
1269 +#define RALINK_I2S_BASE 0xB0000A00
1270 +#define RALINK_SPI_BASE 0xB0000B00
1271 +#define RALINK_UART_LITE1_BASE 0x10000C00
1272 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1273 +#define RALINK_UART_LITE2_BASE 0x10000D00
1274 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1275 +#define RALINK_UART_LITE3_BASE 0x10000E00
1276 +#define RALINK_PCM_BASE 0xB0002000
1277 +#define RALINK_GDMA_BASE 0xB0002800
1278 +#define RALINK_AES_ENGINE_BASE 0xB0004000
1279 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
1280 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1281 +#define RALINK_PPE_BASE 0xB0100C00
1282 +#define RALINK_ETH_SW_BASE 0xB0110000
1283 +#define RALINK_USB_DEV_BASE 0xB0120000
1284 +#define RALINK_MSDC_BASE 0xB0130000
1285 +#define RALINK_PCI_BASE 0xB0140000
1286 +#define RALINK_11N_MAC_BASE 0xB0180000
1287 +#define RALINK_USB_HOST_BASE 0x101C0000
1289 +#define RALINK_MCNT_CFG 0xB0000500
1290 +#define RALINK_COMPARE 0xB0000504
1291 +#define RALINK_COUNT 0xB0000508
1294 +//Interrupt Controller
1295 +#define RALINK_INTCTL_SYSCTL (1<<0)
1296 +#define RALINK_INTCTL_TIMER0 (1<<1)
1297 +#define RALINK_INTCTL_WDTIMER (1<<2)
1298 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1299 +#define RALINK_INTCTL_PCM (1<<4)
1300 +#define RALINK_INTCTL_UART (1<<5)
1301 +#define RALINK_INTCTL_PIO (1<<6)
1302 +#define RALINK_INTCTL_DMA (1<<7)
1303 +#define RALINK_INTCTL_PC (1<<9)
1304 +#define RALINK_INTCTL_I2S (1<<10)
1305 +#define RALINK_INTCTL_SPI (1<<11)
1306 +#define RALINK_INTCTL_UARTLITE (1<<12)
1307 +#define RALINK_INTCTL_CRYPTO (1<<13)
1308 +#define RALINK_INTCTL_ESW (1<<17)
1309 +#define RALINK_INTCTL_UHST (1<<18)
1310 +#define RALINK_INTCTL_UDEV (1<<19)
1311 +#define RALINK_INTCTL_GLOBAL (1<<31)
1313 +//Reset Control Register
1314 +#define RALINK_SYS_RST (1<<0)
1315 +#define RALINK_TIMER_RST (1<<8)
1316 +#define RALINK_INTC_RST (1<<9)
1317 +#define RALINK_MC_RST (1<<10)
1318 +#define RALINK_PCM_RST (1<<11)
1319 +#define RALINK_UART_RST (1<<12)
1320 +#define RALINK_PIO_RST (1<<13)
1321 +#define RALINK_DMA_RST (1<<14)
1322 +#define RALINK_I2C_RST (1<<16)
1323 +#define RALINK_I2S_RST (1<<17)
1324 +#define RALINK_SPI_RST (1<<18)
1325 +#define RALINK_UARTL_RST (1<<19)
1326 +#define RALINK_FE_RST (1<<21)
1327 +#define RALINK_UHST_RST (1<<22)
1328 +#define RALINK_ESW_RST (1<<23)
1329 +#define RALINK_EPHY_RST (1<<24)
1330 +#define RALINK_UDEV_RST (1<<25)
1331 +#define RALINK_PCIE0_RST (1<<26)
1332 +#define RALINK_PCIE1_RST (1<<27)
1333 +#define RALINK_MIPS_CNT_RST (1<<28)
1334 +#define RALINK_CRYPTO_RST (1<<29)
1336 +//Clock Conf Register
1337 +#define RALINK_UPHY0_CLK_EN (1<<25)
1338 +#define RALINK_UPHY1_CLK_EN (1<<22)
1339 +#define RALINK_PCIE0_CLK_EN (1<<26)
1340 +#define RALINK_PCIE1_CLK_EN (1<<27)
1342 +//CPU PLL CFG Register
1343 +#define CPLL_SW_CONFIG (0x1UL << 31)
1344 +#define CPLL_MULT_RATIO_SHIFT 16
1345 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1346 +#define CPLL_DIV_RATIO_SHIFT 10
1347 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1348 +#define BASE_CLOCK 40 /* Mhz */
1353 +++ b/arch/mips/include/asm/rt2880/serial_rt2880.h
1355 +/**************************************************************************
1357 + * BRIEF MODULE DESCRIPTION
1358 + * serial port definition for Ralink RT2880 solution
1360 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
1362 + * This program is free software; you can redistribute it and/or modify it
1363 + * under the terms of the GNU General Public License as published by the
1364 + * Free Software Foundation; either version 2 of the License, or (at your
1365 + * option) any later version.
1367 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1368 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1369 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1370 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1371 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1372 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1373 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1374 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1375 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1376 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1378 + * You should have received a copy of the GNU General Public License along
1379 + * with this program; if not, write to the Free Software Foundation, Inc.,
1380 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1383 + **************************************************************************
1384 + * May 2007 Bruce Chang
1390 + **************************************************************************
1393 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1394 +#define RT2880_UART_RBR_OFFSET 0x00
1395 +#define RT2880_UART_TBR_OFFSET 0x00
1396 +#define RT2880_UART_IER_OFFSET 0x04
1397 +#define RT2880_UART_IIR_OFFSET 0x08
1398 +#define RT2880_UART_FCR_OFFSET 0x08
1399 +#define RT2880_UART_LCR_OFFSET 0x0C
1400 +#define RT2880_UART_MCR_OFFSET 0x10
1401 +#define RT2880_UART_LSR_OFFSET 0x14
1402 +#define RT2880_UART_DLL_OFFSET 0x00
1403 +#define RT2880_UART_DLM_OFFSET 0x04
1405 +#define RT2880_UART_RBR_OFFSET 0x00
1406 +#define RT2880_UART_TBR_OFFSET 0x04
1407 +#define RT2880_UART_IER_OFFSET 0x08
1408 +#define RT2880_UART_IIR_OFFSET 0x0C
1409 +#define RT2880_UART_FCR_OFFSET 0x10
1410 +#define RT2880_UART_LCR_OFFSET 0x14
1411 +#define RT2880_UART_MCR_OFFSET 0x18
1412 +#define RT2880_UART_LSR_OFFSET 0x1C
1413 +#define RT2880_UART_DLL_OFFSET 0x2C
1414 +#define RT2880_UART_DLM_OFFSET 0x30
1417 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
1418 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
1419 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
1420 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
1421 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
1422 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
1423 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
1424 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
1425 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
1426 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
1429 +#if defined (CONFIG_RALINK_RT2880) || \
1430 + defined (CONFIG_RALINK_RT2883) || \
1431 + defined (CONFIG_RALINK_RT3883) || \
1432 + defined (CONFIG_RALINK_RT3352) || \
1433 + defined (CONFIG_RALINK_RT5350) || \
1434 + defined (CONFIG_RALINK_RT6855) || \
1435 + defined (CONFIG_RALINK_MT7620) || \
1436 + defined (CONFIG_RALINK_RT3052)
1438 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1440 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
1441 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
1443 + * Out: Fifo custom trigger levels
1447 +#define UART_IER 8 /* Out: Interrupt Enable Register */
1448 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
1452 +#define UART_IIR 12 /* In: Interrupt ID Register */
1453 +#define UART_EFR 12 /* I/O: Extended Features Register */
1454 + /* (DLAB=1, 16C660 only) */
1456 +#define UART_FCR 16 /* Out: FIFO Control Register */
1457 +#define UART_LCR 20 /* Out: Line Control Register */
1458 +#define UART_MCR 24 /* Out: Modem Control Register */
1459 +#define UART_LSR 28 /* In: Line Status Register */
1460 +#define UART_MSR 32 /* In: Modem Status Register */
1461 +#define UART_SCR 36 /* I/O: Scratch Register */
1462 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
1463 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
1464 + * unpredictable values to be written to the Divisor Latch
1466 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
1470 +#define UART_RX 0 /* In: Receive buffer */
1471 +#define UART_TX 0 /* Out: Transmit buffer */
1472 +#define UART_DLL 0 /* Out: Divisor Latch Low */
1473 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1475 + * Out: Fifo custom trigger levels */
1477 +#define UART_DLM 4 /* Out: Divisor Latch High */
1478 +#define UART_IER 4 /* Out: Interrupt Enable Register */
1479 +#define UART_FCTR 4 /* Feature Control Register */
1481 +#define UART_IIR 8 /* In: Interrupt ID Register */
1482 +#define UART_FCR 8 /* Out: FIFO Control Register */
1483 +#define UART_EFR 8 /* I/O: Extended Features Register */
1485 +#define UART_LCR 12 /* Out: Line Control Register */
1486 +#define UART_MCR 16 /* Out: Modem Control Register */
1487 +#define UART_LSR 20 /* In: Line Status Register */
1488 +#define UART_MSR 24 /* In: Modem Status Register */
1489 +#define UART_SCR 28 /* I/O: Scratch Register */
1490 +#define UART_EMSR 28 /* Extended Mode Select Register */
1496 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
1497 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1498 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1499 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1500 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1502 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
1504 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
1506 +//#define UART_IIR 2 /* In: Interrupt ID Register */
1507 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1508 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1509 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1510 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1511 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1512 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1514 +//#define UART_FCR 2 /* Out: FIFO Control Register */
1515 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1516 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1517 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1518 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1520 + * Note: The FIFO trigger levels are chip specific:
1521 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
1522 + * PC16550D: 1 4 8 14 xx xx xx xx
1523 + * TI16C550A: 1 4 8 14 xx xx xx xx
1524 + * TI16C550C: 1 4 8 14 xx xx xx xx
1525 + * ST16C550: 1 4 8 14 xx xx xx xx
1526 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
1527 + * NS16C552: 1 4 8 14 xx xx xx xx
1528 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
1529 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
1530 + * TI16C752: 8 16 56 60 8 16 32 56
1532 +#define UART_FCR_R_TRIG_00 0x00
1533 +#define UART_FCR_R_TRIG_01 0x40
1534 +#define UART_FCR_R_TRIG_10 0x80
1535 +#define UART_FCR_R_TRIG_11 0xc0
1536 +#define UART_FCR_T_TRIG_00 0x00
1537 +#define UART_FCR_T_TRIG_01 0x10
1538 +#define UART_FCR_T_TRIG_10 0x20
1539 +#define UART_FCR_T_TRIG_11 0x30
1541 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
1542 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
1543 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
1544 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
1545 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
1546 +/* 16650 definitions */
1547 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
1548 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
1549 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
1550 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
1551 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
1552 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
1553 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
1554 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
1555 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
1557 +//#define UART_LCR 3 /* Out: Line Control Register */
1559 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
1560 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
1562 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1563 +#define UART_LCR_SBC 0x40 /* Set break control */
1564 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1565 +#define UART_LCR_EPAR 0x10 /* Even parity select */
1566 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
1567 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
1568 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1569 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1570 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1571 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1573 +//#define UART_MCR 4 /* Out: Modem Control Register */
1574 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
1575 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
1576 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
1577 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
1578 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1579 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
1580 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
1581 +#define UART_MCR_RTS 0x02 /* RTS complement */
1582 +#define UART_MCR_DTR 0x01 /* DTR complement */
1584 +//#define UART_LSR 5 /* In: Line Status Register */
1585 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1586 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1587 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1588 +#define UART_LSR_FE 0x08 /* Frame error indicator */
1589 +#define UART_LSR_PE 0x04 /* Parity error indicator */
1590 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
1591 +#define UART_LSR_DR 0x01 /* Receiver data ready */
1593 +//#define UART_MSR 6 /* In: Modem Status Register */
1594 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1595 +#define UART_MSR_RI 0x40 /* Ring Indicator */
1596 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
1597 +#define UART_MSR_CTS 0x10 /* Clear to Send */
1598 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
1599 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1600 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
1601 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
1602 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1604 +//#define UART_SCR 7 /* I/O: Scratch Register */
1609 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
1610 +//#define UART_DLM 1 /* Out: Divisor Latch High */
1613 + * LCR=0xBF (or DLAB=1 for 16C660)
1615 +//#define UART_EFR 2 /* I/O: Extended Features Register */
1616 +#define UART_EFR_CTS 0x80 /* CTS flow control */
1617 +#define UART_EFR_RTS 0x40 /* RTS flow control */
1618 +#define UART_EFR_SCD 0x20 /* Special character detect */
1619 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
1621 + * the low four bits control software flow control
1625 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
1627 +#define UART_XON1 4 /* I/O: Xon character 1 */
1628 +#define UART_XON2 5 /* I/O: Xon character 2 */
1629 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
1630 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
1633 + * EFR[4]=1 MCR[6]=1, TI16C752
1635 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
1636 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
1639 + * LCR=0xBF, XR16C85x
1641 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1642 +// * In: Fifo count
1643 +// * Out: Fifo custom trigger levels */
1645 + * These are the definitions for the Programmable Trigger Register
1647 +#define UART_TRG_1 0x01
1648 +#define UART_TRG_4 0x04
1649 +#define UART_TRG_8 0x08
1650 +#define UART_TRG_16 0x10
1651 +#define UART_TRG_32 0x20
1652 +#define UART_TRG_64 0x40
1653 +#define UART_TRG_96 0x60
1654 +#define UART_TRG_120 0x78
1655 +#define UART_TRG_128 0x80
1657 +//#define UART_FCTR 1 /* Feature Control Register */
1658 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
1659 +#define UART_FCTR_RTS_4DELAY 0x01
1660 +#define UART_FCTR_RTS_6DELAY 0x02
1661 +#define UART_FCTR_RTS_8DELAY 0x03
1662 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
1663 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
1664 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
1665 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
1666 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
1667 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
1668 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
1669 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
1670 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
1673 + * LCR=0xBF, FCTR[6]=1
1675 +//#define UART_EMSR 7 /* Extended Mode Select Register */
1676 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
1677 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
1680 + * The Intel XScale on-chip UARTs define these bits
1682 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
1683 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
1684 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
1685 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
1687 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
1689 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
1690 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
1691 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
1692 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
1698 + * These register definitions are for the 16C950
1700 +#define UART_ASR 0x01 /* Additional Status Register */
1701 +#define UART_RFL 0x03 /* Receiver FIFO level */
1702 +#define UART_TFL 0x04 /* Transmitter FIFO level */
1703 +#define UART_ICR 0x05 /* Index Control Register */
1705 +/* The 16950 ICR registers */
1706 +#define UART_ACR 0x00 /* Additional Control Register */
1707 +#define UART_CPR 0x01 /* Clock Prescalar Register */
1708 +#define UART_TCR 0x02 /* Times Clock Register */
1709 +#define UART_CKS 0x03 /* Clock Select Register */
1710 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
1711 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
1712 +#define UART_FCL 0x06 /* Flow Control Level Lower */
1713 +#define UART_FCH 0x07 /* Flow Control Level Higher */
1714 +#define UART_ID1 0x08 /* ID #1 */
1715 +#define UART_ID2 0x09 /* ID #2 */
1716 +#define UART_ID3 0x0A /* ID #3 */
1717 +#define UART_REV 0x0B /* Revision */
1718 +#define UART_CSR 0x0C /* Channel Software Reset */
1719 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
1720 +#define UART_CTR 0xFF
1723 + * The 16C950 Additional Control Reigster
1725 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
1726 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
1727 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
1728 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
1729 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
1730 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
1735 + * These definitions are for the RSA-DV II/S card, from
1737 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
1740 +#define UART_RSA_BASE (-8)
1742 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
1744 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
1745 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
1746 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
1747 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
1749 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
1751 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
1752 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
1753 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
1754 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
1755 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
1757 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
1759 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
1760 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
1761 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
1762 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
1763 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
1764 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
1765 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
1766 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
1768 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
1770 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
1772 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
1774 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
1777 + * The RSA DSV/II board has two fixed clock frequencies. One is the
1778 + * standard rate, and the other is 8 times faster.
1780 +#define SERIAL_RSA_BAUD_BASE (921600)
1781 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
1784 + * Extra serial register definitions for the internal UARTs
1785 + * in TI OMAP processors.
1787 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
1788 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
1789 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
1790 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
1791 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
1792 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
1793 +#define UART_OMAP_MVER 0x14 /* Module version register */
1794 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
1795 +#define UART_OMAP_SYSS 0x16 /* System status register */
1799 +++ b/arch/mips/include/asm/rt2880/sizes.h
1802 + * This program is free software; you can redistribute it and/or modify
1803 + * it under the terms of the GNU General Public License as published by
1804 + * the Free Software Foundation; either version 2 of the License, or
1805 + * (at your option) any later version.
1807 + * This program is distributed in the hope that it will be useful,
1808 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1809 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1810 + * GNU General Public License for more details.
1812 + * You should have received a copy of the GNU General Public License
1813 + * along with this program; if not, write to the Free Software
1814 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1816 +/* DO NOT EDIT!! - this file automatically generated
1817 + * from .s file by awk -f s2h.awk
1819 +/* Size definitions
1820 + * Copyright (C) ARM Limited 1998. All rights reserved.
1824 +#define __sizes_h 1
1827 +#define SZ_1K 0x00000400
1828 +#define SZ_4K 0x00001000
1829 +#define SZ_8K 0x00002000
1830 +#define SZ_16K 0x00004000
1831 +#define SZ_64K 0x00010000
1832 +#define SZ_128K 0x00020000
1833 +#define SZ_256K 0x00040000
1834 +#define SZ_512K 0x00080000
1836 +#define SZ_1M 0x00100000
1837 +#define SZ_2M 0x00200000
1838 +#define SZ_4M 0x00400000
1839 +#define SZ_8M 0x00800000
1840 +#define SZ_16M 0x01000000
1841 +#define SZ_32M 0x02000000
1842 +#define SZ_64M 0x04000000
1843 +#define SZ_128M 0x08000000
1844 +#define SZ_256M 0x10000000
1845 +#define SZ_512M 0x20000000
1847 +#define SZ_1G 0x40000000
1848 +#define SZ_2G 0x80000000
1854 +++ b/arch/mips/include/asm/rt2880/surfboard.h
1857 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1859 + * ########################################################################
1861 + * This program is free software; you can distribute it and/or modify it
1862 + * under the terms of the GNU General Public License (Version 2) as
1863 + * published by the Free Software Foundation.
1865 + * This program is distributed in the hope it will be useful, but WITHOUT
1866 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1867 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1868 + * for more details.
1870 + * You should have received a copy of the GNU General Public License along
1871 + * with this program; if not, write to the Free Software Foundation, Inc.,
1872 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1874 + * ########################################################################
1877 +#ifndef _SURFBOARD_H
1878 +#define _SURFBOARD_H
1880 +#include <asm/addrspace.h>
1885 + * Surfboard system clock.
1886 + * This is the default value and maybe overidden by System Clock passed on the
1887 + * command line (sysclk=).
1889 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
1892 + * Surfboard UART base baud rate = System Clock / 16.
1893 + * Ex. (14.7456 MHZ / 16) = 921600
1894 + * (32.0000 MHZ / 16) = 2000000
1896 +#define SURFBOARD_BAUD_DIV (16)
1897 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
1900 + * Maximum number of IDE Controllers
1901 + * Surfboard only has one ide (ide0), so only 2 drives are
1902 + * possible. (no need to check for more hwifs.)
1904 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
1905 +#define MAX_IDE_HWIFS (2) /* Graphite board */
1907 +#define GCMP_BASE_ADDR 0x1fbf8000
1908 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
1911 + * * GIC Specific definitions
1913 +#define GIC_BASE_ADDR 0x1fbc0000
1914 +#define GIC_ADDRSPACE_SZ (128 * 1024)
1915 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
1917 +/* GIC's Nomenclature for Core Interrupt Pins */
1918 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
1919 +#define GIC_CPU_INT1 1 /* . */
1920 +#define GIC_CPU_INT2 2 /* . */
1921 +#define GIC_CPU_INT3 3 /* . */
1922 +#define GIC_CPU_INT4 4 /* . */
1923 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
1925 +#endif /* !(_SURFBOARD_H) */
1927 +++ b/arch/mips/include/asm/rt2880/surfboardint.h
1930 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1932 + * ########################################################################
1934 + * This program is free software; you can distribute it and/or modify it
1935 + * under the terms of the GNU General Public License (Version 2) as
1936 + * published by the Free Software Foundation.
1938 + * This program is distributed in the hope it will be useful, but WITHOUT
1939 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1940 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1941 + * for more details.
1943 + * You should have received a copy of the GNU General Public License along
1944 + * with this program; if not, write to the Free Software Foundation, Inc.,
1945 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1947 + * ########################################################################
1949 + * Defines for the Surfboard interrupt controller.
1952 +#ifndef _SURFBOARDINT_H
1953 +#define _SURFBOARDINT_H
1955 +/* Number of IRQ supported on hw interrupt 0. */
1956 +#if defined (CONFIG_RALINK_RT2880)
1957 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
1958 +#define SURFBOARDINT_GPIO 7 /* GPIO */
1959 +#define SURFBOARDINT_UART1 8 /* UART Lite */
1960 +#define SURFBOARDINT_UART 9 /* UART */
1961 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
1962 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
1963 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
1964 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1965 +#define SURFBOARDINT_DMA 7 /* DMA */
1966 +#define SURFBOARDINT_NAND 8 /* NAND */
1967 +#define SURFBOARDINT_PC 9 /* Performance counter */
1968 +#define SURFBOARDINT_I2S 10 /* I2S */
1969 +#define SURFBOARDINT_SDXC 14 /* SDXC */
1970 +#define SURFBOARDINT_ESW 17 /* ESW */
1971 +#define SURFBOARDINT_UART1 12 /* UART Lite */
1972 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
1973 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
1974 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
1975 +#define SURFBOARDINT_WDG 34 /* watch dog */
1976 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
1977 +#define SURFBOARDINT_PCM 36 /* PCM */
1978 +#define SURFBOARDINT_UART 37 /* UART */
1979 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
1980 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
1983 +#elif defined (CONFIG_RALINK_MT7628)
1984 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
1985 +#define SURFBOARDINT_PCM 4 /* PCM */
1986 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1987 +#define SURFBOARDINT_DMA 7 /* DMA */
1988 +#define SURFBOARDINT_PC 9 /* Performance counter */
1989 +#define SURFBOARDINT_I2S 10 /* I2S */
1990 +#define SURFBOARDINT_SPI 11 /* SPI */
1991 +#define SURFBOARDINT_AES 13 /* AES */
1992 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
1993 +#define SURFBOARDINT_SDXC 14 /* SDXC */
1994 +#define SURFBOARDINT_ESW 17 /* ESW */
1995 +#define SURFBOARDINT_USB 18 /* USB */
1996 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
1997 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
1998 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
1999 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
2000 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
2001 +#define SURFBOARDINT_WDG 23 /* WDG timer */
2002 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
2003 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
2004 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2005 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
2008 +#elif defined (CONFIG_RALINK_MT7621)
2010 +#define SURFBOARDINT_FE 3 /* FE */
2011 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
2012 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
2013 +#define SURFBOARDINT_I2C 8 /* I2C */
2014 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
2015 +#define SURFBOARDINT_PCM 10 /* PCM */
2016 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
2017 +#define SURFBOARDINT_GPIO 12 /* GPIO */
2018 +#define SURFBOARDINT_DMA 13 /* GDMA */
2019 +#define SURFBOARDINT_NAND 14 /* NAND */
2020 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
2021 +#define SURFBOARDINT_I2S 16 /* I2S */
2022 +#define SURFBOARDINT_SPI 17 /* SPI */
2023 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
2024 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
2025 +#define SURFBOARDINT_SDXC 20 /* SDXC */
2026 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
2027 +#define SURFBOARDINT_USB 22 /* USB */
2028 +#define SURFBOARDINT_ESW 31 /* Switch */
2029 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
2030 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
2031 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
2032 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
2033 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
2034 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
2035 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
2037 +#define SURFBOARDINT_WDG 29 /* WDG timer */
2038 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
2039 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
2041 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
2042 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
2043 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
2045 +#elif defined (CONFIG_RALINK_RT3883)
2046 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
2047 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2048 +#define SURFBOARDINT_DMA 7 /* DMA */
2049 +#define SURFBOARDINT_NAND 8 /* NAND */
2050 +#define SURFBOARDINT_PC 9 /* Performance counter */
2051 +#define SURFBOARDINT_I2S 10 /* I2S */
2052 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2053 +#define SURFBOARDINT_PCI 18 /* PCI */
2054 +#define SURFBOARDINT_UDEV 19 /* USB Device */
2055 +#define SURFBOARDINT_UHST 20 /* USB Host */
2056 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2057 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2058 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2059 +#define SURFBOARDINT_PCM 36 /* PCM */
2060 +#define SURFBOARDINT_UART 37 /* UART */
2063 +#define SURFBOARDINT_END 64
2064 +#define RT2880_INTERINT_START 40
2066 +/* Global interrupt bit definitions */
2067 +#define C_SURFBOARD_GLOBAL_INT 31
2068 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
2071 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
2072 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
2073 +/* end of added, bobtseng */
2076 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
2077 + * only word access are allowed.
2079 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2080 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
2081 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
2082 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
2083 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
2084 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
2085 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
2087 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
2088 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
2089 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
2090 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
2091 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
2092 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
2095 +/* bobtseng added ++, 2006.3.6. */
2096 +#define read_32bit_cp0_register(source) \
2098 + __asm__ __volatile__( \
2099 + ".set\tpush\n\t" \
2100 + ".set\treorder\n\t" \
2101 + "mfc0\t%0,"STR(source)"\n\t" \
2103 + : "=r" (__res)); \
2106 +#define write_32bit_cp0_register(register,value) \
2107 + __asm__ __volatile__( \
2108 + "mtc0\t%0,"STR(register)"\n\t" \
2112 +/* bobtseng added --, 2006.3.6. */
2114 +void surfboardint_init(void);
2115 +u32 get_surfboard_sysclk(void);
2118 +#endif /* !(_SURFBOARDINT_H) */
2120 +++ b/arch/mips/include/asm/rt2880/war.h
2123 + * This file is subject to the terms and conditions of the GNU General Public
2124 + * License. See the file "COPYING" in the main directory of this archive
2125 + * for more details.
2127 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2129 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
2130 +#define __ASM_MIPS_MACH_MIPS_WAR_H
2132 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2133 +#define R4600_V1_HIT_CACHEOP_WAR 0
2134 +#define R4600_V2_HIT_CACHEOP_WAR 0
2135 +#define R5432_CP0_INTERRUPT_WAR 0
2136 +#define BCM1250_M3_WAR 0
2137 +#define SIBYTE_1956_WAR 0
2138 +#define MIPS4K_ICACHE_REFILL_WAR 1
2139 +#define MIPS_CACHE_SYNC_WAR 1
2140 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2141 +#define RM9000_CDEX_SMP_WAR 0
2142 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
2143 +#define R10000_LLSC_WAR 0
2144 +#define MIPS34K_MISSED_ITLB_WAR 0
2146 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
2147 --- a/drivers/net/ethernet/Kconfig
2148 +++ b/drivers/net/ethernet/Kconfig
2149 @@ -135,6 +135,7 @@ source "drivers/net/ethernet/packetengin
2150 source "drivers/net/ethernet/pasemi/Kconfig"
2151 source "drivers/net/ethernet/qlogic/Kconfig"
2152 source "drivers/net/ethernet/ralink/Kconfig"
2153 +source "drivers/net/ethernet/raeth/Kconfig"
2154 source "drivers/net/ethernet/realtek/Kconfig"
2155 source "drivers/net/ethernet/renesas/Kconfig"
2156 source "drivers/net/ethernet/rdc/Kconfig"
2157 --- a/drivers/net/ethernet/Makefile
2158 +++ b/drivers/net/ethernet/Makefile
2159 @@ -57,6 +57,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packe
2160 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
2161 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
2162 obj-$(CONFIG_NET_RALINK) += ralink/
2163 +obj-$(CONFIG_RAETH) += raeth/
2164 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
2165 obj-$(CONFIG_SH_ETH) += renesas/
2166 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
2168 +++ b/drivers/net/ethernet/raeth/Kconfig
2179 + depends on SOC_MT7621
2181 +config RALINK_MT7621
2184 + depends on SOC_MT7621
2187 + tristate "Ralink GMAC"
2188 + depends on SOC_MT7621
2190 + This driver supports Ralink gigabit ethernet family of
2195 + default y if (RALINK_MT7620 || RALINK_MT7621)
2198 +config RAETH_SCATTER_GATHER_RX_DMA
2200 + default y if (RALINK_MT7620 || RALINK_MT7621)
2205 + prompt "Network BottomHalves"
2207 + default RA_NETWORK_WORKQUEUE_BH
2209 + config RA_NETWORK_TASKLET_BH
2212 + config RA_NETWORK_WORKQUEUE_BH
2220 +#config TASKLET_WORKQUEUE_SW
2221 +# bool "Tasklet and Workqueue switch"
2222 +# depends on RA_NETWORK_TASKLET_BH
2224 +config RAETH_SKB_RECYCLE_2K
2225 + bool "SKB Recycling"
2228 +config RAETH_SPECIAL_TAG
2229 + bool "Ralink Special Tag (0x810x)"
2230 + depends on RAETH && RT_3052_ESW
2232 +#config RAETH_JUMBOFRAME
2233 +# bool "Jumbo Frame up to 4K bytes"
2234 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
2236 +config RAETH_CHECKSUM_OFFLOAD
2237 + bool "TCP/UDP/IP checksum offload"
2239 + depends on RAETH && !RALINK_RT2880
2241 +#config RAETH_SW_FC
2242 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
2247 + bool "32bytes TX/RX description"
2249 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
2251 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
2254 + bool "LRO (Large Receive Offload )"
2256 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
2258 +config RAETH_HW_VLAN_TX
2259 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
2260 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
2262 + Please disable HW_VLAN_TX if you need double vlan
2264 +config RAETH_HW_VLAN_RX
2265 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
2266 + depends on RAETH && RALINK_MT7621
2268 + Please disable HW_VLAN_RX if you need double vlan
2271 + bool "TSOV4 (Tcp Segmentaton Offload)"
2272 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
2275 + bool "TSOV6 (Tcp Segmentaton Offload)"
2276 + depends on RAETH_TSO
2278 +config RAETH_RW_PDMAPTR_FROM_VAR
2280 + default y if RALINK_RT6855A || RALINK_MT7620
2284 +# bool "QoS Feature"
2285 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
2289 + depends on RAETH_QOS
2290 + default DSCP_QOS_DSCP
2292 +config RAETH_QOS_DSCP_BASED
2294 + depends on RAETH_QOS
2296 +config RAETH_QOS_VPRI_BASED
2298 + depends on RAETH_QOS
2303 + bool "Choose QDMA instead PDMA"
2305 + depends on RAETH && RALINK_MT7621
2308 + prompt "GMAC is connected to"
2310 + default GE1_RGMII_FORCE_1000
2312 +config GE1_MII_FORCE_100
2313 + bool "MII_FORCE_100 (10/100M Switch)"
2314 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2317 + bool "MII_AN (100Phy)"
2318 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2320 +config GE1_RVMII_FORCE_100
2321 + bool "RvMII_FORCE_100 (CPU)"
2322 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2324 +config GE1_RGMII_FORCE_1000
2325 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2326 + depends on (RALINK_RT2880 || RALINK_RT3883)
2329 +config GE1_RGMII_FORCE_1000
2330 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2331 + depends on (RALINK_MT7621)
2332 + select RT_3052_ESW
2334 +config GE1_TRGMII_FORCE_1200
2335 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
2336 + depends on (RALINK_MT7621)
2337 + select RT_3052_ESW
2339 +config GE1_RGMII_AN
2340 + bool "RGMII_AN (GigaPhy)"
2341 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2343 +config GE1_RGMII_NONE
2344 + bool "NONE (NO CONNECT)"
2345 + depends on (RALINK_MT7621)
2350 + bool "Ralink Embedded Switch"
2352 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
2354 +config LAN_WAN_SUPPORT
2355 + bool "LAN/WAN Partition"
2356 + depends on RAETH_ROUTER || RT_3052_ESW
2359 + prompt "Switch Board Layout Type"
2360 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
2370 +config RALINK_VISTA_BASIC
2371 + bool 'Vista Basic Logo for IC+ 175C'
2372 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
2374 +config ESW_DOUBLE_VLAN_TAG
2376 + default y if RT_3052_ESW
2378 +config RAETH_HAS_PORT4
2379 + bool "Port 4 Support"
2380 + depends on RAETH && RALINK_MT7620
2382 + prompt "Target Mode"
2383 + depends on RAETH_HAS_PORT4
2384 + default P4_RGMII_TO_MAC_MODE
2386 + config P4_MAC_TO_PHY_MODE
2387 + bool "Giga_Phy (RGMII)"
2388 + config GE_RGMII_MT7530_P0_AN
2389 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
2390 + config GE_RGMII_MT7530_P4_AN
2391 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
2392 + config P4_RGMII_TO_MAC_MODE
2393 + bool "Giga_SW/iNIC (RGMII)"
2394 + config P4_MII_TO_MAC_MODE
2395 + bool "External_CPU (MII_RvMII)"
2396 + config P4_RMII_TO_MAC_MODE
2397 + bool "External_CPU (RvMII_MII)"
2400 +config MAC_TO_GIGAPHY_MODE_ADDR2
2401 + hex "Port4 Phy Address"
2403 + depends on P4_MAC_TO_PHY_MODE
2405 +config RAETH_HAS_PORT5
2406 + bool "Port 5 Support"
2407 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
2409 + prompt "Target Mode"
2410 + depends on RAETH_HAS_PORT5
2411 + default P5_RGMII_TO_MAC_MODE
2413 + config P5_MAC_TO_PHY_MODE
2414 + bool "Giga_Phy (RGMII)"
2415 + config P5_RGMII_TO_MAC_MODE
2416 + bool "Giga_SW/iNIC (RGMII)"
2417 + config P5_RGMII_TO_MT7530_MODE
2418 + bool "MT7530 Giga_SW (RGMII)"
2419 + depends on RALINK_MT7620
2420 + config P5_MII_TO_MAC_MODE
2421 + bool "External_CPU (MII_RvMII)"
2422 + config P5_RMII_TO_MAC_MODE
2423 + bool "External_CPU (RvMII_MII)"
2426 +config MAC_TO_GIGAPHY_MODE_ADDR
2427 + hex "GE1 Phy Address"
2429 + depends on GE1_MII_AN || GE1_RGMII_AN
2431 +config MAC_TO_GIGAPHY_MODE_ADDR
2432 + hex "Port5 Phy Address"
2434 + depends on P5_MAC_TO_PHY_MODE
2437 + bool "GMAC2 Support"
2438 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
2441 + prompt "GMAC2 is connected to"
2442 + depends on RAETH_GMAC2
2443 + default GE2_RGMII_AN
2445 +config GE2_MII_FORCE_100
2446 + bool "MII_FORCE_100 (10/100M Switch)"
2447 + depends on RAETH_GMAC2
2450 + bool "MII_AN (100Phy)"
2451 + depends on RAETH_GMAC2
2453 +config GE2_RVMII_FORCE_100
2454 + bool "RvMII_FORCE_100 (CPU)"
2455 + depends on RAETH_GMAC2
2457 +config GE2_RGMII_FORCE_1000
2458 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2459 + depends on RAETH_GMAC2
2462 +config GE2_RGMII_AN
2463 + bool "RGMII_AN (GigaPhy)"
2464 + depends on RAETH_GMAC2
2466 +config GE2_INTERNAL_GPHY
2467 + bool "Internal GigaPHY"
2468 + depends on RAETH_GMAC2
2469 + select LAN_WAN_SUPPORT
2473 +config GE_RGMII_INTERNAL_P0_AN
2475 + depends on GE2_INTERNAL_GPHY
2476 + default y if WAN_AT_P0
2478 +config GE_RGMII_INTERNAL_P4_AN
2480 + depends on GE2_INTERNAL_GPHY
2481 + default y if WAN_AT_P4
2483 +config MAC_TO_GIGAPHY_MODE_ADDR2
2485 + default 0 if GE_RGMII_INTERNAL_P0_AN
2486 + default 4 if GE_RGMII_INTERNAL_P4_AN
2487 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
2489 +config MAC_TO_GIGAPHY_MODE_ADDR2
2490 + hex "GE2 Phy Address"
2492 + depends on GE2_MII_AN || GE2_RGMII_AN
2495 +config RAETH_ROUTER
2497 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
2500 +config MAC_TO_MAC_MODE
2502 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
2503 +depends on (RALINK_RT2880 || RALINK_RT3883)
2508 +default y if GE1_RGMII_AN || GE2_RGMII_AN
2513 +default y if GE1_MII_AN || GE2_MII_AN
2515 +++ b/drivers/net/ethernet/raeth/Makefile
2517 +obj-$(CONFIG_RAETH) += raeth.o
2518 +raeth-objs := ra_mac.o mii_mgr.o
2519 +raeth-objs += raether_pdma.o
2520 +EXTRA_CFLAGS += -DWORKQUEUE_BH
2521 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
2523 +raeth-objs += raether.o
2525 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2528 +Ethtool readme for selecting different PHY address.
2530 +Before doing any ethtool command you should make sure the current PHY
2531 +address is expected. The default PHY address is 1(port 1).
2533 +You can change current PHY address to X(0~4) by doing follow command:
2534 +# echo X > /proc/rt2880/gmac
2536 +Ethtool command also would show the current PHY address as following.
2540 + Supported ports: [ TP MII ]
2541 + Supported link modes: 10baseT/Half 10baseT/Full
2542 + 100baseT/Half 100baseT/Full
2543 + Supports auto-negotiation: Yes
2544 + Advertised link modes: 10baseT/Half 10baseT/Full
2545 + 100baseT/Half 100baseT/Full
2546 + Advertised auto-negotiation: No
2551 + Transceiver: internal
2552 + Auto-negotiation: off
2553 + Current message level: 0x00000000 (0)
2557 +The "PHYAD" field shows the current PHY address.
2563 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2567 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2572 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2574 +#include <linux/module.h>
2575 +#include <linux/version.h>
2576 +#include <linux/netdevice.h>
2578 +#include <linux/kernel.h>
2579 +#include <linux/sched.h>
2580 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2581 +#include <asm/rt2880/rt_mmap.h>
2584 +#include "ra2882ethreg.h"
2585 +#include "raether.h"
2588 +#define PHY_CONTROL_0 0x0004
2589 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2590 +#define enable_mdio(x)
2593 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2595 + u32 volatile status = 0;
2597 + unsigned long volatile t_start = jiffies;
2598 + u32 volatile data = 0;
2600 + /* We enable mdio gpio purpose register, and disable it when exit. */
2603 + // make sure previous read operation is complete
2605 + // 0 : Read/write operation complete
2606 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2610 + else if (time_after(jiffies, t_start + 5*HZ)) {
2612 + printk("\n MDIO Read operation is ongoing !!\n");
2617 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
2618 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2620 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2621 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2624 + // make sure read operation is complete
2625 + t_start = jiffies;
2627 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
2628 + status = sysRegRead(MDIO_PHY_CONTROL_0);
2629 + *read_data = (u32)(status & 0x0000FFFF);
2634 + else if (time_after(jiffies, t_start+5*HZ)) {
2636 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
2642 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2644 + unsigned long volatile t_start=jiffies;
2645 + u32 volatile data;
2649 + // make sure previous write operation is complete
2651 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2655 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2657 + printk("\n MDIO Write operation ongoing\n");
2661 + /*add 1 us delay to make sequencial write more robus*/
2664 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
2665 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2667 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
2668 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2670 + t_start = jiffies;
2672 + // make sure write operation is complete
2674 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
2679 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2681 + printk("\n MDIO Write operation Time Out\n");
2687 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2693 + //phase1: write page address phase
2694 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
2695 + //phase2: write address & read low word phase
2696 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
2697 + //phase3: write address & read high word phase
2698 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
2699 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
2706 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
2714 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2716 + if(phy_addr == 31)
2718 + //phase1: write page address phase
2719 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
2720 + //phase2: write address & read low word phase
2721 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
2722 + //phase3: write address & read high word phase
2723 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
2730 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
2738 +EXPORT_SYMBOL(mii_mgr_write);
2739 +EXPORT_SYMBOL(mii_mgr_read);
2741 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
2743 +#ifndef RA2882ETHREG_H
2744 +#define RA2882ETHREG_H
2746 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
2747 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
2749 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2750 +#include <asm/rt2880/rt_mmap.h>
2752 +#include "raether.h"
2754 +#ifdef WORKQUEUE_BH
2755 +#include <linux/workqueue.h>
2756 +#endif // WORKQUEUE_BH //
2757 +#ifdef CONFIG_RAETH_LRO
2758 +#include <linux/inet_lro.h>
2761 +#define MAX_PACKET_SIZE 1514
2762 +#define MIN_PACKET_SIZE 60
2764 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
2766 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
2767 +#define BIT(x) ((1 << x))
2769 +#define ETHER_ADDR_LEN 6
2771 +/* Phy Vender ID list */
2773 +#define EV_ICPLUS_PHY_ID0 0x0243
2774 +#define EV_ICPLUS_PHY_ID1 0x0D90
2775 +#define EV_MARVELL_PHY_ID0 0x0141
2776 +#define EV_MARVELL_PHY_ID1 0x0CC2
2777 +#define EV_VTSS_PHY_ID0 0x0007
2778 +#define EV_VTSS_PHY_ID1 0x0421
2783 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2784 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2786 +#define RX_COHERENT BIT(31)
2787 +#define RX_DLY_INT BIT(30)
2788 +#define TX_COHERENT BIT(29)
2789 +#define TX_DLY_INT BIT(28)
2791 +#define RX_DONE_INT1 BIT(17)
2792 +#define RX_DONE_INT0 BIT(16)
2794 +#define TX_DONE_INT3 BIT(3)
2795 +#define TX_DONE_INT2 BIT(2)
2796 +#define TX_DONE_INT1 BIT(1)
2797 +#define TX_DONE_INT0 BIT(0)
2799 +#if defined (CONFIG_RALINK_MT7621)
2800 +#define RLS_COHERENT BIT(29)
2801 +#define RLS_DLY_INT BIT(28)
2802 +#define RLS_DONE_INT BIT(0)
2806 +//#define CNT_PPE_AF BIT(31)
2807 +//#define CNT_GDM_AF BIT(29)
2808 +#define PSE_P2_FC BIT(26)
2809 +#define GDM_CRC_DROP BIT(25)
2810 +#define PSE_BUF_DROP BIT(24)
2811 +#define GDM_OTHER_DROP BIT(23)
2812 +#define PSE_P1_FC BIT(22)
2813 +#define PSE_P0_FC BIT(21)
2814 +#define PSE_FQ_EMPTY BIT(20)
2815 +#define GE1_STA_CHG BIT(18)
2816 +#define TX_COHERENT BIT(17)
2817 +#define RX_COHERENT BIT(16)
2819 +#define TX_DONE_INT3 BIT(11)
2820 +#define TX_DONE_INT2 BIT(10)
2821 +#define TX_DONE_INT1 BIT(9)
2822 +#define TX_DONE_INT0 BIT(8)
2823 +#define RX_DONE_INT1 RX_DONE_INT0
2824 +#define RX_DONE_INT0 BIT(2)
2825 +#define TX_DLY_INT BIT(1)
2826 +#define RX_DLY_INT BIT(0)
2829 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
2830 + TX_DONE_INT1 | TX_DONE_INT0 | \
2833 +#if defined (CONFIG_RALINK_MT7621)
2834 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
2835 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
2837 +#define NUM_QDMA_PAGE 256
2838 +#define QDMA_PAGE_SIZE 2048
2843 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2844 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
2845 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
2846 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
2847 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
2848 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
2849 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
2850 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
2851 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
2852 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
2853 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
2854 +#define PORT_ST_CHG BIT(26) //Port status change
2855 +#define UNSECURED_ALERT BIT(27) //Intruder alert
2856 +#define ABNORMAL_ALERT BIT(28) //Abnormal
2858 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
2859 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
2860 +#define ESW_INT_ALL (PORT_ST_CHG)
2862 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2863 + defined (CONFIG_RALINK_MT7620)
2864 +#define MIB_INT BIT(25)
2865 +#define ACL_INT BIT(24)
2866 +#define P5_LINK_CH BIT(5)
2867 +#define P4_LINK_CH BIT(4)
2868 +#define P3_LINK_CH BIT(3)
2869 +#define P2_LINK_CH BIT(2)
2870 +#define P1_LINK_CH BIT(1)
2871 +#define P0_LINK_CH BIT(0)
2873 +#define RX_GOCT_CNT BIT(4)
2874 +#define RX_GOOD_CNT BIT(6)
2875 +#define TX_GOCT_CNT BIT(17)
2876 +#define TX_GOOD_CNT BIT(19)
2878 +#define MSK_RX_GOCT_CNT BIT(4)
2879 +#define MSK_RX_GOOD_CNT BIT(6)
2880 +#define MSK_TX_GOCT_CNT BIT(17)
2881 +#define MSK_TX_GOOD_CNT BIT(19)
2882 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
2883 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
2886 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
2887 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
2888 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
2889 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
2890 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
2891 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
2892 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
2893 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
2894 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
2895 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
2896 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
2897 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
2898 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
2899 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
2900 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
2901 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
2902 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
2903 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
2905 +#if defined (CONFIG_RALINK_MT7620)
2906 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
2907 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
2911 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
2913 +#elif defined (CONFIG_RALINK_MT7621)
2915 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
2917 +#define P5_LINK_CH BIT(5)
2918 +#define P4_LINK_CH BIT(4)
2919 +#define P3_LINK_CH BIT(3)
2920 +#define P2_LINK_CH BIT(2)
2921 +#define P1_LINK_CH BIT(1)
2922 +#define P0_LINK_CH BIT(0)
2925 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
2927 +#define RX_BUF_ALLOC_SIZE 2000
2928 +#define FASTPATH_HEADROOM 64
2930 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
2932 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
2933 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
2934 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
2936 +#ifdef CONFIG_PSEUDO_SUPPORT
2937 +typedef struct _PSEUDO_ADAPTER {
2938 + struct net_device *RaethDev;
2939 + struct net_device *PseudoDev;
2940 + struct net_device_stats stat;
2941 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
2942 + struct mii_if_info mii_info;
2945 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
2947 +#define MAX_PSEUDO_ENTRY 1
2952 +/* Register Categories Definition */
2953 +#define RAFRAMEENGINE_OFFSET 0x0000
2954 +#define RAGDMA_OFFSET 0x0020
2955 +#define RAPSE_OFFSET 0x0040
2956 +#define RAGDMA2_OFFSET 0x0060
2957 +#define RACDMA_OFFSET 0x0080
2958 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2959 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2961 +#define RAPDMA_OFFSET 0x0800
2962 +#define SDM_OFFSET 0x0C00
2964 +#define RAPDMA_OFFSET 0x0100
2966 +#define RAPPE_OFFSET 0x0200
2967 +#define RACMTABLE_OFFSET 0x0400
2968 +#define RAPOLICYTABLE_OFFSET 0x1000
2971 +/* Register Map Detail */
2973 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
2975 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2978 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
2979 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
2980 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
2981 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
2983 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
2984 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
2985 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
2986 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
2988 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
2989 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
2990 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
2991 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
2993 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
2994 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
2995 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
2996 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
2998 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
2999 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3000 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3001 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3003 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3004 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3005 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3006 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3008 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3009 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3010 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3011 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3012 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3013 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3014 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3015 +#define FE_INT_STATUS (INT_STATUS)
3016 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3017 +#define FE_INT_ENABLE (INT_MASK)
3018 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3019 +#define PDMA_SCH_CFG (PDMA_WRR)
3021 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3022 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3023 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3024 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3025 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3026 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3027 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3028 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3029 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3030 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3032 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3033 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3035 +/* Old FE with New PDMA */
3036 +#define PDMA_RELATED 0x0800
3038 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3039 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3040 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3041 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3043 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3044 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3045 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3046 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3048 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3049 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3050 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3051 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3053 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3054 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3055 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3056 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3058 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3059 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3060 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3061 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3063 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3064 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3065 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3066 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3068 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3069 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3070 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3071 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3072 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3073 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3074 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3075 +#define FE_INT_STATUS (INT_STATUS)
3076 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3077 +#define FE_INT_ENABLE (INT_MASK)
3078 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3079 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3081 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3082 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3083 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3084 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3085 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3086 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3088 +#if defined (CONFIG_RALINK_MT7620)
3089 +#define GDMA1_RELATED 0x0600
3090 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3091 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3092 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3093 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3094 +#elif defined (CONFIG_RALINK_MT7621)
3095 +#define GDMA1_RELATED 0x0500
3096 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3097 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3098 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3099 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3101 +#define GDMA2_RELATED 0x1500
3102 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3103 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3104 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3105 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3107 +#define GDMA1_RELATED 0x0020
3108 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3109 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3110 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3111 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3112 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
3114 +#define GDMA2_RELATED 0x0060
3115 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3116 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3117 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3118 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3119 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
3122 +#if defined (CONFIG_RALINK_MT7620)
3123 +#define PSE_RELATED 0x0500
3124 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3125 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3126 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3128 +#define PSE_RELATED 0x0040
3129 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3130 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3131 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3132 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
3133 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
3134 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
3135 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
3136 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
3140 +#if defined (CONFIG_RALINK_MT7620)
3141 +#define CDMA_RELATED 0x0400
3142 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3143 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
3144 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
3145 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
3146 +#elif defined (CONFIG_RALINK_MT7621)
3147 +#define CDMA_RELATED 0x0400
3148 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
3149 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3150 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3152 +#define CDMA_RELATED 0x0080
3153 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3154 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3155 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
3156 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
3157 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
3160 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
3163 +#if defined (CONFIG_RALINK_MT7621)
3164 +/*kurtis: add QDMA define*/
3166 +#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
3167 +#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
3169 +#define QDMA_RELATED 0x1800
3170 +#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
3171 +#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
3172 +#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
3173 +#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
3174 +#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
3175 +#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
3176 +#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
3177 +#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
3178 +#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
3179 +#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
3180 +#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
3181 +#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
3182 +#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
3183 +#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
3184 +#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
3185 +#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
3186 +#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
3187 +#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
3188 +#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
3189 +#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
3190 +#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
3191 +#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
3192 +#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
3193 +#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
3194 +#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
3195 +#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
3196 +#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
3197 +#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
3198 +#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
3199 +#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
3200 +#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
3201 +#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
3202 +#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
3203 +#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
3204 +#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
3205 +#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
3206 +#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
3207 +#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
3208 +#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
3209 +#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
3210 +#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
3211 +#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
3212 +#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
3213 +#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
3214 +#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
3215 +#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
3216 +#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
3217 +#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
3218 +#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
3219 +#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
3220 +#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
3221 +#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
3222 +#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
3223 +#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
3224 +#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
3225 +#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
3226 +#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
3227 +#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
3228 +#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
3229 +#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
3230 +#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
3231 +#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
3232 +#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
3233 +#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
3234 +#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
3235 +#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
3236 +#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
3237 +#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
3238 +#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
3239 +#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
3240 +#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
3241 +#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
3242 +#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
3243 +#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
3244 +#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
3245 +#define QDMA_RST_CFG (QDMA_RST_IDX)
3246 +#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
3247 +#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
3248 +#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
3249 +#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
3250 +#define QFE_INT_STATUS (QDMA_INT_STS)
3251 +#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
3252 +#define QFE_INT_ENABLE (QDMA_INT_MASK)
3253 +#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
3254 +#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
3255 +#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
3256 +#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
3257 +#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
3258 +#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
3259 +#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
3260 +#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
3261 +#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
3262 +#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
3263 +#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
3264 +#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
3265 +#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
3266 +#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
3267 +#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
3268 +#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
3269 +#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
3270 +#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
3271 +#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
3272 +#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
3273 +#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
3274 +#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
3275 +#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
3276 +#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
3277 +#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
3278 +#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
3279 +#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
3280 +#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
3281 +#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
3284 +#endif/*MT7621 QDMA*/
3288 +/* 1. Frame Engine Global Registers */
3289 +#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
3290 +#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
3291 +#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
3292 +#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
3293 +#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
3294 +#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
3295 +#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
3296 +#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
3299 +/* 2. GDMA Registers */
3300 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
3301 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
3302 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
3303 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
3304 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
3306 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
3307 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
3308 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
3309 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
3310 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
3313 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
3314 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
3315 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
3316 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
3317 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0)
3320 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
3321 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
3322 +/* skip ppoe sid and vlan id definition */
3326 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
3327 +#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
3328 +#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
3330 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
3332 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
3333 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
3334 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
3335 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
3337 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
3338 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
3339 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
3340 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
3342 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3343 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3344 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3345 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3347 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
3348 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
3349 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
3350 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
3352 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
3353 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
3354 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
3355 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
3357 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3358 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3359 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3360 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3364 +#define DELAY_INT_INIT 0x84048404
3365 +#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
3368 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3370 +/* 6. Counter and Meter Table */
3371 +#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
3372 +#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
3375 +#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
3377 +#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
3379 +#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
3380 +#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
3381 +#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
3382 +#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
3384 +/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
3385 +#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
3386 +#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
3387 +#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
3388 +#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
3389 +#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
3390 +#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
3391 +#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
3392 +#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
3397 +/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
3398 +#define PORT0_PKCOUNT (0xb01100e8)
3399 +#define PORT1_PKCOUNT (0xb01100ec)
3400 +#define PORT2_PKCOUNT (0xb01100f0)
3401 +#define PORT3_PKCOUNT (0xb01100f4)
3402 +#define PORT4_PKCOUNT (0xb01100f8)
3403 +#define PORT5_PKCOUNT (0xb01100fc)
3407 +#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
3410 +#define sysRegRead(phys) \
3411 + (*(volatile unsigned int *)PHYS_TO_K1(phys))
3413 +#define sysRegWrite(phys, val) \
3414 + ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
3416 +#define u_long unsigned long
3417 +#define u32 unsigned int
3418 +#define u16 unsigned short
3421 +/* ====================================== */
3422 +#define GDM1_DISPAD BIT(18)
3423 +#define GDM1_DISCRC BIT(17)
3425 +//GDMA1 uni-cast frames destination port
3426 +#define GDM1_ICS_EN (0x1 << 22)
3427 +#define GDM1_TCS_EN (0x1 << 21)
3428 +#define GDM1_UCS_EN (0x1 << 20)
3429 +#define GDM1_JMB_EN (0x1 << 19)
3430 +#define GDM1_STRPCRC (0x1 << 16)
3431 +#define GDM1_UFRC_P_CPU (0 << 12)
3432 +#if defined (CONFIG_RALINK_MT7621)
3433 +#define GDM1_UFRC_P_PPE (4 << 12)
3435 +#define GDM1_UFRC_P_PPE (6 << 12)
3438 +//GDMA1 broad-cast MAC address frames
3439 +#define GDM1_BFRC_P_CPU (0 << 8)
3440 +#if defined (CONFIG_RALINK_MT7621)
3441 +#define GDM1_BFRC_P_PPE (4 << 8)
3443 +#define GDM1_BFRC_P_PPE (6 << 8)
3446 +//GDMA1 multi-cast MAC address frames
3447 +#define GDM1_MFRC_P_CPU (0 << 4)
3448 +#if defined (CONFIG_RALINK_MT7621)
3449 +#define GDM1_MFRC_P_PPE (4 << 4)
3451 +#define GDM1_MFRC_P_PPE (6 << 4)
3454 +//GDMA1 other MAC address frames destination port
3455 +#define GDM1_OFRC_P_CPU (0 << 0)
3456 +#if defined (CONFIG_RALINK_MT7621)
3457 +#define GDM1_OFRC_P_PPE (4 << 0)
3459 +#define GDM1_OFRC_P_PPE (6 << 0)
3462 +#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3463 +/* checksum generator registers are removed */
3464 +#define ICS_GEN_EN (0 << 2)
3465 +#define UCS_GEN_EN (0 << 1)
3466 +#define TCS_GEN_EN (0 << 0)
3468 +#define ICS_GEN_EN (1 << 2)
3469 +#define UCS_GEN_EN (1 << 1)
3470 +#define TCS_GEN_EN (1 << 0)
3474 +#define MDIO_CFG_GP1_FC_TX (1 << 11)
3475 +#define MDIO_CFG_GP1_FC_RX (1 << 10)
3477 +/* ====================================== */
3478 +/* ====================================== */
3479 +#define GP1_LNK_DWN BIT(9)
3480 +#define GP1_AN_FAIL BIT(8)
3481 +/* ====================================== */
3482 +/* ====================================== */
3483 +#define PSE_RESET BIT(0)
3484 +/* ====================================== */
3485 +#define PST_DRX_IDX1 BIT(17)
3486 +#define PST_DRX_IDX0 BIT(16)
3487 +#define PST_DTX_IDX3 BIT(3)
3488 +#define PST_DTX_IDX2 BIT(2)
3489 +#define PST_DTX_IDX1 BIT(1)
3490 +#define PST_DTX_IDX0 BIT(0)
3492 +#define RX_2B_OFFSET BIT(31)
3493 +#define DESC_32B_EN BIT(8)
3494 +#define TX_WB_DDONE BIT(6)
3495 +#define RX_DMA_BUSY BIT(3)
3496 +#define TX_DMA_BUSY BIT(1)
3497 +#define RX_DMA_EN BIT(2)
3498 +#define TX_DMA_EN BIT(0)
3500 +#define PDMA_BT_SIZE_4DWORDS (0<<4)
3501 +#define PDMA_BT_SIZE_8DWORDS (1<<4)
3502 +#define PDMA_BT_SIZE_16DWORDS (2<<4)
3503 +#define PDMA_BT_SIZE_32DWORDS (3<<4)
3508 +#define MACCFG_RXEN (1<<2)
3509 +#define MACCFG_TXEN (1<<3)
3510 +#define MACCFG_PROMISC (1<<18)
3511 +#define MACCFG_RXMCAST (1<<19)
3512 +#define MACCFG_FDUPLEX (1<<20)
3513 +#define MACCFG_PORTSEL (1<<27)
3514 +#define MACCFG_HBEATDIS (1<<28)
3517 +#define DMACTL_SR (1<<1) /* Start/Stop Receive */
3518 +#define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */
3520 +#define DMACFG_SWR (1<<0) /* Software Reset */
3521 +#define DMACFG_BURST32 (32<<8)
3523 +#define DMASTAT_TS 0x00700000 /* Transmit Process State */
3524 +#define DMASTAT_RS 0x000e0000 /* Receive Process State */
3526 +#define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
3530 +/* Descriptor bits.
3532 +#define R_OWN 0x80000000 /* Own Bit */
3533 +#define RD_RER 0x02000000 /* Receive End Of Ring */
3534 +#define RD_LS 0x00000100 /* Last Descriptor */
3535 +#define RD_ES 0x00008000 /* Error Summary */
3536 +#define RD_CHAIN 0x01000000 /* Chained */
3539 +#define T_OWN 0x80000000 /* Own Bit */
3540 +#define TD_ES 0x00008000 /* Error Summary */
3543 +#define TD_LS 0x40000000 /* Last Segment */
3544 +#define TD_FS 0x20000000 /* First Segment */
3545 +#define TD_TER 0x08000000 /* Transmit End Of Ring */
3546 +#define TD_CHAIN 0x01000000 /* Chained */
3549 +#define TD_SET 0x08000000 /* Setup Packet */
3552 +#define POLL_DEMAND 1
3554 +#define RSTCTL (0x34)
3555 +#define RSTCTL_RSTENET1 (1<<19)
3556 +#define RSTCTL_RSTENET2 (1<<20)
3558 +#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
3559 +#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
3560 +#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
3561 +#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
3563 +// Define Whole FE Reset Register
3564 +#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
3566 +/*=========================================
3567 + PDMA RX Descriptor Format define
3568 +=========================================*/
3570 +//-------------------------------------------------
3571 +typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
3573 +struct _PDMA_RXD_INFO1_
3575 + unsigned int PDP0;
3577 +//-------------------------------------------------
3578 +typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
3580 +struct _PDMA_RXD_INFO2_
3582 + unsigned int PLEN1 : 14;
3583 + unsigned int LS1 : 1;
3584 + unsigned int TAG : 1;
3585 + unsigned int PLEN0 : 14;
3586 + unsigned int LS0 : 1;
3587 + unsigned int DDONE_bit : 1;
3589 +//-------------------------------------------------
3590 +typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
3592 +struct _PDMA_RXD_INFO3_
3594 + unsigned int VID:16;
3595 + unsigned int TPID:16;
3597 +//-------------------------------------------------
3598 +typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
3600 +struct _PDMA_RXD_INFO4_
3602 +#if defined (CONFIG_RALINK_MT7620)
3603 + unsigned int FOE_Entry : 14;
3604 + unsigned int CRSN : 5;
3605 + unsigned int SPORT : 3;
3606 + unsigned int L4F : 1;
3607 + unsigned int L4VLD : 1;
3608 + unsigned int TACK : 1;
3609 + unsigned int IP4F : 1;
3610 + unsigned int IP4 : 1;
3611 + unsigned int IP6 : 1;
3612 + unsigned int UN_USE1 : 4;
3613 +#elif defined (CONFIG_RALINK_MT7621)
3614 + unsigned int FOE_Entry : 14;
3615 + unsigned int CRSN : 5;
3616 + unsigned int SP : 4;
3617 + unsigned int L4F : 1;
3618 + unsigned int L4VLD : 1;
3619 + unsigned int TACK : 1;
3620 + unsigned int IP4F : 1;
3621 + unsigned int IP4 : 1;
3622 + unsigned int IP6 : 1;
3623 + unsigned int UN_USE1 : 3;
3625 + unsigned int FOE_Entry : 14;
3626 + unsigned int FVLD : 1;
3627 + unsigned int UN_USE1 : 1;
3628 + unsigned int AI : 8;
3629 + unsigned int SP : 3;
3630 + unsigned int AIS : 1;
3631 + unsigned int L4F : 1;
3632 + unsigned int IPF : 1;
3633 + unsigned int L4FVLD_bit : 1;
3634 + unsigned int IPFVLD_bit : 1;
3639 +struct PDMA_rxdesc {
3640 + PDMA_RXD_INFO1_T rxd_info1;
3641 + PDMA_RXD_INFO2_T rxd_info2;
3642 + PDMA_RXD_INFO3_T rxd_info3;
3643 + PDMA_RXD_INFO4_T rxd_info4;
3644 +#ifdef CONFIG_32B_DESC
3645 + unsigned int rxd_info5;
3646 + unsigned int rxd_info6;
3647 + unsigned int rxd_info7;
3648 + unsigned int rxd_info8;
3652 +/*=========================================
3653 + PDMA TX Descriptor Format define
3654 +=========================================*/
3655 +//-------------------------------------------------
3656 +typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
3658 +struct _PDMA_TXD_INFO1_
3660 + unsigned int SDP0;
3662 +//-------------------------------------------------
3663 +typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
3665 +struct _PDMA_TXD_INFO2_
3667 + unsigned int SDL1 : 14;
3668 + unsigned int LS1_bit : 1;
3669 + unsigned int BURST_bit : 1;
3670 + unsigned int SDL0 : 14;
3671 + unsigned int LS0_bit : 1;
3672 + unsigned int DDONE_bit : 1;
3674 +//-------------------------------------------------
3675 +typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
3677 +struct _PDMA_TXD_INFO3_
3679 + unsigned int SDP1;
3681 +//-------------------------------------------------
3682 +typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
3684 +struct _PDMA_TXD_INFO4_
3686 +#if defined (CONFIG_RALINK_MT7620)
3687 + unsigned int VPRI_VIDX : 8;
3688 + unsigned int SIDX : 4;
3689 + unsigned int INSP : 1;
3690 + unsigned int RESV : 2;
3691 + unsigned int UDF : 5;
3692 + unsigned int FP_BMAP : 8;
3693 + unsigned int TSO : 1;
3694 + unsigned int TUI_CO : 3;
3695 +#elif defined (CONFIG_RALINK_MT7621)
3696 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3697 + unsigned int RESV : 2;
3698 + unsigned int UDF : 6;
3699 + unsigned int FPORT : 3;
3700 + unsigned int TSO : 1;
3701 + unsigned int TUI_CO : 3;
3703 + unsigned int VPRI_VIDX : 8;
3704 + unsigned int SIDX : 4;
3705 + unsigned int INSP : 1;
3706 + unsigned int RESV : 1;
3707 + unsigned int UN_USE3 : 2;
3708 + unsigned int QN : 3;
3709 + unsigned int UN_USE2 : 1;
3710 + unsigned int UDF : 4;
3711 + unsigned int PN : 3;
3712 + unsigned int UN_USE1 : 1;
3713 + unsigned int TSO : 1;
3714 + unsigned int TUI_CO : 3;
3719 +struct PDMA_txdesc {
3720 + PDMA_TXD_INFO1_T txd_info1;
3721 + PDMA_TXD_INFO2_T txd_info2;
3722 + PDMA_TXD_INFO3_T txd_info3;
3723 + PDMA_TXD_INFO4_T txd_info4;
3724 +#ifdef CONFIG_32B_DESC
3725 + unsigned int txd_info5;
3726 + unsigned int txd_info6;
3727 + unsigned int txd_info7;
3728 + unsigned int txd_info8;
3733 +#if defined (CONFIG_RALINK_MT7621)
3734 +/*=========================================
3735 + QDMA TX Descriptor Format define
3736 +=========================================*/
3737 +//-------------------------------------------------
3738 +typedef struct _QDMA_TXD_INFO1_ QDMA_TXD_INFO1_T;
3740 +struct _QDMA_TXD_INFO1_
3744 +//-------------------------------------------------
3745 +typedef struct _QDMA_TXD_INFO2_ QDMA_TXD_INFO2_T;
3747 +struct _QDMA_TXD_INFO2_
3751 +//-------------------------------------------------
3752 +typedef struct _QDMA_TXD_INFO3_ QDMA_TXD_INFO3_T;
3754 +struct _QDMA_TXD_INFO3_
3756 + unsigned int QID : 4;
3757 + unsigned int RESV : 10;
3758 + unsigned int SWC_bit : 1;
3759 + unsigned int BURST_bit : 1;
3760 + unsigned int SDL : 14;
3761 + unsigned int LS_bit : 1;
3762 + unsigned int OWN_bit : 1;
3764 +//-------------------------------------------------
3765 +typedef struct _QDMA_TXD_INFO4_ QDMA_TXD_INFO4_T;
3767 +struct _QDMA_TXD_INFO4_
3769 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3770 + unsigned int RESV : 2;
3771 + unsigned int UDF : 6;
3772 + unsigned int FPORT : 3;
3773 + unsigned int TSO : 1;
3774 + unsigned int TUI_CO : 3;
3778 +struct QDMA_txdesc {
3779 + QDMA_TXD_INFO1_T txd_info1;
3780 + QDMA_TXD_INFO2_T txd_info2;
3781 + QDMA_TXD_INFO3_T txd_info3;
3782 + QDMA_TXD_INFO4_T txd_info4;
3783 +#ifdef CONFIG_32B_DESC
3784 + unsigned int txd_info5;
3785 + unsigned int txd_info6;
3786 + unsigned int txd_info7;
3787 + unsigned int txd_info8;
3792 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
3794 +#define PHY_Enable_Auto_Nego 0x1000
3795 +#define PHY_Restart_Auto_Nego 0x0200
3797 +/* PHY_STAT_REG = 1; */
3798 +#define PHY_Auto_Neco_Comp 0x0020
3799 +#define PHY_Link_Status 0x0004
3801 +/* PHY_AUTO_NEGO_REG = 4; */
3802 +#define PHY_Cap_10_Half 0x0020
3803 +#define PHY_Cap_10_Full 0x0040
3804 +#define PHY_Cap_100_Half 0x0080
3805 +#define PHY_Cap_100_Full 0x0100
3807 +/* proc definition */
3809 +#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
3810 + !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621)
3811 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
3812 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
3813 +#define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
3814 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
3817 +#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
3818 +#if defined (CONFIG_RALINK_RT2880)
3819 +#define PROCREG_DIR "rt2880"
3820 +#elif defined (CONFIG_RALINK_RT3052)
3821 +#define PROCREG_DIR "rt3052"
3822 +#elif defined (CONFIG_RALINK_RT3352)
3823 +#define PROCREG_DIR "rt3352"
3824 +#elif defined (CONFIG_RALINK_RT5350)
3825 +#define PROCREG_DIR "rt5350"
3826 +#elif defined (CONFIG_RALINK_RT2883)
3827 +#define PROCREG_DIR "rt2883"
3828 +#elif defined (CONFIG_RALINK_RT3883)
3829 +#define PROCREG_DIR "rt3883"
3830 +#elif defined (CONFIG_RALINK_RT6855)
3831 +#define PROCREG_DIR "rt6855"
3832 +#elif defined (CONFIG_RALINK_MT7620)
3833 +#define PROCREG_DIR "mt7620"
3834 +#elif defined (CONFIG_RALINK_MT7621)
3835 +#define PROCREG_DIR "mt7621"
3836 +#elif defined (CONFIG_RALINK_MT7628)
3837 +#define PROCREG_DIR "mt7628"
3838 +#elif defined (CONFIG_RALINK_RT6855A)
3839 +#define PROCREG_DIR "rt6855a"
3841 +#define PROCREG_DIR "rt2880"
3843 +#define PROCREG_SKBFREE "skb_free"
3844 +#define PROCREG_TXRING "tx_ring"
3845 +#define PROCREG_RXRING "rx_ring"
3846 +#define PROCREG_NUM_OF_TXD "num_of_txd"
3847 +#define PROCREG_TSO_LEN "tso_len"
3848 +#define PROCREG_LRO_STATS "lro_stats"
3849 +#define PROCREG_GMAC "gmac"
3850 +#define PROCREG_GMAC2 "gmac2"
3851 +#define PROCREG_CP0 "cp0"
3852 +#define PROCREG_RAQOS "qos"
3853 +#define PROCREG_READ_VAL "regread_value"
3854 +#define PROCREG_WRITE_VAL "regwrite_value"
3855 +#define PROCREG_ADDR "reg_addr"
3856 +#define PROCREG_CTL "procreg_control"
3857 +#define PROCREG_RXDONE_INTR "rxdone_intr_count"
3858 +#define PROCREG_ESW_INTR "esw_intr_count"
3859 +#define PROCREG_ESW_CNT "esw_cnt"
3860 +#define PROCREG_SNMP "snmp"
3861 +#if defined (TASKLET_WORKQUEUE_SW)
3862 +#define PROCREG_SCHE "schedule"
3864 +#define PROCREG_QDMA "qdma"
3866 +struct rt2880_reg_op_data {
3868 + unsigned int reg_addr;
3870 + unsigned int reg_value;
3873 +#ifdef CONFIG_RAETH_LRO
3874 +struct lro_counters {
3875 + u32 lro_aggregated;
3880 +struct lro_para_struct {
3881 + unsigned int lan_ip1;
3884 +#endif // CONFIG_RAETH_LRO //
3889 +typedef struct end_device
3892 + unsigned int tx_cpu_owner_idx0;
3893 + unsigned int rx_cpu_owner_idx0;
3894 + unsigned int fe_int_status;
3895 + unsigned int tx_full;
3897 +#if !defined (CONFIG_RAETH_QDMA)
3898 + unsigned int phy_tx_ring0;
3901 + struct sk_buff *free_skb[NUM_TX_DESC];
3902 + unsigned int tx_dma_ptr;
3903 + unsigned int tx_cpu_ptr;
3904 + unsigned int free_txd_num;
3905 + unsigned int free_txd_head;
3906 + unsigned int free_txd_tail;
3907 + struct QDMA_txdesc *txd_pool;
3908 + dma_addr_t phy_txd_pool;
3909 +// unsigned int phy_txd_pool;
3910 + unsigned int txd_pool_info[NUM_TX_DESC];
3913 + unsigned int phy_rx_ring0, phy_rx_ring1;
3915 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
3916 + defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
3917 + defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
3918 + defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3919 + //send signal to user application to notify link status changed
3920 + struct work_struct kill_sig_wq;
3923 + struct work_struct reset_task;
3924 +#ifdef WORKQUEUE_BH
3925 + struct work_struct rx_wq;
3927 +#if defined (TASKLET_WORKQUEUE_SW)
3928 + struct work_struct rx_wq;
3930 +#endif // WORKQUEUE_BH //
3932 +#if defined(CONFIG_RAETH_QOS)
3933 + struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC];
3934 + unsigned int free_idx[NUM_TX_RINGS];
3936 + struct sk_buff* skb_free[NUM_TX_DESC];
3937 + unsigned int free_idx;
3940 + struct net_device_stats stat; /* The new statistics table. */
3941 + spinlock_t page_lock; /* Page register locks */
3942 + struct PDMA_txdesc *tx_ring0;
3943 +#if defined(CONFIG_RAETH_QOS)
3944 + struct PDMA_txdesc *tx_ring1;
3945 + struct PDMA_txdesc *tx_ring2;
3946 + struct PDMA_txdesc *tx_ring3;
3948 + struct PDMA_rxdesc *rx_ring0;
3949 + struct sk_buff *netrx0_skbuf[NUM_RX_DESC];
3950 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
3951 + struct PDMA_rxdesc *rx_ring1;
3952 + struct sk_buff *netrx1_skbuf[NUM_RX_DESC];
3954 +#ifdef CONFIG_RAETH_NAPI
3956 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
3957 + struct napi_struct napi;
3960 +#ifdef CONFIG_PSEUDO_SUPPORT
3961 + struct net_device *PseudoDev;
3962 + unsigned int isPseudo;
3964 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
3965 + struct mii_if_info mii_info;
3967 +#ifdef CONFIG_RAETH_LRO
3968 + struct lro_counters lro_counters;
3969 + struct net_lro_mgr lro_mgr;
3970 + struct net_lro_desc lro_arr[8];
3972 +#ifdef CONFIG_RAETH_HW_VLAN_RX
3973 + struct vlan_group *vlgrp;
3975 +} END_DEVICE, *pEND_DEVICE;
3978 +#define RAETH_VERSION "v3.0"
3982 +#ifdef CONFIG_RAETH_QDMA
3983 +#define DMA_GLO_CFG QDMA_GLO_CFG
3984 +#define GDMA1_FWD_PORT 0x5555
3985 +#define GDMA2_FWD_PORT 0x5555
3986 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
3987 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
3988 +#define RAETH_FE_INT_STATUS QFE_INT_STATUS
3989 +#define RAETH_FE_INT_ALL QFE_INT_ALL
3990 +#define RAETH_FE_INT_ENABLE QFE_INT_ENABLE
3991 +#define RAETH_FE_INT_DLY_INIT QFE_INT_DLY_INIT
3992 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT
3993 +#define RAETH_TX_DLY_INT RLS_DLY_INT
3994 +#define RAETH_TX_DONE_INT0 RLS_DONE_INT
3995 +#define RAETH_DLY_INT_CFG QDMA_DELAY_INT
3997 +#define DMA_GLO_CFG PDMA_GLO_CFG
3998 +#define GDMA1_FWD_PORT 0x0000
3999 +#define GDMA2_FWD_PORT 0x0000
4000 +#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
4001 +#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
4002 +#define RAETH_FE_INT_STATUS FE_INT_STATUS
4003 +#define RAETH_FE_INT_ALL FE_INT_ALL
4004 +#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
4005 +#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
4006 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
4007 +#define RAETH_TX_DLY_INT TX_DLY_INT
4008 +#define RAETH_TX_DONE_INT0 TX_DONE_INT0
4009 +#define RAETH_DLY_INT_CFG DLY_INT_CFG
4012 +++ b/drivers/net/ethernet/raeth/ra_ioctl.h
4014 +#ifndef _RAETH_IOCTL_H
4015 +#define _RAETH_IOCTL_H
4017 +/* ioctl commands */
4018 +#define RAETH_ESW_REG_READ 0x89F1
4019 +#define RAETH_ESW_REG_WRITE 0x89F2
4020 +#define RAETH_MII_READ 0x89F3
4021 +#define RAETH_MII_WRITE 0x89F4
4022 +#define RAETH_ESW_INGRESS_RATE 0x89F5
4023 +#define RAETH_ESW_EGRESS_RATE 0x89F6
4024 +#define RAETH_ESW_PHY_DUMP 0x89F7
4025 +#define RAETH_QDMA_REG_READ 0x89F8
4026 +#define RAETH_QDMA_REG_WRITE 0x89F9
4027 +#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
4028 +#define RAETH_QDMA_READ_CPU_CLK 0x89FB
4030 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4031 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4033 +#define REG_ESW_WT_MAC_MFC 0x10
4034 +#define REG_ESW_WT_MAC_ATA1 0x74
4035 +#define REG_ESW_WT_MAC_ATA2 0x78
4036 +#define REG_ESW_WT_MAC_ATWD 0x7C
4037 +#define REG_ESW_WT_MAC_ATC 0x80
4039 +#define REG_ESW_TABLE_TSRA1 0x84
4040 +#define REG_ESW_TABLE_TSRA2 0x88
4041 +#define REG_ESW_TABLE_ATRD 0x8C
4044 +#define REG_ESW_VLAN_VTCR 0x90
4045 +#define REG_ESW_VLAN_VAWD1 0x94
4046 +#define REG_ESW_VLAN_VAWD2 0x98
4049 +#define REG_ESW_VLAN_ID_BASE 0x100
4051 +//#define REG_ESW_VLAN_ID_BASE 0x50
4052 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4053 +#define REG_ESW_TABLE_SEARCH 0x24
4054 +#define REG_ESW_TABLE_STATUS0 0x28
4055 +#define REG_ESW_TABLE_STATUS1 0x2C
4056 +#define REG_ESW_TABLE_STATUS2 0x30
4057 +#define REG_ESW_WT_MAC_AD0 0x34
4058 +#define REG_ESW_WT_MAC_AD1 0x38
4059 +#define REG_ESW_WT_MAC_AD2 0x3C
4062 +/* rt3052 embedded ethernet switch registers */
4063 +#define REG_ESW_VLAN_ID_BASE 0x50
4064 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4065 +#define REG_ESW_TABLE_SEARCH 0x24
4066 +#define REG_ESW_TABLE_STATUS0 0x28
4067 +#define REG_ESW_TABLE_STATUS1 0x2C
4068 +#define REG_ESW_TABLE_STATUS2 0x30
4069 +#define REG_ESW_WT_MAC_AD0 0x34
4070 +#define REG_ESW_WT_MAC_AD1 0x38
4071 +#define REG_ESW_WT_MAC_AD2 0x3C
4075 +#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
4076 +#define REG_ESW_MAX 0x16C
4077 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4078 + defined (CONFIG_RALINK_MT7620)
4079 +#define REG_ESW_MAX 0x7FFFF
4080 +#else //RT305x, RT3350
4081 +#define REG_ESW_MAX 0xFC
4083 +#define REG_HQOS_MAX 0x3FFF
4086 +typedef struct rt3052_esw_reg {
4091 +typedef struct ralink_mii_ioctl_data {
4096 +} ra_mii_ioctl_data;
4098 +typedef struct rt335x_esw_reg {
4099 + unsigned int on_off;
4100 + unsigned int port;
4101 + unsigned int bw;/*Mbps*/
4107 +++ b/drivers/net/ethernet/raeth/ra_mac.c
4109 +#include <linux/module.h>
4110 +#include <linux/version.h>
4111 +#include <linux/kernel.h>
4112 +#include <linux/sched.h>
4113 +#include <linux/types.h>
4114 +#include <linux/fcntl.h>
4115 +#include <linux/interrupt.h>
4116 +#include <linux/ptrace.h>
4117 +#include <linux/ioport.h>
4118 +#include <linux/in.h>
4119 +#include <linux/slab.h>
4120 +#include <linux/string.h>
4121 +#include <linux/signal.h>
4122 +#include <linux/irq.h>
4123 +#include <linux/ctype.h>
4125 +#include <asm/io.h>
4126 +#include <asm/bitops.h>
4127 +#include <asm/io.h>
4128 +#include <asm/dma.h>
4130 +#include <asm/rt2880/surfboardint.h> /* for cp0 reg access, added by bobtseng */
4132 +#include <linux/errno.h>
4133 +#include <linux/init.h>
4134 +//#include <linux/mca.h>
4136 +#include <linux/netdevice.h>
4137 +#include <linux/etherdevice.h>
4138 +#include <linux/skbuff.h>
4140 +#include <linux/init.h>
4141 +#include <linux/module.h>
4142 +#include <linux/proc_fs.h>
4143 +#include <asm/uaccess.h>
4145 +#if defined(CONFIG_USER_SNMPD)
4146 +#include <linux/seq_file.h>
4151 +#include "ra2882ethreg.h"
4152 +#include "raether.h"
4153 +#include "ra_mac.h"
4155 +extern struct net_device *dev_raether;
4158 +void ra2880stop(END_DEVICE *ei_local)
4160 + unsigned int regValue;
4161 + printk("ra2880stop()...");
4163 + regValue = sysRegRead(PDMA_GLO_CFG);
4164 + regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
4165 + sysRegWrite(PDMA_GLO_CFG, regValue);
4166 + printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regValue);
4170 +void ei_irq_clear(void)
4172 + sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
4173 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_STATUS", FE_INT_STATUS, 0xFFFFFFFF);
4176 +void rt2880_gmac_hard_reset(void)
4178 + sysRegWrite(RSTCTRL, RALINK_FE_RST);
4179 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, RALINK_FE_RST);
4180 + sysRegWrite(RSTCTRL, 0);
4181 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, 0);
4184 +void ra2880EnableInterrupt()
4186 + unsigned int regValue = sysRegRead(FE_INT_ENABLE);
4187 + sysRegWrite(FE_INT_ENABLE, regValue);
4188 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_ENABLE", FE_INT_ENABLE, regValue);
4191 +void ra2880MacAddressSet(unsigned char p[6])
4193 + unsigned long regValue;
4195 + regValue = (p[0] << 8) | (p[1]);
4196 + sysRegWrite(GDMA1_MAC_ADRH, regValue);
4197 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRH", GDMA1_MAC_ADRH, regValue);
4199 + regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
4200 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRL", GDMA1_MAC_ADRL, regValue);
4201 + sysRegWrite(GDMA1_MAC_ADRL, regValue);
4208 +++ b/drivers/net/ethernet/raeth/ra_mac.h
4213 +void ra2880stop(END_DEVICE *ei_local);
4214 +void ra2880MacAddressSet(unsigned char p[6]);
4215 +void ra2880Mac2AddressSet(unsigned char p[6]);
4216 +void ethtool_init(struct net_device *dev);
4218 +void ra2880EnableInterrupt(void);
4220 +void dump_qos(void);
4221 +void dump_reg(void);
4222 +void dump_cp0(void);
4224 +int debug_proc_init(void);
4225 +void debug_proc_exit(void);
4227 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4228 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4229 +void enable_auto_negotiate(int unused);
4231 +void enable_auto_negotiate(int ge);
4234 +void rt2880_gmac_hard_reset(void);
4236 +int TsoLenUpdate(int tso_len);
4237 +int NumOfTxdUpdate(int num_of_txd);
4239 +#ifdef CONFIG_RAETH_LRO
4240 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
4242 +int getnext(const char *src, int separator, char *dest);
4243 +int str_to_ip(unsigned int *ip, const char *str);
4246 +++ b/drivers/net/ethernet/raeth/raether.c
4248 +#include <linux/module.h>
4249 +#include <linux/version.h>
4250 +#include <linux/kernel.h>
4251 +#include <linux/types.h>
4252 +#include <linux/pci.h>
4253 +#include <linux/interrupt.h>
4254 +#include <linux/init.h>
4255 +#include <linux/skbuff.h>
4256 +#include <linux/if_vlan.h>
4257 +#include <linux/if_ether.h>
4258 +#include <linux/fs.h>
4259 +#include <asm/uaccess.h>
4260 +#include <linux/delay.h>
4261 +#include <linux/sched.h>
4263 +#include <asm/rt2880/rt_mmap.h>
4264 +#include "ra2882ethreg.h"
4265 +#include "raether.h"
4266 +#include "ra_mac.h"
4267 +#include "ra_ioctl.h"
4269 +static int rt2880_eth_recv(struct net_device* dev);
4272 +void setup_internal_gsw(void);
4274 +#define MAX_RX_LENGTH 1536
4276 +struct net_device *dev_raether;
4278 +static int rx_dma_owner_idx;
4279 +static int rx_dma_owner_idx0;
4280 +static int pending_recv;
4281 +static struct PDMA_rxdesc *rx_ring;
4282 +static unsigned long tx_ring_full=0;
4284 +#define KSEG1 0xa0000000
4285 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
4286 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
4288 +extern int fe_dma_init(struct net_device *dev);
4289 +extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
4290 +extern void ei_xmit_housekeeping(unsigned long unused);
4291 +extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
4293 +static int ei_set_mac_addr(struct net_device *dev, void *p)
4295 + struct sockaddr *addr = p;
4297 + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4299 + if(netif_running(dev))
4302 + ra2880MacAddressSet(addr->sa_data);
4307 +void set_fe_dma_glo_cfg(void)
4309 + int dma_glo_cfg=0;
4311 + dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
4313 + dma_glo_cfg |= (RX_2B_OFFSET);
4315 + sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
4316 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "DMA_GLO_CFG", DMA_GLO_CFG, dma_glo_cfg);
4319 +int forward_config(struct net_device *dev)
4321 + unsigned int regVal, regCsg;
4323 + regVal = sysRegRead(GDMA1_FWD_CFG);
4324 + regCsg = sysRegRead(CDMA_CSG_CFG);
4326 + //set unicast/multicast/broadcast frame to cpu
4327 + regVal &= ~0xFFFF;
4328 + regVal |= GDMA1_FWD_PORT;
4331 + //disable ipv4 header checksum check
4332 + regVal &= ~GDM1_ICS_EN;
4333 + regCsg &= ~ICS_GEN_EN;
4335 + //disable tcp checksum check
4336 + regVal &= ~GDM1_TCS_EN;
4337 + regCsg &= ~TCS_GEN_EN;
4339 + //disable udp checksum check
4340 + regVal &= ~GDM1_UCS_EN;
4341 + regCsg &= ~UCS_GEN_EN;
4344 + dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
4347 + sysRegWrite(GDMA1_FWD_CFG, regVal);
4348 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "GDMA1_FWD_CFG", GDMA1_FWD_CFG, regVal);
4349 + sysRegWrite(CDMA_CSG_CFG, regCsg);
4350 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "CDMA_CSG_CFG", CDMA_CSG_CFG, regCsg);
4353 + sysRegWrite(FE_RST_GL, regVal);
4354 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, regVal);
4355 + sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
4356 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, 1);
4358 + regCsg = sysRegRead(CDMA_CSG_CFG);
4359 + printk("CDMA_CSG_CFG = %0X\n",regCsg);
4360 + regVal = sysRegRead(GDMA1_FWD_CFG);
4361 + printk("GDMA1_FWD_CFG = %0X\n",regVal);
4367 +static int rt2880_eth_recv(struct net_device* dev)
4369 + struct sk_buff *skb, *rx_skb;
4370 + unsigned int length = 0;
4371 + unsigned long RxProcessed;
4374 + int bReschedule = 0;
4375 + END_DEVICE* ei_local = netdev_priv(dev);
4381 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4385 + if (RxProcessed++ > NUM_RX_MAX_PROCESS)
4387 + // need to reschedule rx handle
4394 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
4395 + rx_ring = ei_local->rx_ring0;
4396 + rx_dma_owner_idx = rx_dma_owner_idx0;
4401 + /* skb processing */
4402 + length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
4403 + rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
4404 + rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
4405 + rx_skb->len = length;
4407 + rx_skb->data += NET_IP_ALIGN;
4409 + rx_skb->tail = rx_skb->data + length;
4411 + rx_skb->dev = dev;
4412 + rx_skb->protocol = eth_type_trans(rx_skb,dev);
4414 + rx_skb->ip_summed = CHECKSUM_NONE;
4417 + /* We have to check the free memory size is big enough
4418 + * before pass the packet to cpu*/
4419 + skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
4421 + if (unlikely(skb == NULL))
4423 + printk(KERN_ERR "skb not available...\n");
4424 + ei_local->stat.rx_dropped++;
4434 + ei_local->stat.rx_packets++;
4435 + ei_local->stat.rx_bytes += length;
4439 + rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
4440 + rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
4441 + rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
4442 + rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
4444 + /* Move point to next RXD which wants to alloc*/
4445 + sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4446 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_RX_CALC_IDX0", RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4447 + ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
4449 + /* Update to Next packet point that was received.
4451 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4454 + return bReschedule;
4457 +void ei_receive_workq(struct work_struct *work)
4459 + struct net_device *dev = dev_raether;
4460 + END_DEVICE *ei_local = netdev_priv(dev);
4461 + unsigned long reg_int_mask=0;
4462 + int bReschedule=0;
4465 + if(tx_ring_full==0){
4466 + bReschedule = rt2880_eth_recv(dev);
4469 + schedule_work(&ei_local->rx_wq);
4471 + reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
4472 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4473 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4476 + schedule_work(&ei_local->rx_wq);
4481 +static irqreturn_t ei_interrupt(int irq, void *dev_id)
4483 + unsigned long reg_int_val;
4484 + unsigned long reg_int_mask=0;
4485 + unsigned int recv = 0;
4486 + unsigned int transmit __maybe_unused = 0;
4487 + unsigned long flags;
4489 + struct net_device *dev = (struct net_device *) dev_id;
4490 + END_DEVICE *ei_local = netdev_priv(dev);
4494 + printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
4499 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4500 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
4502 + if((reg_int_val & RX_DLY_INT))
4505 + if (reg_int_val & RAETH_TX_DLY_INT)
4508 + sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4509 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_STATUS", RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4511 + ei_xmit_housekeeping(0);
4513 + if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
4515 + reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
4516 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4517 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4519 + schedule_work(&ei_local->rx_wq);
4521 + else if (recv == 1 && tx_ring_full==1)
4525 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4527 + return IRQ_HANDLED;
4530 +static void esw_link_status_changed(int port_no, void *dev_id)
4532 + unsigned int reg_val;
4533 + mii_mgr_read(31, (0x3008 + (port_no*0x100)), ®_val);
4534 + if(reg_val & 0x1) {
4535 + printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
4537 + printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
4542 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
4544 + unsigned long flags;
4545 + unsigned int reg_int_val;
4546 + struct net_device *dev = (struct net_device *) dev_id;
4547 + END_DEVICE *ei_local = netdev_priv(dev);
4549 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4550 + mii_mgr_read(31, 0x700c, ®_int_val);
4552 + if (reg_int_val & P4_LINK_CH) {
4553 + esw_link_status_changed(4, dev_id);
4556 + if (reg_int_val & P3_LINK_CH) {
4557 + esw_link_status_changed(3, dev_id);
4559 + if (reg_int_val & P2_LINK_CH) {
4560 + esw_link_status_changed(2, dev_id);
4562 + if (reg_int_val & P1_LINK_CH) {
4563 + esw_link_status_changed(1, dev_id);
4565 + if (reg_int_val & P0_LINK_CH) {
4566 + esw_link_status_changed(0, dev_id);
4569 + mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
4570 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4571 + return IRQ_HANDLED;
4576 +static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
4578 + return ei_start_xmit(skb, dev, 1);
4581 +static int ei_change_mtu(struct net_device *dev, int new_mtu)
4583 + unsigned long flags;
4584 + END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
4586 + if ( ei_local == NULL ) {
4587 + printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
4591 + spin_lock_irqsave(&ei_local->page_lock, flags);
4593 + if ( (new_mtu > 4096) || (new_mtu < 64)) {
4594 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4598 + if ( new_mtu > 1500 ) {
4599 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4603 + dev->mtu = new_mtu;
4605 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4610 +static const struct net_device_ops ei_netdev_ops = {
4611 + .ndo_init = rather_probe,
4612 + .ndo_open = ei_open,
4613 + .ndo_stop = ei_close,
4614 + .ndo_start_xmit = ei_start_xmit_fake,
4615 + .ndo_set_mac_address = eth_mac_addr,
4616 + .ndo_change_mtu = ei_change_mtu,
4617 + .ndo_validate_addr = eth_validate_addr,
4620 +void ra2880_setup_dev_fptable(struct net_device *dev)
4622 + RAETH_PRINT(__FUNCTION__ "is called!\n");
4624 + dev->netdev_ops = &ei_netdev_ops;
4625 +#define TX_TIMEOUT (5*HZ)
4626 + dev->watchdog_timeo = TX_TIMEOUT;
4630 +void fe_reset(void)
4633 + val = sysRegRead(RSTCTRL);
4635 + val = val | RALINK_FE_RST;
4636 + sysRegWrite(RSTCTRL, val);
4637 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4638 + val = val & ~(RALINK_FE_RST);
4639 + sysRegWrite(RSTCTRL, val);
4640 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4643 +void ei_reset_task(struct work_struct *work)
4645 + struct net_device *dev = dev_raether;
4653 +void ei_tx_timeout(struct net_device *dev)
4655 + END_DEVICE *ei_local = netdev_priv(dev);
4657 + schedule_work(&ei_local->reset_task);
4660 +int __init rather_probe(struct net_device *dev)
4662 + END_DEVICE *ei_local = netdev_priv(dev);
4663 + struct sockaddr addr;
4664 + unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
4667 + memcpy(addr.sa_data, mac_addr01234, 5);
4668 + addr.sa_data[5] = prandom_u32()&0xFF;
4669 + ei_set_mac_addr(dev, &addr);
4670 + spin_lock_init(&ei_local->page_lock);
4677 +int ei_open(struct net_device *dev)
4680 + unsigned long flags;
4681 + END_DEVICE *ei_local;
4684 + if (!try_module_get(THIS_MODULE))
4686 + printk("%s: Cannot reserve module\n", __FUNCTION__);
4689 + printk("Raeth %s (",RAETH_VERSION);
4690 + printk("Workqueue");
4693 + ei_local = netdev_priv(dev); // get device pointer from System
4694 + // unsigned int flags;
4696 + if (ei_local == NULL)
4698 + printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
4702 + /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
4703 + for ( i = 0; i < NUM_RX_DESC; i++)
4705 + ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
4706 + if (ei_local->netrx0_skbuf[i] == NULL ) {
4707 + printk("rx skbuff buffer allocation failed!");
4712 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4714 + fe_sw_init(); //initialize fe and switch register
4715 + err = request_irq( dev->irq, ei_interrupt, 0, dev->name, dev); // try to fix irq in open
4719 + if ( dev->dev_addr != NULL) {
4720 + ra2880MacAddressSet((void *)(dev->dev_addr));
4722 + printk("dev->dev_addr is empty !\n");
4724 + mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
4725 + err = request_irq(31, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
4729 + sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4730 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_DLY_INT_CFG", RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4731 + sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4732 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4734 + INIT_WORK(&ei_local->reset_task, ei_reset_task);
4736 + INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
4738 + netif_start_queue(dev);
4741 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4744 + forward_config(dev);
4748 +int ei_close(struct net_device *dev)
4751 + END_DEVICE *ei_local = netdev_priv(dev); // device pointer
4752 + unsigned long flags;
4753 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4755 + cancel_work_sync(&ei_local->reset_task);
4756 + netif_stop_queue(dev);
4757 + ra2880stop(ei_local);
4760 + cancel_work_sync(&ei_local->rx_wq);
4761 + free_irq(dev->irq, dev);
4762 + free_irq(31, dev);
4763 + for ( i = 0; i < NUM_RX_DESC; i++)
4765 + if (ei_local->netrx0_skbuf[i] != NULL) {
4766 + dev_kfree_skb(ei_local->netrx0_skbuf[i]);
4767 + ei_local->netrx0_skbuf[i] = NULL;
4770 + if (ei_local->tx_ring0 != NULL) {
4771 + pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
4773 + pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
4775 + printk("Free TX/RX Ring Memory!\n");
4778 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4780 + module_put(THIS_MODULE);
4785 +void setup_internal_gsw(void)
4790 + /* reduce RGMII2 PAD driving strength */
4791 + *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
4793 + //RGMII1=Normal mode
4794 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
4796 + //GMAC1= RGMII mode
4797 + *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
4799 + //enable MDIO to control MT7530
4800 + regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
4801 + regValue &= ~(0x3 << 12);
4802 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
4807 + mii_mgr_read(i, 0x0 ,®Value);
4808 + regValue |= (0x1<<11);
4809 + mii_mgr_write(i, 0x0, regValue);
4811 + mii_mgr_write(31, 0x7000, 0x3); //reset switch
4814 + if(sysRegRead(0xbe00000c)==0x00030101) {
4815 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e30b);//(GE1, Force 1000M/FD, FC ON)
4816 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e30b);
4817 + mii_mgr_write(31, 0x3600, 0x5e30b);
4819 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e33b);//(GE1, Force 1000M/FD, FC ON)
4820 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e33b);
4821 + mii_mgr_write(31, 0x3600, 0x5e33b);
4824 + sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
4825 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x200", RALINK_ETH_SW_BASE+0x200, 0x00008000);
4827 + //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
4828 + mii_mgr_read(31, 0x7804 ,®Value);
4829 + regValue &= ~(1<<8); //Enable Port 6
4830 + regValue |= (1<<6); //Disable Port 5
4831 + regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
4833 + regValue |= (1<<16);//change HW-TRAP
4834 + printk("change HW-TRAP to 0x%x!!!!!!!!!!!!",regValue);
4835 + mii_mgr_write(31, 0x7804 ,regValue);
4836 + regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
4837 + regValue = (regValue >> 6) & 0x7;
4838 + if(regValue >= 6) { //25Mhz Xtal
4840 + } else if(regValue >=3) { //40Mhz
4842 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock
4843 + mii_mgr_write(0, 14, 0x410);
4844 + mii_mgr_write(0, 13, 0x401f);
4845 + mii_mgr_write(0, 14, 0x0);
4847 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL
4848 + mii_mgr_write(0, 14, 0x40d);
4849 + mii_mgr_write(0, 13, 0x401f);
4850 + mii_mgr_write(0, 14, 0x2020);
4852 + mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz
4853 + mii_mgr_write(0, 14, 0x40e);
4854 + mii_mgr_write(0, 13, 0x401f);
4855 + mii_mgr_write(0, 14, 0x119);
4857 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL
4858 + mii_mgr_write(0, 14, 0x40d);
4859 + mii_mgr_write(0, 13, 0x401f);
4860 + mii_mgr_write(0, 14, 0x2820);
4862 + udelay(20); //suggest by CD
4864 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock
4865 + mii_mgr_write(0, 14, 0x410);
4866 + mii_mgr_write(0, 13, 0x401f);
4867 + }else { //20Mhz Xtal
4872 + mii_mgr_write(0, 14, 0x1); /*RGMII*/
4875 + mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M
4876 + mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M
4878 + mii_mgr_write(31, 0x7b00, 8); // delay setting for 100M
4879 + mii_mgr_write(31, 0x7b04, 0x14); // for 100M
4882 + mii_mgr_write(31, 0x7a54, 0x44); //lower driving
4883 + mii_mgr_write(31, 0x7a5c, 0x44); //lower driving
4884 + mii_mgr_write(31, 0x7a64, 0x44); //lower driving
4885 + mii_mgr_write(31, 0x7a6c, 0x44); //lower driving
4886 + mii_mgr_write(31, 0x7a74, 0x44); //lower driving
4887 + mii_mgr_write(31, 0x7a7c, 0x44); //lower driving
4892 + mii_mgr_read(i, 0x0 ,®Value);
4893 + regValue &= ~(0x1<<11);
4894 + mii_mgr_write(i, 0x0, regValue);
4897 + mii_mgr_read(31, 0x7808 ,®Value);
4898 + regValue |= (3<<16); //Enable INTR
4899 + mii_mgr_write(31, 0x7808 ,regValue);
4902 +int __init ra2882eth_init(void)
4905 + struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
4909 + strcpy(dev->name, DEV_NAME);
4910 + dev->irq = IRQ_ENET0;
4911 + dev->addr_len = 6;
4912 + dev->base_addr = RALINK_FRAME_ENGINE_BASE;
4914 + rather_probe(dev);
4915 + ra2880_setup_dev_fptable(dev);
4917 + if ( register_netdev(dev) != 0) {
4918 + printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
4923 + dev_raether = dev;
4927 +void fe_sw_init(void)
4929 + setup_internal_gsw();
4933 +void ra2882eth_cleanup_module(void)
4936 +EXPORT_SYMBOL(set_fe_dma_glo_cfg);
4937 +module_init(ra2882eth_init);
4938 +module_exit(ra2882eth_cleanup_module);
4939 +MODULE_LICENSE("GPL");
4941 +++ b/drivers/net/ethernet/raeth/raether.h
4943 +#ifndef RA2882ETHEND_H
4944 +#define RA2882ETHEND_H
4946 +#ifdef DSP_VIA_NONCACHEABLE
4947 +#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */
4949 +#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */
4952 +#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000))
4953 +#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800))
4955 +#if defined(CONFIG_RALINK_RT2880)
4956 +#define NUM_TX_RINGS 1
4958 +#define NUM_TX_RINGS 4
4960 +#ifdef MEMORY_OPTIMIZATION
4961 +#ifdef CONFIG_RAETH_ROUTER
4962 +#define NUM_RX_DESC 128
4963 +#define NUM_TX_DESC 128
4964 +#elif CONFIG_RT_3052_ESW
4965 +#define NUM_RX_DESC 64
4966 +#define NUM_TX_DESC 64
4968 +#define NUM_RX_DESC 128
4969 +#define NUM_TX_DESC 128
4971 +//#define NUM_RX_MAX_PROCESS 32
4972 +#define NUM_RX_MAX_PROCESS 64
4974 +#if defined (CONFIG_RAETH_ROUTER)
4975 +#define NUM_RX_DESC 256
4976 +#define NUM_TX_DESC 256
4977 +#elif defined (CONFIG_RT_3052_ESW)
4978 +#define NUM_RX_DESC 256
4979 +#define NUM_TX_DESC 256
4981 +#define NUM_RX_DESC 256
4982 +#define NUM_TX_DESC 256
4984 +#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
4985 +#define NUM_RX_MAX_PROCESS 2
4987 +#define NUM_RX_MAX_PROCESS 16
4991 +#define DEV_NAME "eth0"
4992 +#define DEV2_NAME "eth3"
4994 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
4995 +#define GMAC0_OFFSET 0xE000
4996 +#define GMAC2_OFFSET 0xE006
4998 +#define GMAC0_OFFSET 0x28
4999 +#define GMAC2_OFFSET 0x22
5002 +#if defined(CONFIG_RALINK_RT6855A)
5003 +#define IRQ_ENET0 22
5005 +#define IRQ_ENET0 11 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
5008 +#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
5009 +#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
5011 +//#define RAETH_DEBUG
5013 +#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
5015 +#define RAETH_PRINT(fmt, args...) { }
5018 +struct net_device_stats *ra_get_stats(struct net_device *dev);
5020 +void ei_tx_timeout(struct net_device *dev);
5021 +int rather_probe(struct net_device *dev);
5022 +int ei_open(struct net_device *dev);
5023 +int ei_close(struct net_device *dev);
5025 +int ra2882eth_init(void);
5026 +void ra2882eth_cleanup_module(void);
5028 +void ei_xmit_housekeeping(unsigned long data);
5030 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
5031 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
5032 +void fe_sw_init(void);
5036 +++ b/drivers/net/ethernet/raeth/raether_pdma.c
5038 +#include <linux/module.h>
5039 +#include <linux/version.h>
5040 +#include <linux/kernel.h>
5041 +#include <linux/types.h>
5042 +#include <linux/pci.h>
5043 +#include <linux/init.h>
5044 +#include <linux/skbuff.h>
5045 +#include <linux/if_vlan.h>
5046 +#include <linux/if_ether.h>
5047 +#include <linux/fs.h>
5048 +#include <asm/uaccess.h>
5049 +#include <linux/delay.h>
5050 +#include <linux/sched.h>
5051 +#include <asm/rt2880/rt_mmap.h>
5052 +#include "ra2882ethreg.h"
5053 +#include "raether.h"
5054 +#include "ra_mac.h"
5056 +#define MAX_RX_LENGTH 1536
5058 +extern int reg_dbg;
5059 +extern struct net_device *dev_raether;
5060 +static unsigned long tx_ring_full=0;
5062 +#define KSEG1 0xa0000000
5063 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5064 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5066 +extern void set_fe_dma_glo_cfg(void);
5068 +int fe_dma_init(struct net_device *dev)
5072 + unsigned int regVal;
5073 + END_DEVICE* ei_local = netdev_priv(dev);
5077 + regVal = sysRegRead(PDMA_GLO_CFG);
5078 + if((regVal & RX_DMA_BUSY))
5080 + printk("\n RX_DMA_BUSY !!! ");
5083 + if((regVal & TX_DMA_BUSY))
5085 + printk("\n TX_DMA_BUSY !!! ");
5091 + for (i=0;i<NUM_TX_DESC;i++){
5092 + ei_local->skb_free[i]=0;
5094 + ei_local->free_idx =0;
5095 + ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
5096 + printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
5098 + for (i=0; i < NUM_TX_DESC; i++) {
5099 + memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
5100 + ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
5101 + ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
5105 + /* Initial RX Ring 0*/
5106 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5107 + for (i = 0; i < NUM_RX_DESC; i++) {
5108 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5109 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5110 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5111 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5112 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5114 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5117 + regVal = sysRegRead(PDMA_GLO_CFG);
5118 + regVal &= 0x000000FF;
5119 + sysRegWrite(PDMA_GLO_CFG, regVal);
5120 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regVal);
5122 + regVal=sysRegRead(PDMA_GLO_CFG);
5124 + /* Tell the adapter where the TX/RX rings are located. */
5125 + sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5126 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_BASE_PTR0", TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5127 + sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5128 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_MAX_CNT0", TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5129 + sysRegWrite(TX_CTX_IDX0, 0);
5130 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_CTX_IDX0", TX_CTX_IDX0, 0);
5131 + sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
5132 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DTX_IDX0);
5134 + sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5135 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_BASE_PTR0", RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5136 + sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5137 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_MAX_CNT0", RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5138 + sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5139 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_CALC_IDX0", RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5140 + sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
5141 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DRX_IDX0);
5143 + set_fe_dma_glo_cfg();
5148 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5150 + unsigned int length=skb->len;
5151 + END_DEVICE* ei_local = netdev_priv(dev);
5152 + unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
5154 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5156 + ei_local->stat.tx_errors++;
5159 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
5160 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
5161 + if (gmac_no == 1) {
5162 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
5164 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
5166 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
5167 + tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
5168 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5170 + ei_local->stat.tx_errors++;
5172 + sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
5175 + ei_local->stat.tx_packets++;
5176 + ei_local->stat.tx_bytes += length;
5182 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5184 + END_DEVICE *ei_local = netdev_priv(dev);
5185 + unsigned long flags;
5186 + unsigned long tx_cpu_owner_idx;
5187 + unsigned int tx_cpu_owner_idx_next;
5188 + unsigned int num_of_txd;
5189 + unsigned int tx_cpu_owner_idx_next2;
5191 + dev->trans_start = jiffies; /* save the timestamp */
5192 + spin_lock_irqsave(&ei_local->page_lock, flags);
5193 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5195 + tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
5197 + tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
5199 + if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
5200 + rt2880_eth_send(dev, skb, gmac_no);
5202 + tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
5204 + if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
5207 + ei_local->stat.tx_dropped++;
5209 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5213 + ei_local->skb_free[tx_cpu_owner_idx] = skb;
5214 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5218 +void ei_xmit_housekeeping(unsigned long unused)
5220 + struct net_device *dev = dev_raether;
5221 + END_DEVICE *ei_local = netdev_priv(dev);
5222 + struct PDMA_txdesc *tx_desc;
5223 + unsigned long skb_free_idx;
5224 + unsigned long tx_dtx_idx __maybe_unused;
5225 + unsigned long reg_int_mask=0;
5227 + tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
5228 + tx_desc = ei_local->tx_ring0;
5229 + skb_free_idx = ei_local->free_idx;
5230 + if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
5231 + while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
5232 + dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
5233 + ei_local->skb_free[skb_free_idx]=0;
5234 + skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
5237 + netif_wake_queue(dev);
5239 + ei_local->free_idx = skb_free_idx;
5242 + reg_int_mask=sysRegRead(FE_INT_ENABLE);
5243 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
5246 +EXPORT_SYMBOL(ei_start_xmit);
5247 +EXPORT_SYMBOL(ei_xmit_housekeeping);
5248 +EXPORT_SYMBOL(fe_dma_init);
5249 +EXPORT_SYMBOL(rt2880_eth_send);
5251 +++ b/drivers/net/ethernet/raeth/raether_qdma.c
5253 +#include <linux/module.h>
5254 +#include <linux/version.h>
5255 +#include <linux/kernel.h>
5256 +#include <linux/types.h>
5257 +#include <linux/pci.h>
5258 +#include <linux/init.h>
5259 +#include <linux/skbuff.h>
5260 +#include <linux/if_vlan.h>
5261 +#include <linux/if_ether.h>
5262 +#include <linux/fs.h>
5263 +#include <asm/uaccess.h>
5264 +#include <asm/rt2880/surfboardint.h>
5265 +#if defined (CONFIG_RAETH_TSO)
5266 +#include <linux/tcp.h>
5267 +#include <net/ipv6.h>
5268 +#include <linux/ip.h>
5269 +#include <net/ip.h>
5270 +#include <net/tcp.h>
5271 +#include <linux/in.h>
5272 +#include <linux/ppp_defs.h>
5273 +#include <linux/if_pppox.h>
5275 +#include <linux/delay.h>
5276 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5277 +#include <linux/sched.h>
5280 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
5281 +#include <asm/rt2880/rt_mmap.h>
5283 +#include <linux/libata-compat.h>
5286 +#include "ra2882ethreg.h"
5287 +#include "raether.h"
5288 +#include "ra_mac.h"
5289 +#include "ra_ioctl.h"
5290 +#include "ra_rfrw.h"
5291 +#ifdef CONFIG_RAETH_NETLINK
5292 +#include "ra_netlink.h"
5294 +#if defined (CONFIG_RAETH_QOS)
5295 +#include "ra_qos.h"
5298 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5299 +#include "../../../net/nat/hw_nat/ra_nat.h"
5302 +#if defined (TASKLET_WORKQUEUE_SW)
5304 +int working_schedule;
5308 +#if !defined(CONFIG_RA_NAT_NONE)
5311 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
5312 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
5315 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
5318 +#include <asm/mipsregs.h>
5319 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
5320 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
5321 +#endif /* CONFIG_RA_CLASSIFIER */
5323 +#if defined (CONFIG_RALINK_RT3052_MP2)
5324 +int32_t mcast_rx(struct sk_buff * skb);
5325 +int32_t mcast_tx(struct sk_buff * skb);
5328 +#ifdef RA_MTD_RW_BY_NUM
5329 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
5331 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
5334 +/* gmac driver feature set config */
5335 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
5338 +#define DELAY_INT 1
5341 +//#define CONFIG_UNH_TEST
5342 +/* end of config */
5344 +#if defined (CONFIG_RAETH_JUMBOFRAME)
5345 +#define MAX_RX_LENGTH 4096
5347 +#define MAX_RX_LENGTH 1536
5350 +extern struct net_device *dev_raether;
5352 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5353 +static int rx_dma_owner_idx1;
5354 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5355 +static int rx_calc_idx1;
5358 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5359 +static int rx_calc_idx0;
5360 +static unsigned long tx_cpu_owner_idx0=0;
5362 +static unsigned long tx_ring_full=0;
5364 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
5365 +#include "ra_ethtool.h"
5366 +extern struct ethtool_ops ra_ethtool_ops;
5367 +#ifdef CONFIG_PSEUDO_SUPPORT
5368 +extern struct ethtool_ops ra_virt_ethtool_ops;
5369 +#endif // CONFIG_PSEUDO_SUPPORT //
5370 +#endif // (CONFIG_ETHTOOL //
5372 +#ifdef CONFIG_RALINK_VISTA_BASIC
5373 +int is_switch_175c = 1;
5376 +//skb->mark to queue mapping table
5377 +extern unsigned int M2Q_table[64];
5380 +#define KSEG1 0xa0000000
5381 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5382 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5384 +extern void set_fe_dma_glo_cfg(void);
5389 + * @brief: get the TXD index from its address
5393 + * @return: TXD index
5396 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
5398 + struct net_device *dev = dev_raether;
5399 + END_DEVICE *ei_local = netdev_priv(dev);
5401 + ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
5402 + ctx_offset = (*cpu_ptr - ei_local->txd_pool);
5404 + return ctx_offset;
5410 + * @brief get free TXD from TXD queue
5416 +static int get_free_txd(struct QDMA_txdesc **free_txd)
5418 + struct net_device *dev = dev_raether;
5419 + END_DEVICE *ei_local = netdev_priv(dev);
5420 + unsigned int tmp_idx;
5422 + if(ei_local->free_txd_num > 0){
5423 + tmp_idx = ei_local->free_txd_head;
5424 + ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
5425 + ei_local->free_txd_num -= 1;
5426 + *free_txd = &ei_local->txd_pool[tmp_idx];
5429 + return NUM_TX_DESC;
5434 + * @brief add free TXD into TXD queue
5440 +int put_free_txd(int free_txd_idx)
5442 + struct net_device *dev = dev_raether;
5443 + END_DEVICE *ei_local = netdev_priv(dev);
5444 + ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
5445 + ei_local->free_txd_tail = free_txd_idx;
5446 + ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
5447 + ei_local->free_txd_num += 1;
5451 +/*define qdma initial alloc*/
5460 +bool qdma_tx_desc_alloc(void)
5462 + struct net_device *dev = dev_raether;
5463 + END_DEVICE *ei_local = netdev_priv(dev);
5464 + struct QDMA_txdesc *free_txd = NULL;
5465 + unsigned int txd_idx;
5469 + ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
5470 + printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
5472 + if (ei_local->txd_pool == NULL) {
5473 + printk("adapter->txd_pool allocation failed!\n");
5476 + printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
5477 + //set all txd_pool_info to 0.
5478 + for ( i = 0; i < NUM_TX_DESC; i++)
5480 + ei_local->skb_free[i]= 0;
5481 + ei_local->txd_pool_info[i] = i + 1;
5482 + ei_local->txd_pool[i].txd_info3.LS_bit = 1;
5483 + ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
5486 + ei_local->free_txd_head = 0;
5487 + ei_local->free_txd_tail = NUM_TX_DESC - 1;
5488 + ei_local->free_txd_num = NUM_TX_DESC;
5491 + //get free txd from txd pool
5492 + txd_idx = get_free_txd(&free_txd);
5493 + if( txd_idx == NUM_TX_DESC) {
5494 + printk("get_free_txd fail\n");
5498 + //add null TXD for transmit
5499 + ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
5500 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5501 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5502 + sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
5504 + //get free txd from txd pool
5506 + txd_idx = get_free_txd(&free_txd);
5507 + if( txd_idx == NUM_TX_DESC) {
5508 + printk("get_free_txd fail\n");
5511 + // add null TXD for release
5512 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
5513 + sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
5515 + printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
5517 + printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n");
5518 + printk("----------------+---------+--------\n");
5520 + printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
5521 + ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
5526 +bool fq_qdma_init(void)
5528 + struct QDMA_txdesc *free_head = NULL;
5529 + unsigned int free_head_phy;
5530 + unsigned int free_tail_phy;
5531 + unsigned int *free_page_head = NULL;
5532 + unsigned int free_page_head_phy;
5535 + free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
5536 + if (unlikely(free_head == NULL)){
5537 + printk(KERN_ERR "QDMA FQ decriptor not available...\n");
5540 + memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
5542 + free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
5543 + if (unlikely(free_page_head == NULL)){
5544 + printk(KERN_ERR "QDMA FQ pager not available...\n");
5547 + for (i=0; i < NUM_QDMA_PAGE; i++) {
5548 + free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
5549 + if(i < (NUM_QDMA_PAGE-1)){
5550 + free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
5554 + printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
5555 + printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
5556 + printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
5557 + printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
5560 + free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
5563 + free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
5565 + printk("free_head_phy is 0x%x!!!\n", free_head_phy);
5566 + printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
5567 + sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
5568 + sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
5569 + sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
5570 + sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
5574 +int fe_dma_init(struct net_device *dev)
5578 + unsigned int regVal;
5579 + END_DEVICE* ei_local = netdev_priv(dev);
5585 + regVal = sysRegRead(QDMA_GLO_CFG);
5586 + if((regVal & RX_DMA_BUSY))
5588 + printk("\n RX_DMA_BUSY !!! ");
5591 + if((regVal & TX_DMA_BUSY))
5593 + printk("\n TX_DMA_BUSY !!! ");
5598 + /*tx desc alloc, add a NULL TXD to HW*/
5600 + qdma_tx_desc_alloc();
5603 + /* Initial RX Ring 0*/
5604 +#ifdef CONFIG_32B_DESC
5605 + ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5606 + ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
5608 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5610 + for (i = 0; i < NUM_RX_DESC; i++) {
5611 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5612 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5613 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5614 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5615 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5617 + ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
5619 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5621 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5623 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5624 + /* Initial RX Ring 1*/
5625 +#ifdef CONFIG_32B_DESC
5626 + ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5627 + ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
5629 + ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
5631 + for (i = 0; i < NUM_RX_DESC; i++) {
5632 + memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
5633 + ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
5634 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5635 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5636 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5638 + ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
5640 + ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5642 + printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
5645 + regVal = sysRegRead(QDMA_GLO_CFG);
5646 + regVal &= 0x000000FF;
5647 + sysRegWrite(QDMA_GLO_CFG, regVal);
5648 + regVal=sysRegRead(QDMA_GLO_CFG);
5650 + /* Tell the adapter where the TX/RX rings are located. */
5652 + sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5653 + sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_RX_DESC));
5654 + sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5655 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5656 + rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0);
5658 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
5659 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5660 + sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
5661 + sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_RX_DESC));
5662 + sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5663 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5664 + rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1);
5666 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
5669 + set_fe_dma_glo_cfg();
5674 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5676 + unsigned int length=skb->len;
5677 + END_DEVICE* ei_local = netdev_priv(dev);
5679 + struct QDMA_txdesc *cpu_ptr;
5681 + struct QDMA_txdesc *dma_ptr __maybe_unused;
5682 + struct QDMA_txdesc *free_txd;
5684 +#if defined (CONFIG_RAETH_TSO)
5685 + struct iphdr *iph = NULL;
5686 + struct QDMA_txdesc *init_cpu_ptr;
5687 + struct tcphdr *th = NULL;
5688 + struct skb_frag_struct *frag;
5689 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5692 +#endif // CONFIG_RAETH_TSO //
5694 +#if defined (CONFIG_RAETH_TSOV6)
5695 + struct ipv6hdr *ip6h = NULL;
5698 +#ifdef CONFIG_PSEUDO_SUPPORT
5699 + PSEUDO_ADAPTER *pAd;
5701 + cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
5702 + dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
5703 + ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
5704 + ei_local->skb_free[ctx_offset] = skb;
5705 +#if defined (CONFIG_RAETH_TSO)
5706 + init_cpu_ptr = cpu_ptr;
5707 + init_txd_idx = ctx_offset;
5710 +#if !defined (CONFIG_RAETH_TSO)
5713 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5714 + cpu_ptr->txd_info3.SDL = skb->len;
5716 + if (gmac_no == 1) {
5717 + cpu_ptr->txd_info4.FPORT = 1;
5719 + cpu_ptr->txd_info4.FPORT = 2;
5723 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5725 + iph = (struct iphdr *)skb_network_header(skb);
5726 + if (iph->tos == 0xe0)
5727 + cpu_ptr->txd_info3.QID = 3;
5728 + else if (iph->tos == 0xa0)
5729 + cpu_ptr->txd_info3.QID = 2;
5730 + else if (iph->tos == 0x20)
5731 + cpu_ptr->txd_info3.QID = 1;
5733 + cpu_ptr->txd_info3.QID = 0;
5736 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5737 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5738 + cpu_ptr->txd_info4.TUI_CO = 7;
5740 + cpu_ptr->txd_info4.TUI_CO = 0;
5744 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5745 + if(vlan_tx_tag_present(skb)) {
5746 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5748 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5752 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5753 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5754 + if(ra_sw_nat_hook_rx!= NULL){
5755 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5756 + FOE_MAGIC_TAG(skb) = 0;
5761 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5762 + cpu_ptr->txd_info4.UDF = 0x2F;
5765 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5766 + cpu_ptr->txd_info3.SWC_bit = 1;
5768 + //3. get NULL TXD and decrease free_tx_num by 1.
5769 + ctx_offset = get_free_txd(&free_txd);
5770 + if(ctx_offset == NUM_TX_DESC) {
5771 + printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
5775 + //4. hook new TXD in the end of queue
5776 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5779 + //5. move CPU_PTR to new TXD
5780 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5781 + cpu_ptr->txd_info3.OWN_bit = 0;
5782 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5785 + printk("----------------------------------------------\n");
5786 + printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
5787 + printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
5788 + printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
5789 + printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
5792 +#else //#if !defined (CONFIG_RAETH_TSO)
5793 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5794 + cpu_ptr->txd_info3.SDL = (length - skb->data_len);
5795 + cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
5796 + if (gmac_no == 1) {
5797 + cpu_ptr->txd_info4.FPORT = 1;
5799 + cpu_ptr->txd_info4.FPORT = 2;
5802 + cpu_ptr->txd_info4.TSO = 0;
5803 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5804 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5805 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5806 + cpu_ptr->txd_info4.TUI_CO = 7;
5808 + cpu_ptr->txd_info4.TUI_CO = 0;
5812 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5813 + if(vlan_tx_tag_present(skb)) {
5814 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5816 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5820 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5821 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5822 + if(ra_sw_nat_hook_rx!= NULL){
5823 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5824 + FOE_MAGIC_TAG(skb) = 0;
5829 + cpu_ptr->txd_info3.SWC_bit = 1;
5831 + ctx_offset = get_free_txd(&free_txd);
5832 + if(ctx_offset == NUM_TX_DESC) {
5833 + printk("get_free_txd fail\n");
5836 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5837 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5839 + if(nr_frags > 0) {
5840 + for(i=0;i<nr_frags;i++) {
5841 + frag = &skb_shinfo(skb)->frags[i];
5842 + cpu_ptr = free_txd;
5843 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5844 + cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
5845 + cpu_ptr->txd_info3.SDL = frag->size;
5846 + cpu_ptr->txd_info3.LS_bit = (i==nr_frags-1)?1:0;
5847 + cpu_ptr->txd_info3.OWN_bit = 0;
5848 + cpu_ptr->txd_info3.SWC_bit = 1;
5849 + ei_local->skb_free[ctx_offset] = (i==nr_frags-1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5851 + ctx_offset = get_free_txd(&free_txd);
5852 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5853 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5855 + ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5858 + if(skb_shinfo(skb)->gso_segs > 1) {
5860 +// TsoLenUpdate(skb->len);
5862 + /* TCP over IPv4 */
5863 + iph = (struct iphdr *)skb_network_header(skb);
5864 +#if defined (CONFIG_RAETH_TSOV6)
5865 + /* TCP over IPv6 */
5866 + ip6h = (struct ipv6hdr *)skb_network_header(skb);
5868 + if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
5869 + th = (struct tcphdr *)skb_transport_header(skb);
5871 + init_cpu_ptr->txd_info4.TSO = 1;
5873 + th->check = htons(skb_shinfo(skb)->gso_size);
5874 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5877 +#if defined (CONFIG_RAETH_TSOV6)
5878 + /* TCP over IPv6 */
5879 + //ip6h = (struct ipv6hdr *)skb_network_header(skb);
5880 + else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
5881 + th = (struct tcphdr *)skb_transport_header(skb);
5882 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5883 + init_cpu_ptr->txd_info4.TSO = 1;
5885 + init_cpu_ptr->txd_info4.TSO = 1;
5887 + th->check = htons(skb_shinfo(skb)->gso_size);
5888 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5894 +// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5896 + init_cpu_ptr->txd_info3.OWN_bit = 0;
5897 +#endif // CONFIG_RAETH_TSO //
5899 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5901 +#ifdef CONFIG_PSEUDO_SUPPORT
5902 + if (gmac_no == 2) {
5903 + if (ei_local->PseudoDev != NULL) {
5904 + pAd = netdev_priv(ei_local->PseudoDev);
5905 + pAd->stat.tx_packets++;
5906 + pAd->stat.tx_bytes += length;
5912 + ei_local->stat.tx_packets++;
5913 + ei_local->stat.tx_bytes += skb->len;
5918 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5920 + END_DEVICE *ei_local = netdev_priv(dev);
5921 + unsigned long flags;
5922 + unsigned int num_of_txd;
5923 +#if defined (CONFIG_RAETH_TSO)
5924 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5926 +#ifdef CONFIG_PSEUDO_SUPPORT
5927 + PSEUDO_ADAPTER *pAd;
5930 +#if !defined(CONFIG_RA_NAT_NONE)
5931 + if(ra_sw_nat_hook_tx!= NULL)
5933 + spin_lock_irqsave(&ei_local->page_lock, flags);
5934 + if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
5935 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5938 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5946 + dev->trans_start = jiffies; /* save the timestamp */
5947 + spin_lock_irqsave(&ei_local->page_lock, flags);
5948 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5951 +//check free_txd_num before calling rt288_eth_send()
5953 +#if defined (CONFIG_RAETH_TSO)
5954 + num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
5959 +#if defined(CONFIG_RALINK_MT7621)
5960 + if(sysRegRead(0xbe00000c)==0x00030101) {
5961 + ei_xmit_housekeeping(0);
5966 + if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
5968 + rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
5969 + if (ei_local->free_txd_num < 3)
5971 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
5972 + netif_stop_queue(dev);
5973 +#ifdef CONFIG_PSEUDO_SUPPORT
5974 + netif_stop_queue(ei_local->PseudoDev);
5980 +#ifdef CONFIG_PSEUDO_SUPPORT
5983 + if (ei_local->PseudoDev != NULL)
5985 + pAd = netdev_priv(ei_local->PseudoDev);
5986 + pAd->stat.tx_dropped++;
5990 + ei_local->stat.tx_dropped++;
5992 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5995 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5999 +void ei_xmit_housekeeping(unsigned long unused)
6001 + struct net_device *dev = dev_raether;
6002 + END_DEVICE *ei_local = netdev_priv(dev);
6003 +#ifndef CONFIG_RAETH_NAPI
6004 + unsigned long reg_int_mask=0;
6006 + struct QDMA_txdesc *dma_ptr = NULL;
6007 + struct QDMA_txdesc *cpu_ptr = NULL;
6008 + struct QDMA_txdesc *tmp_ptr = NULL;
6009 + unsigned int htx_offset = 0;
6011 + dma_ptr = PHYS_TO_VIRT(sysRegRead(QTX_DRX_PTR));
6012 + cpu_ptr = PHYS_TO_VIRT(sysRegRead(QTX_CRX_PTR));
6013 + if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6014 + while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6016 + //1. keep cpu next TXD
6017 + tmp_ptr = PHYS_TO_VIRT(cpu_ptr->txd_info2.NDP);
6018 + htx_offset = GET_TXD_OFFSET(&tmp_ptr);
6019 + //2. free skb meomry
6020 +#if defined (CONFIG_RAETH_TSO)
6021 + if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) {
6022 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6025 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6029 + htx_offset = GET_TXD_OFFSET(&cpu_ptr);
6030 + put_free_txd(htx_offset);
6032 + netif_wake_queue(dev);
6033 +#ifdef CONFIG_PSEUDO_SUPPORT
6034 + netif_wake_queue(ei_local->PseudoDev);
6038 + //4. update cpu_ptr to next ptr
6039 + cpu_ptr = tmp_ptr;
6042 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(cpu_ptr));
6043 +#ifndef CONFIG_RAETH_NAPI
6044 + reg_int_mask=sysRegRead(QFE_INT_ENABLE);
6045 +#if defined (DELAY_INT)
6046 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
6049 + sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
6051 +#endif //CONFIG_RAETH_NAPI//
6054 +EXPORT_SYMBOL(ei_start_xmit);
6055 +EXPORT_SYMBOL(ei_xmit_housekeeping);
6056 +EXPORT_SYMBOL(fe_dma_init);
6057 +EXPORT_SYMBOL(rt2880_eth_send);
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