1 From 810c2afe0c7e1be9352ad512b337110b100bfe3a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 36/57] NET: add mt7621 ethernet driver
7 arch/mips/include/asm/rt2880/board-custom.h | 153 +++
8 arch/mips/include/asm/rt2880/eureka_ep430.h | 204 ++++
9 arch/mips/include/asm/rt2880/generic.h | 42 +
10 arch/mips/include/asm/rt2880/lm.h | 32 +
11 arch/mips/include/asm/rt2880/prom.h | 50 +
12 arch/mips/include/asm/rt2880/rt_mmap.h | 796 ++++++++++++++++
13 arch/mips/include/asm/rt2880/serial_rt2880.h | 443 +++++++++
14 arch/mips/include/asm/rt2880/sizes.h | 52 +
15 arch/mips/include/asm/rt2880/surfboard.h | 70 ++
16 arch/mips/include/asm/rt2880/surfboardint.h | 190 ++++
17 arch/mips/include/asm/rt2880/war.h | 25 +
18 drivers/net/ethernet/Kconfig | 1 +
19 drivers/net/ethernet/Makefile | 1 +
20 drivers/net/ethernet/raeth/Kconfig | 344 +++++++
21 drivers/net/ethernet/raeth/Makefile | 7 +
22 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
23 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
24 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
25 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
26 drivers/net/ethernet/raeth/ra_mac.c | 98 ++
27 drivers/net/ethernet/raeth/ra_mac.h | 35 +
28 drivers/net/ethernet/raeth/raether.c | 693 ++++++++++++++
29 drivers/net/ethernet/raeth/raether.h | 92 ++
30 drivers/net/ethernet/raeth/raether_pdma.c | 212 +++++
31 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
32 25 files changed, 5915 insertions(+)
33 create mode 100644 arch/mips/include/asm/rt2880/board-custom.h
34 create mode 100644 arch/mips/include/asm/rt2880/eureka_ep430.h
35 create mode 100644 arch/mips/include/asm/rt2880/generic.h
36 create mode 100644 arch/mips/include/asm/rt2880/lm.h
37 create mode 100644 arch/mips/include/asm/rt2880/prom.h
38 create mode 100644 arch/mips/include/asm/rt2880/rt_mmap.h
39 create mode 100644 arch/mips/include/asm/rt2880/serial_rt2880.h
40 create mode 100644 arch/mips/include/asm/rt2880/sizes.h
41 create mode 100644 arch/mips/include/asm/rt2880/surfboard.h
42 create mode 100644 arch/mips/include/asm/rt2880/surfboardint.h
43 create mode 100644 arch/mips/include/asm/rt2880/war.h
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
47 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
48 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
49 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
50 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
51 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
52 create mode 100644 drivers/net/ethernet/raeth/raether.c
53 create mode 100644 drivers/net/ethernet/raeth/raether.h
54 create mode 100644 drivers/net/ethernet/raeth/raether_pdma.c
55 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
57 Index: linux-3.14.16/arch/mips/include/asm/rt2880/board-custom.h
58 ===================================================================
59 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
60 +++ linux-3.14.16/arch/mips/include/asm/rt2880/board-custom.h 2014-08-24 15:51:48.530654066 +0200
62 +/* Copyright Statement:
64 + * This software/firmware and related documentation ("MediaTek Software") are
65 + * protected under relevant copyright laws. The information contained herein
66 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
67 + * Without the prior written permission of MediaTek inc. and/or its licensors,
68 + * any reproduction, modification, use or disclosure of MediaTek Software,
69 + * and information contained herein, in whole or in part, shall be strictly prohibited.
71 +/* MediaTek Inc. (C) 2010. All rights reserved.
73 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
74 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
75 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
76 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
77 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
78 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
79 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
80 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
81 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
82 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
83 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
84 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
85 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
86 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
87 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
88 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
89 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
90 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
92 + * The following software/firmware and/or related documentation ("MediaTek Software")
93 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
94 + * applicable license agreements with MediaTek Inc.
97 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
98 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
100 +#include <linux/autoconf.h>
102 +/*=======================================================================*/
104 +/*=======================================================================*/
105 +#ifdef MTK_EMMC_SUPPORT
106 +#define CFG_DEV_MSDC0
108 +#define CFG_DEV_MSDC1
109 +#define CFG_DEV_MSDC2
110 +#define CFG_DEV_MSDC3
111 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
113 +SDIO slot index number used by connectivity combo chip:
114 +0: invalid (used by memory card)
118 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
120 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
124 +/*=======================================================================*/
126 +/*=======================================================================*/
127 +#define CFG_DEV_UART1
128 +#define CFG_DEV_UART2
129 +#define CFG_DEV_UART3
130 +#define CFG_DEV_UART4
132 +#define CFG_UART_PORTS (4)
134 +/*=======================================================================*/
136 +/*=======================================================================*/
138 +//#define CFG_I2C_HIGH_SPEED_MODE
139 +//#define CFG_I2C_DMA_MODE
141 +/*=======================================================================*/
143 +/*=======================================================================*/
144 +#define ADB_SERIAL "E1K"
148 +/*=======================================================================*/
149 +/* MT6575 NAND FLASH */
150 +/*=======================================================================*/
152 +#define RAMDOM_READ 1<<0
153 +#define CACHE_READ 1<<1
154 +/*******************************************************************************
155 + * NFI & ECC Configuration
156 + *******************************************************************************/
159 + u16 id; //deviceid+menuid
165 + u32 timmingsetting;
166 + char devciename[14];
167 + u32 advancedmode; //
168 +}flashdev_info,*pflashdev_info;
170 +static const flashdev_info g_FlashTable[]={
172 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
173 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
174 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
175 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
176 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
178 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
179 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
180 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
181 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
182 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
184 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
185 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
186 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
187 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
189 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
190 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
191 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
192 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
194 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
197 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
198 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
203 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
205 +//uboot only support 1 cs
206 +#define NFI_CS_NUM (2)
207 +#define NFI_DEFAULT_CS (0)
209 +#define USE_AHB_MODE (1)
211 +#define PLATFORM_EVB (1)
213 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
215 Index: linux-3.14.16/arch/mips/include/asm/rt2880/eureka_ep430.h
216 ===================================================================
217 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
218 +++ linux-3.14.16/arch/mips/include/asm/rt2880/eureka_ep430.h 2014-08-24 15:51:48.530654066 +0200
220 +/**************************************************************************
222 + * This program is free software; you can redistribute it and/or modify it
223 + * under the terms of the GNU General Public License as published by the
224 + * Free Software Foundation; either version 2 of the License, or (at your
225 + * option) any later version.
227 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
228 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
229 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
230 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
231 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
232 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
233 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
234 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
235 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
236 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
238 + * You should have received a copy of the GNU General Public License along
239 + * with this program; if not, write to the Free Software Foundation, Inc.,
240 + * 675 Mass Ave, Cambridge, MA 02139, USA.
243 + **************************************************************************
246 +#ifndef _EUREKA_EP430_H
247 +#define _EUREKA_EP430_H
250 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
251 +#include <asm/byteorder.h> /* for cpu_to_le32() */
252 +#include <asm/mach-ralink/rt_mmap.h>
256 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
257 + * bytes when running bigendian.
260 +#define MV_WRITE(ofs, data) \
261 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
262 +#define MV_READ(ofs, data) \
263 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
264 +#define MV_READ_DATA(ofs) \
265 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
267 +#define MV_WRITE_16(ofs, data) \
268 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
269 +#define MV_READ_16(ofs, data) \
270 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
272 +#define MV_WRITE_8(ofs, data) \
273 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
274 +#define MV_READ_8(ofs, data) \
275 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
277 +#define MV_SET_REG_BITS(ofs,bits) \
278 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
279 +#define MV_RESET_REG_BITS(ofs,bits) \
280 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
282 +#define RALINK_PCI_CONFIG_ADDR 0x20
283 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
285 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
286 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
287 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
288 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
289 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
290 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
291 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
292 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
293 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
294 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
295 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
296 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
297 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
298 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
299 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
301 +#elif defined(CONFIG_RALINK_RT3883)
303 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
304 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
305 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
306 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
307 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
308 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
309 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
310 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
316 +#define RT3883_PCI_OFFSET 0x1000
317 +#define RT3883_PCIE_OFFSET 0x2000
319 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
320 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
321 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
322 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
323 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
325 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
326 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
327 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
328 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
329 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
330 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
332 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
334 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
335 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
336 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
337 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
338 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
339 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
340 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
341 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
347 +#define RT6855_PCIE0_OFFSET 0x2000
348 +#define RT6855_PCIE1_OFFSET 0x3000
350 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
351 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
352 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
353 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
354 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
355 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
356 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
357 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
359 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
360 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
361 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
362 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
363 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
364 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
365 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
366 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
368 +#elif defined (CONFIG_RALINK_MT7621)
370 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
371 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
372 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
373 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
374 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
375 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
376 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
377 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
384 +#define RT6855_PCIE0_OFFSET 0x2000
385 +#define RT6855_PCIE1_OFFSET 0x3000
386 +#define RT6855_PCIE2_OFFSET 0x4000
388 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
389 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
390 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
391 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
392 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
393 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
394 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
395 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
397 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
398 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
399 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
400 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
401 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
402 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
403 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
404 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
406 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
407 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
408 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
409 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
410 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
411 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
412 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
413 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
415 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
416 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
418 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
420 +#error "undefined in PCI"
424 Index: linux-3.14.16/arch/mips/include/asm/rt2880/generic.h
425 ===================================================================
426 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
427 +++ linux-3.14.16/arch/mips/include/asm/rt2880/generic.h 2014-08-24 15:51:48.530654066 +0200
430 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
432 + * This program is free software; you can distribute it and/or modify it
433 + * under the terms of the GNU General Public License (Version 2) as
434 + * published by the Free Software Foundation.
436 + * This program is distributed in the hope it will be useful, but WITHOUT
437 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
438 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
439 + * for more details.
441 + * You should have received a copy of the GNU General Public License along
442 + * with this program; if not, write to the Free Software Foundation, Inc.,
443 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
445 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
447 +#ifndef __ASM_SURFBOARD_GENERIC_H
448 +#define __ASM_SURFBOARD_GENERIC_H
450 +#include <asm/addrspace.h>
451 +#include <asm/byteorder.h>
452 +#include <asm/mach-ralink/rt_mmap.h>
457 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
458 +#define GORESET (0x1)
461 + * Power-off register
463 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
464 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
465 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
466 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
467 +#define POWEROFF (0x0) /* drive low */
470 +#endif /* __ASM_SURFBOARD_GENERIC_H */
471 Index: linux-3.14.16/arch/mips/include/asm/rt2880/lm.h
472 ===================================================================
473 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
474 +++ linux-3.14.16/arch/mips/include/asm/rt2880/lm.h 2014-08-24 15:51:48.530654066 +0200
476 +#include <linux/version.h>
480 + struct resource resource;
483 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
489 + struct device_driver drv;
490 + int (*probe)(struct lm_device *);
491 + void (*remove)(struct lm_device *);
492 + int (*suspend)(struct lm_device *, u32);
493 + int (*resume)(struct lm_device *);
496 +int lm_driver_register(struct lm_driver *drv);
497 +void lm_driver_unregister(struct lm_driver *drv);
499 +int lm_device_register(struct lm_device *dev);
501 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
502 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
503 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
505 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
506 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
508 Index: linux-3.14.16/arch/mips/include/asm/rt2880/prom.h
509 ===================================================================
510 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
511 +++ linux-3.14.16/arch/mips/include/asm/rt2880/prom.h 2014-08-24 15:51:48.530654066 +0200
514 + * Carsten Langgaard, carstenl@mips.com
515 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
517 + * ########################################################################
519 + * This program is free software; you can distribute it and/or modify it
520 + * under the terms of the GNU General Public License (Version 2) as
521 + * published by the Free Software Foundation.
523 + * This program is distributed in the hope it will be useful, but WITHOUT
524 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
525 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
526 + * for more details.
528 + * You should have received a copy of the GNU General Public License along
529 + * with this program; if not, write to the Free Software Foundation, Inc.,
530 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
532 + * ########################################################################
534 + * MIPS boards bootprom interface for the Linux kernel.
538 +#ifndef _MIPS_PROM_H
539 +#define _MIPS_PROM_H
541 +extern char *prom_getcmdline(void);
542 +extern char *prom_getenv(char *name);
543 +extern void setup_prom_printf(int tty_no);
544 +extern void prom_setup_printf(int tty_no);
545 +extern void prom_printf(char *fmt, ...);
546 +extern void prom_init_cmdline(void);
547 +extern void prom_meminit(void);
548 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
549 +extern void prom_free_prom_memory (void);
550 +extern void mips_display_message(const char *str);
551 +extern void mips_display_word(unsigned int num);
552 +extern int get_ethernet_addr(char *ethernet_addr);
554 +/* Memory descriptor management. */
555 +#define PROM_MAX_PMEMBLOCKS 32
556 +struct prom_pmemblock {
557 + unsigned long base; /* Within KSEG0. */
558 + unsigned int size; /* In bytes. */
559 + unsigned int type; /* free or prom memory */
562 +#endif /* !(_MIPS_PROM_H) */
563 Index: linux-3.14.16/arch/mips/include/asm/rt2880/rt_mmap.h
564 ===================================================================
565 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
566 +++ linux-3.14.16/arch/mips/include/asm/rt2880/rt_mmap.h 2014-08-24 15:51:48.530654066 +0200
568 +/**************************************************************************
570 + * BRIEF MODULE DESCRIPTION
571 + * register definition for Ralink RT-series SoC
573 + * Copyright 2007 Ralink Inc.
575 + * This program is free software; you can redistribute it and/or modify it
576 + * under the terms of the GNU General Public License as published by the
577 + * Free Software Foundation; either version 2 of the License, or (at your
578 + * option) any later version.
580 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
581 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
582 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
583 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
584 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
585 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
586 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
587 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
588 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
589 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
591 + * You should have received a copy of the GNU General Public License along
592 + * with this program; if not, write to the Free Software Foundation, Inc.,
593 + * 675 Mass Ave, Cambridge, MA 02139, USA.
596 + **************************************************************************
599 +#ifndef __RALINK_MMAP__
600 +#define __RALINK_MMAP__
602 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
604 +#define RALINK_SYSCTL_BASE 0xA0300000
605 +#define RALINK_TIMER_BASE 0xA0300100
606 +#define RALINK_INTCL_BASE 0xA0300200
607 +#define RALINK_MEMCTRL_BASE 0xA0300300
608 +#define RALINK_UART_BASE 0xA0300500
609 +#define RALINK_PIO_BASE 0xA0300600
610 +#define RALINK_I2C_BASE 0xA0300900
611 +#define RALINK_SPI_BASE 0xA0300B00
612 +#define RALINK_UART_LITE_BASE 0xA0300C00
613 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
614 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
615 +#define RALINK_PCI_BASE 0xA0500000
616 +#define RALINK_11N_MAC_BASE 0xA0600000
618 +//Interrupt Controller
619 +#define RALINK_INTCTL_TIMER0 (1<<0)
620 +#define RALINK_INTCTL_WDTIMER (1<<1)
621 +#define RALINK_INTCTL_UART (1<<2)
622 +#define RALINK_INTCTL_PIO (1<<3)
623 +#define RALINK_INTCTL_PCM (1<<4)
624 +#define RALINK_INTCTL_UARTLITE (1<<8)
625 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
627 +//Reset Control Register
628 +#define RALINK_TIMER_RST (1<<1)
629 +#define RALINK_INTC_RST (1<<2)
630 +#define RALINK_MC_RST (1<<3)
631 +#define RALINK_CPU_RST (1<<4)
632 +#define RALINK_UART_RST (1<<5)
633 +#define RALINK_PIO_RST (1<<6)
634 +#define RALINK_I2C_RST (1<<9)
635 +#define RALINK_SPI_RST (1<<11)
636 +#define RALINK_UART2_RST (1<<12)
637 +#define RALINK_PCI_RST (1<<16)
638 +#define RALINK_2860_RST (1<<17)
639 +#define RALINK_FE_RST (1<<18)
640 +#define RALINK_PCM_RST (1<<19)
643 +#elif defined (CONFIG_RALINK_RT2880_MP)
645 +#define RALINK_SYSCTL_BASE 0xA0300000
646 +#define RALINK_TIMER_BASE 0xA0300100
647 +#define RALINK_INTCL_BASE 0xA0300200
648 +#define RALINK_MEMCTRL_BASE 0xA0300300
649 +#define RALINK_UART_BASE 0xA0300500
650 +#define RALINK_PIO_BASE 0xA0300600
651 +#define RALINK_I2C_BASE 0xA0300900
652 +#define RALINK_SPI_BASE 0xA0300B00
653 +#define RALINK_UART_LITE_BASE 0x00300C00
654 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
655 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
656 +#define RALINK_PCI_BASE 0xA0440000
657 +#define RALINK_11N_MAC_BASE 0xA0480000
659 +//Interrupt Controller
660 +#define RALINK_INTCTL_TIMER0 (1<<0)
661 +#define RALINK_INTCTL_WDTIMER (1<<1)
662 +#define RALINK_INTCTL_UART (1<<2)
663 +#define RALINK_INTCTL_PIO (1<<3)
664 +#define RALINK_INTCTL_PCM (1<<4)
665 +#define RALINK_INTCTL_UARTLITE (1<<8)
666 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
668 +//Reset Control Register
669 +#define RALINK_TIMER_RST (1<<1)
670 +#define RALINK_INTC_RST (1<<2)
671 +#define RALINK_MC_RST (1<<3)
672 +#define RALINK_CPU_RST (1<<4)
673 +#define RALINK_UART_RST (1<<5)
674 +#define RALINK_PIO_RST (1<<6)
675 +#define RALINK_I2C_RST (1<<9)
676 +#define RALINK_SPI_RST (1<<11)
677 +#define RALINK_UART2_RST (1<<12)
678 +#define RALINK_PCI_RST (1<<16)
679 +#define RALINK_2860_RST (1<<17)
680 +#define RALINK_FE_RST (1<<18)
681 +#define RALINK_PCM_RST (1<<19)
683 +#elif defined (CONFIG_RALINK_RT3052)
685 +#define RALINK_SYSCTL_BASE 0xB0000000
686 +#define RALINK_TIMER_BASE 0xB0000100
687 +#define RALINK_INTCL_BASE 0xB0000200
688 +#define RALINK_MEMCTRL_BASE 0xB0000300
689 +#define RALINK_PCM_BASE 0xB0000400
690 +#define RALINK_UART_BASE 0x10000500
691 +#define RALINK_PIO_BASE 0xB0000600
692 +#define RALINK_GDMA_BASE 0xB0000700
693 +#define RALINK_NAND_CTRL_BASE 0xB0000800
694 +#define RALINK_I2C_BASE 0xB0000900
695 +#define RALINK_I2S_BASE 0xB0000A00
696 +#define RALINK_SPI_BASE 0xB0000B00
697 +#define RALINK_UART_LITE_BASE 0x10000C00
698 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
699 +#define RALINK_ETH_SW_BASE 0xB0110000
700 +#define RALINK_11N_MAC_BASE 0xB0180000
701 +#define RALINK_USB_OTG_BASE 0x101C0000
703 +//Interrupt Controller
704 +#define RALINK_INTCTL_SYSCTL (1<<0)
705 +#define RALINK_INTCTL_TIMER0 (1<<1)
706 +#define RALINK_INTCTL_WDTIMER (1<<2)
707 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
708 +#define RALINK_INTCTL_PCM (1<<4)
709 +#define RALINK_INTCTL_UART (1<<5)
710 +#define RALINK_INTCTL_PIO (1<<6)
711 +#define RALINK_INTCTL_DMA (1<<7)
712 +#define RALINK_INTCTL_NAND (1<<8)
713 +#define RALINK_INTCTL_PC (1<<9)
714 +#define RALINK_INTCTL_I2S (1<<10)
715 +#define RALINK_INTCTL_UARTLITE (1<<12)
716 +#define RALINK_INTCTL_ESW (1<<17)
717 +#define RALINK_INTCTL_OTG (1<<18)
718 +#define RALINK_INTCTL_OTG_IRQN 18
719 +#define RALINK_INTCTL_GLOBAL (1<<31)
721 +//Reset Control Register
722 +#define RALINK_SYS_RST (1<<0)
723 +#define RALINK_CPU_RST (1<<1)
724 +#define RALINK_TIMER_RST (1<<8)
725 +#define RALINK_INTC_RST (1<<9)
726 +#define RALINK_MC_RST (1<<10)
727 +#define RALINK_PCM_RST (1<<11)
728 +#define RALINK_UART_RST (1<<12)
729 +#define RALINK_PIO_RST (1<<13)
730 +#define RALINK_DMA_RST (1<<14)
731 +#define RALINK_I2C_RST (1<<16)
732 +#define RALINK_I2S_RST (1<<17)
733 +#define RALINK_SPI_RST (1<<18)
734 +#define RALINK_UARTL_RST (1<<19)
735 +#define RALINK_RT2872_RST (1<<20)
736 +#define RALINK_FE_RST (1<<21)
737 +#define RALINK_OTG_RST (1<<22)
738 +#define RALINK_SW_RST (1<<23)
739 +#define RALINK_EPHY_RST (1<<24)
741 +#elif defined (CONFIG_RALINK_RT3352)
743 +#define RALINK_SYSCTL_BASE 0xB0000000
744 +#define RALINK_TIMER_BASE 0xB0000100
745 +#define RALINK_INTCL_BASE 0xB0000200
746 +#define RALINK_MEMCTRL_BASE 0xB0000300
747 +#define RALINK_UART_BASE 0x10000500
748 +#define RALINK_PIO_BASE 0xB0000600
749 +#define RALINK_I2C_BASE 0xB0000900
750 +#define RALINK_I2S_BASE 0xB0000A00
751 +#define RALINK_SPI_BASE 0xB0000B00
752 +#define RALINK_NAND_CTRL_BASE 0xB0000800
753 +#define RALINK_UART_LITE_BASE 0x10000C00
754 +#define RALINK_PCM_BASE 0xB0002000
755 +#define RALINK_GDMA_BASE 0xB0002800
756 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
757 +#define RALINK_ETH_SW_BASE 0xB0110000
758 +#define RALINK_USB_DEV_BASE 0x10120000
759 +#define RALINK_11N_MAC_BASE 0xB0180000
760 +#define RALINK_USB_HOST_BASE 0x101C0000
762 +#define RALINK_MCNT_CFG 0xB0000D00
763 +#define RALINK_COMPARE 0xB0000D04
764 +#define RALINK_COUNT 0xB0000D08
766 +//Interrupt Controller
767 +#define RALINK_INTCTL_SYSCTL (1<<0)
768 +#define RALINK_INTCTL_TIMER0 (1<<1)
769 +#define RALINK_INTCTL_WDTIMER (1<<2)
770 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
771 +#define RALINK_INTCTL_PCM (1<<4)
772 +#define RALINK_INTCTL_UART (1<<5)
773 +#define RALINK_INTCTL_PIO (1<<6)
774 +#define RALINK_INTCTL_DMA (1<<7)
775 +#define RALINK_INTCTL_PC (1<<9)
776 +#define RALINK_INTCTL_I2S (1<<10)
777 +#define RALINK_INTCTL_UARTLITE (1<<12)
778 +#define RALINK_INTCTL_ESW (1<<17)
779 +#define RALINK_INTCTL_OTG (1<<18)
780 +#define RALINK_INTCTL_GLOBAL (1<<31)
782 +//Reset Control Register
783 +#define RALINK_SYS_RST (1<<0)
784 +#define RALINK_TIMER_RST (1<<8)
785 +#define RALINK_INTC_RST (1<<9)
786 +#define RALINK_MC_RST (1<<10)
787 +#define RALINK_PCM_RST (1<<11)
788 +#define RALINK_UART_RST (1<<12)
789 +#define RALINK_PIO_RST (1<<13)
790 +#define RALINK_DMA_RST (1<<14)
791 +#define RALINK_I2C_RST (1<<16)
792 +#define RALINK_I2S_RST (1<<17)
793 +#define RALINK_SPI_RST (1<<18)
794 +#define RALINK_UARTL_RST (1<<19)
795 +#define RALINK_WLAN_RST (1<<20)
796 +#define RALINK_FE_RST (1<<21)
797 +#define RALINK_UHST_RST (1<<22)
798 +#define RALINK_ESW_RST (1<<23)
799 +#define RALINK_EPHY_RST (1<<24)
800 +#define RALINK_UDEV_RST (1<<25)
803 +//Clock Conf Register
804 +#define RALINK_UPHY1_CLK_EN (1<<20)
805 +#define RALINK_UPHY0_CLK_EN (1<<18)
806 +#define RALINK_GE1_CLK_EN (1<<16)
809 +#elif defined (CONFIG_RALINK_RT5350)
811 +#define RALINK_SYSCTL_BASE 0xB0000000
812 +#define RALINK_TIMER_BASE 0xB0000100
813 +#define RALINK_INTCL_BASE 0xB0000200
814 +#define RALINK_MEMCTRL_BASE 0xB0000300
815 +#define RALINK_UART_BASE 0x10000500
816 +#define RALINK_PIO_BASE 0xB0000600
817 +#define RALINK_I2C_BASE 0xB0000900
818 +#define RALINK_I2S_BASE 0xB0000A00
819 +#define RALINK_SPI_BASE 0xB0000B00
820 +#define RALINK_UART_LITE_BASE 0x10000C00
821 +#define RALINK_PCM_BASE 0xB0002000
822 +#define RALINK_GDMA_BASE 0xB0002800
823 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
824 +#define RALINK_ETH_SW_BASE 0xB0110000
825 +#define RALINK_USB_DEV_BASE 0x10120000
826 +#define RALINK_11N_MAC_BASE 0xB0180000
827 +#define RALINK_USB_HOST_BASE 0x101C0000
829 +#define RALINK_MCNT_CFG 0xB0000D00
830 +#define RALINK_COMPARE 0xB0000D04
831 +#define RALINK_COUNT 0xB0000D08
833 +//Interrupt Controller
834 +#define RALINK_INTCTL_SYSCTL (1<<0)
835 +#define RALINK_INTCTL_TIMER0 (1<<1)
836 +#define RALINK_INTCTL_WDTIMER (1<<2)
837 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
838 +#define RALINK_INTCTL_PCM (1<<4)
839 +#define RALINK_INTCTL_UART (1<<5)
840 +#define RALINK_INTCTL_PIO (1<<6)
841 +#define RALINK_INTCTL_DMA (1<<7)
842 +#define RALINK_INTCTL_PC (1<<9)
843 +#define RALINK_INTCTL_I2S (1<<10)
844 +#define RALINK_INTCTL_UARTLITE (1<<12)
845 +#define RALINK_INTCTL_ESW (1<<17)
846 +#define RALINK_INTCTL_USB_HOST (1<<18)
847 +#define RALINK_INTCTL_USB_DEV (1<<19)
848 +#define RALINK_INTCTL_GLOBAL (1<<31)
850 +//Reset Control Register
851 +#define RALINK_SYS_RST (1<<0)
852 +#define RALINK_TIMER_RST (1<<8)
853 +#define RALINK_INTC_RST (1<<9)
854 +#define RALINK_MC_RST (1<<10)
855 +#define RALINK_PCM_RST (1<<11)
856 +#define RALINK_UART_RST (1<<12)
857 +#define RALINK_PIO_RST (1<<13)
858 +#define RALINK_DMA_RST (1<<14)
859 +#define RALINK_I2C_RST (1<<16)
860 +#define RALINK_I2S_RST (1<<17)
861 +#define RALINK_SPI_RST (1<<18)
862 +#define RALINK_UARTL_RST (1<<19)
863 +#define RALINK_WLAN_RST (1<<20)
864 +#define RALINK_FE_RST (1<<21)
865 +#define RALINK_UHST_RST (1<<22)
866 +#define RALINK_ESW_RST (1<<23)
867 +#define RALINK_EPHY_RST (1<<24)
868 +#define RALINK_UDEV_RST (1<<25)
869 +#define RALINK_MIPSC_RST (1<<28)
871 +//Clock Conf Register
872 +#define RALINK_UPHY0_CLK_EN (1<<18)
873 +#define RALINK_GE1_CLK_EN (1<<16)
875 +#elif defined (CONFIG_RALINK_RT2883)
877 +#define RALINK_SYSCTL_BASE 0xB0000000
878 +#define RALINK_TIMER_BASE 0xB0000100
879 +#define RALINK_INTCL_BASE 0xB0000200
880 +#define RALINK_MEMCTRL_BASE 0xB0000300
881 +#define RALINK_PCM_BASE 0xB0000400
882 +#define RALINK_UART_BASE 0x10000500
883 +#define RALINK_PIO_BASE 0xB0000600
884 +#define RALINK_GDMA_BASE 0xB0000700
885 +#define RALINK_NAND_CTRL_BASE 0xB0000800
886 +#define RALINK_I2C_BASE 0xB0000900
887 +#define RALINK_I2S_BASE 0xB0000A00
888 +#define RALINK_SPI_BASE 0xB0000B00
889 +#define RALINK_UART_LITE_BASE 0x10000C00
890 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
891 +#define RALINK_PCI_BASE 0xB0140000
892 +#define RALINK_11N_MAC_BASE 0xB0180000
893 +#define RALINK_USB_OTG_BASE 0x101C0000
895 +//Interrupt Controller
896 +#define RALINK_INTCTL_SYSCTL (1<<0)
897 +#define RALINK_INTCTL_TIMER0 (1<<1)
898 +#define RALINK_INTCTL_WDTIMER (1<<2)
899 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
900 +#define RALINK_INTCTL_PCM (1<<4)
901 +#define RALINK_INTCTL_UART (1<<5)
902 +#define RALINK_INTCTL_PIO (1<<6)
903 +#define RALINK_INTCTL_DMA (1<<7)
904 +#define RALINK_INTCTL_NAND (1<<8)
905 +#define RALINK_INTCTL_PC (1<<9)
906 +#define RALINK_INTCTL_I2S (1<<10)
907 +#define RALINK_INTCTL_UARTLITE (1<<12)
908 +#define RALINK_INTCTL_OTG (1<<18)
909 +#define RALINK_INTCTL_OTG_IRQN 18
910 +#define RALINK_INTCTL_GLOBAL (1<<31)
912 +//Reset Control Register
913 +#define RALINK_SYS_RST (1<<0)
914 +#define RALINK_CPU_RST (1<<1)
915 +#define RALINK_TIMER_RST (1<<8)
916 +#define RALINK_INTC_RST (1<<9)
917 +#define RALINK_MC_RST (1<<10)
918 +#define RALINK_PCM_RST (1<<11)
919 +#define RALINK_UART_RST (1<<12)
920 +#define RALINK_PIO_RST (1<<13)
921 +#define RALINK_DMA_RST (1<<14)
922 +#define RALINK_I2C_RST (1<<16)
923 +#define RALINK_I2S_RST (1<<17)
924 +#define RALINK_SPI_RST (1<<18)
925 +#define RALINK_UARTL_RST (1<<19)
926 +#define RALINK_WLAN_RST (1<<20)
927 +#define RALINK_FE_RST (1<<21)
928 +#define RALINK_OTG_RST (1<<22)
929 +#define RALINK_PCIE_RST (1<<23)
931 +#elif defined (CONFIG_RALINK_RT3883)
933 +#define RALINK_SYSCTL_BASE 0xB0000000
934 +#define RALINK_TIMER_BASE 0xB0000100
935 +#define RALINK_INTCL_BASE 0xB0000200
936 +#define RALINK_MEMCTRL_BASE 0xB0000300
937 +#define RALINK_UART_BASE 0x10000500
938 +#define RALINK_PIO_BASE 0xB0000600
939 +#define RALINK_NOR_CTRL_BASE 0xB0000700
940 +#define RALINK_NAND_CTRL_BASE 0xB0000810
941 +#define RALINK_I2C_BASE 0xB0000900
942 +#define RALINK_I2S_BASE 0xB0000A00
943 +#define RALINK_SPI_BASE 0xB0000B00
944 +#define RALINK_UART_LITE_BASE 0x10000C00
945 +#define RALINK_PCM_BASE 0xB0002000
946 +#define RALINK_GDMA_BASE 0xB0002800
947 +#define RALINK_CODEC1_BASE 0xB0003000
948 +#define RALINK_CODEC2_BASE 0xB0003800
949 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
950 +#define RALINK_USB_DEV_BASE 0x10120000
951 +#define RALINK_PCI_BASE 0xB0140000
952 +#define RALINK_11N_MAC_BASE 0xB0180000
953 +#define RALINK_USB_HOST_BASE 0x101C0000
954 +#define RALINK_PCIE_BASE 0xB0200000
956 +//Interrupt Controller
957 +#define RALINK_INTCTL_SYSCTL (1<<0)
958 +#define RALINK_INTCTL_TIMER0 (1<<1)
959 +#define RALINK_INTCTL_WDTIMER (1<<2)
960 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
961 +#define RALINK_INTCTL_PCM (1<<4)
962 +#define RALINK_INTCTL_UART (1<<5)
963 +#define RALINK_INTCTL_PIO (1<<6)
964 +#define RALINK_INTCTL_DMA (1<<7)
965 +#define RALINK_INTCTL_NAND (1<<8)
966 +#define RALINK_INTCTL_PC (1<<9)
967 +#define RALINK_INTCTL_I2S (1<<10)
968 +#define RALINK_INTCTL_UARTLITE (1<<12)
969 +#define RALINK_INTCTL_UHST (1<<18)
970 +#define RALINK_INTCTL_UDEV (1<<19)
972 +//Reset Control Register
973 +#define RALINK_SYS_RST (1<<0)
974 +#define RALINK_TIMER_RST (1<<8)
975 +#define RALINK_INTC_RST (1<<9)
976 +#define RALINK_MC_RST (1<<10)
977 +#define RALINK_PCM_RST (1<<11)
978 +#define RALINK_UART_RST (1<<12)
979 +#define RALINK_PIO_RST (1<<13)
980 +#define RALINK_DMA_RST (1<<14)
981 +#define RALINK_NAND_RST (1<<15)
982 +#define RALINK_I2C_RST (1<<16)
983 +#define RALINK_I2S_RST (1<<17)
984 +#define RALINK_SPI_RST (1<<18)
985 +#define RALINK_UARTL_RST (1<<19)
986 +#define RALINK_WLAN_RST (1<<20)
987 +#define RALINK_FE_RST (1<<21)
988 +#define RALINK_UHST_RST (1<<22)
989 +#define RALINK_PCIE_RST (1<<23)
990 +#define RALINK_PCI_RST (1<<24)
991 +#define RALINK_UDEV_RST (1<<25)
992 +#define RALINK_FLASH_RST (1<<26)
994 +//Clock Conf Register
995 +#define RALINK_UPHY1_CLK_EN (1<<20)
996 +#define RALINK_UPHY0_CLK_EN (1<<18)
997 +#define RALINK_GE1_CLK_EN (1<<16)
999 +#elif defined (CONFIG_RALINK_RT6855)
1001 +#define RALINK_SYSCTL_BASE 0xB0000000
1002 +#define RALINK_TIMER_BASE 0xB0000100
1003 +#define RALINK_INTCL_BASE 0xB0000200
1004 +#define RALINK_MEMCTRL_BASE 0xB0000300
1005 +#define RALINK_UART_BASE 0x10000500
1006 +#define RALINK_PIO_BASE 0xB0000600
1007 +#define RALINK_I2C_BASE 0xB0000900
1008 +#define RALINK_I2S_BASE 0xB0000A00
1009 +#define RALINK_SPI_BASE 0xB0000B00
1010 +#define RALINK_NAND_CTRL_BASE 0xB0000800
1011 +#define RALINK_UART_LITE_BASE 0x10000C00
1012 +#define RALINK_PCM_BASE 0xB0002000
1013 +#define RALINK_GDMA_BASE 0xB0002800
1014 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1015 +#define RALINK_ETH_SW_BASE 0xB0110000
1016 +#define RALINK_PCI_BASE 0xB0140000
1017 +#define RALINK_USB_DEV_BASE 0x10120000
1018 +#define RALINK_11N_MAC_BASE 0xB0180000
1019 +#define RALINK_USB_HOST_BASE 0x101C0000
1021 +#define RALINK_MCNT_CFG 0xB0000D00
1022 +#define RALINK_COMPARE 0xB0000D04
1023 +#define RALINK_COUNT 0xB0000D08
1025 +//Interrupt Controller
1026 +#define RALINK_INTCTL_SYSCTL (1<<0)
1027 +#define RALINK_INTCTL_TIMER0 (1<<1)
1028 +#define RALINK_INTCTL_WDTIMER (1<<2)
1029 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1030 +#define RALINK_INTCTL_PCM (1<<4)
1031 +#define RALINK_INTCTL_UART (1<<5)
1032 +#define RALINK_INTCTL_PIO (1<<6)
1033 +#define RALINK_INTCTL_DMA (1<<7)
1034 +#define RALINK_INTCTL_PC (1<<9)
1035 +#define RALINK_INTCTL_I2S (1<<10)
1036 +#define RALINK_INTCTL_UARTLITE (1<<12)
1037 +#define RALINK_INTCTL_ESW (1<<17)
1038 +#define RALINK_INTCTL_OTG (1<<18)
1039 +#define RALINK_INTCTL_GLOBAL (1<<31)
1041 +//Reset Control Register
1042 +#define RALINK_SYS_RST (1<<0)
1043 +#define RALINK_TIMER_RST (1<<8)
1044 +#define RALINK_INTC_RST (1<<9)
1045 +#define RALINK_MC_RST (1<<10)
1046 +#define RALINK_PCM_RST (1<<11)
1047 +#define RALINK_UART_RST (1<<12)
1048 +#define RALINK_PIO_RST (1<<13)
1049 +#define RALINK_DMA_RST (1<<14)
1050 +#define RALINK_I2C_RST (1<<16)
1051 +#define RALINK_I2S_RST (1<<17)
1052 +#define RALINK_SPI_RST (1<<18)
1053 +#define RALINK_UARTL_RST (1<<19)
1054 +#define RALINK_FE_RST (1<<21)
1055 +#define RALINK_UHST_RST (1<<22)
1056 +#define RALINK_ESW_RST (1<<23)
1057 +#define RALINK_EPHY_RST (1<<24)
1058 +#define RALINK_UDEV_RST (1<<25)
1059 +#define RALINK_PCIE0_RST (1<<26)
1060 +#define RALINK_PCIE1_RST (1<<27)
1062 +//Clock Conf Register
1063 +#define RALINK_UPHY0_CLK_EN (1<<25)
1064 +#define RALINK_PCIE0_CLK_EN (1<<26)
1065 +#define RALINK_PCIE1_CLK_EN (1<<27)
1068 +#elif defined (CONFIG_RALINK_MT7620)
1070 +#define RALINK_SYSCTL_BASE 0xB0000000
1071 +#define RALINK_TIMER_BASE 0xB0000100
1072 +#define RALINK_INTCL_BASE 0xB0000200
1073 +#define RALINK_MEMCTRL_BASE 0xB0000300
1074 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1075 +#define RALINK_UART_BASE 0x10000500
1076 +#define RALINK_PIO_BASE 0xB0000600
1077 +#define RALINK_NAND_CTRL_BASE 0xB0000810
1078 +#define RALINK_I2C_BASE 0xB0000900
1079 +#define RALINK_I2S_BASE 0xB0000A00
1080 +#define RALINK_SPI_BASE 0xB0000B00
1081 +#define RALINK_UART_LITE_BASE 0x10000C00
1082 +#define RALINK_MIPS_CNT_BASE 0x10000D00
1083 +#define RALINK_PCM_BASE 0xB0002000
1084 +#define RALINK_GDMA_BASE 0xB0002800
1085 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
1086 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1087 +#define RALINK_PPE_BASE 0xB0100C00
1088 +#define RALINK_ETH_SW_BASE 0xB0110000
1089 +#define RALINK_USB_DEV_BASE 0x10120000
1090 +#define RALINK_MSDC_BASE 0xB0130000
1091 +#define RALINK_PCI_BASE 0xB0140000
1092 +#define RALINK_11N_MAC_BASE 0xB0180000
1093 +#define RALINK_USB_HOST_BASE 0x101C0000
1095 +#define RALINK_MCNT_CFG 0xB0000D00
1096 +#define RALINK_COMPARE 0xB0000D04
1097 +#define RALINK_COUNT 0xB0000D08
1099 +//Interrupt Controller
1100 +#define RALINK_INTCTL_SYSCTL (1<<0)
1101 +#define RALINK_INTCTL_TIMER0 (1<<1)
1102 +#define RALINK_INTCTL_WDTIMER (1<<2)
1103 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1104 +#define RALINK_INTCTL_PCM (1<<4)
1105 +#define RALINK_INTCTL_UART (1<<5)
1106 +#define RALINK_INTCTL_PIO (1<<6)
1107 +#define RALINK_INTCTL_DMA (1<<7)
1108 +#define RALINK_INTCTL_PC (1<<9)
1109 +#define RALINK_INTCTL_I2S (1<<10)
1110 +#define RALINK_INTCTL_SPI (1<<11)
1111 +#define RALINK_INTCTL_UARTLITE (1<<12)
1112 +#define RALINK_INTCTL_CRYPTO (1<<13)
1113 +#define RALINK_INTCTL_ESW (1<<17)
1114 +#define RALINK_INTCTL_UHST (1<<18)
1115 +#define RALINK_INTCTL_UDEV (1<<19)
1116 +#define RALINK_INTCTL_GLOBAL (1<<31)
1118 +//Reset Control Register
1119 +#define RALINK_SYS_RST (1<<0)
1120 +#define RALINK_TIMER_RST (1<<8)
1121 +#define RALINK_INTC_RST (1<<9)
1122 +#define RALINK_MC_RST (1<<10)
1123 +#define RALINK_PCM_RST (1<<11)
1124 +#define RALINK_UART_RST (1<<12)
1125 +#define RALINK_PIO_RST (1<<13)
1126 +#define RALINK_DMA_RST (1<<14)
1127 +#define RALINK_I2C_RST (1<<16)
1128 +#define RALINK_I2S_RST (1<<17)
1129 +#define RALINK_SPI_RST (1<<18)
1130 +#define RALINK_UARTL_RST (1<<19)
1131 +#define RALINK_FE_RST (1<<21)
1132 +#define RALINK_UHST_RST (1<<22)
1133 +#define RALINK_ESW_RST (1<<23)
1134 +#define RALINK_EPHY_RST (1<<24)
1135 +#define RALINK_UDEV_RST (1<<25)
1136 +#define RALINK_PCIE0_RST (1<<26)
1137 +#define RALINK_PCIE1_RST (1<<27)
1138 +#define RALINK_MIPS_CNT_RST (1<<28)
1139 +#define RALINK_CRYPTO_RST (1<<29)
1141 +//Clock Conf Register
1142 +#define RALINK_UPHY0_CLK_EN (1<<25)
1143 +#define RALINK_UPHY1_CLK_EN (1<<22)
1144 +#define RALINK_PCIE0_CLK_EN (1<<26)
1145 +#define RALINK_PCIE1_CLK_EN (1<<27)
1147 +//CPU PLL CFG Register
1148 +#define CPLL_SW_CONFIG (0x1UL << 31)
1149 +#define CPLL_MULT_RATIO_SHIFT 16
1150 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1151 +#define CPLL_DIV_RATIO_SHIFT 10
1152 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1153 +#define BASE_CLOCK 40 /* Mhz */
1155 +#elif defined (CONFIG_RALINK_MT7621)
1157 +#define RALINK_SYSCTL_BASE 0xBE000000
1158 +#define RALINK_TIMER_BASE 0xBE000100
1159 +#define RALINK_INTCL_BASE 0xBE000200
1160 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
1161 +#define RALINK_MIPS_CNT_BASE 0x1E000500
1162 +#define RALINK_PIO_BASE 0xBE000600
1163 +#define RALINK_SPDIF_BASE 0xBE000700
1164 +#define RALINK_I2C_BASE 0xBE000900
1165 +#define RALINK_I2S_BASE 0xBE000A00
1166 +#define RALINK_SPI_BASE 0xBE000B00
1167 +#define RALINK_UART_LITE1_BASE 0x1E000C00
1168 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1169 +#define RALINK_UART_LITE2_BASE 0x1E000D00
1170 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1171 +#define RALINK_UART_LITE3_BASE 0x1E000E00
1172 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
1173 +#define RALINK_PCM_BASE 0xBE002000
1174 +#define RALINK_GDMA_BASE 0xBE002800
1175 +#define RALINK_NAND_CTRL_BASE 0xBE003000
1176 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
1177 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
1178 +#define RALINK_MEMCTRL_BASE 0xBE005000
1179 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
1180 +#define RALINK_HS_DMA_BASE 0xBE007000
1181 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
1182 +#define RALINK_PPE_BASE 0xBE100C00
1183 +#define RALINK_ETH_SW_BASE 0xBE110000
1184 +#define RALINK_ROM_BASE 0xBE118000
1185 +#define RALINK_MSDC_BASE 0xBE130000
1186 +#define RALINK_PCI_BASE 0xBE140000
1187 +#define RALINK_USB_HOST_BASE 0x1E1C0000
1188 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
1190 +#define RALINK_MCNT_CFG 0xBE000500
1191 +#define RALINK_COMPARE 0xBE000504
1192 +#define RALINK_COUNT 0xBE000508
1194 +//Interrupt Controller
1195 +#define RALINK_INTCTL_FE (1<<3)
1196 +#define RALINK_INTCTL_PCIE0 (1<<4)
1197 +#define RALINK_INTCTL_SYSCTL (1<<6)
1198 +#define RALINK_INTCTL_I2C (1<<8)
1199 +#define RALINK_INTCTL_DRAMC (1<<9)
1200 +#define RALINK_INTCTL_PCM (1<<10)
1201 +#define RALINK_INTCTL_HSDMA (1<<11)
1202 +#define RALINK_INTCTL_PIO (1<<12)
1203 +#define RALINK_INTCTL_DMA (1<<13)
1204 +#define RALINK_INTCTL_NFI (1<<14)
1205 +#define RALINK_INTCTL_NFIECC (1<<15)
1206 +#define RALINK_INTCTL_I2S (1<<16)
1207 +#define RALINK_INTCTL_SPI (1<<17)
1208 +#define RALINK_INTCTL_SPDIF (1<<18)
1209 +#define RALINK_INTCTL_CRYPTO (1<<19)
1210 +#define RALINK_INTCTL_SDXC (1<<20)
1211 +#define RALINK_INTCTL_PCTRL (1<<21)
1212 +#define RALINK_INTCTL_USB (1<<22)
1213 +#define RALINK_INTCTL_SWITCH (1<<23)
1214 +#define RALINK_INTCTL_PCIE1 (1<<24)
1215 +#define RALINK_INTCTL_PCIE2 (1<<25)
1216 +#define RALINK_INTCTL_UART1 (1<<26)
1217 +#define RALINK_INTCTL_UART2 (1<<27)
1218 +#define RALINK_INTCTL_UART3 (1<<28)
1219 +#define RALINK_INTCTL_WDTIMER (1<<29)
1220 +#define RALINK_INTCTL_TIMER0 (1<<30)
1221 +#define RALINK_INTCTL_TIMER1 (1<<31)
1224 +//Reset Control Register
1225 +#define RALINK_SYS_RST (1<<0)
1226 +#define RALINK_MCM_RST (1<<1)
1227 +#define RALINK_HSDMA_RST (1<<2)
1228 +#define RALINK_FE_RST (1<<6)
1229 +#define RALINK_SPDIF_RST (1<<7)
1230 +#define RALINK_TIMER_RST (1<<8)
1231 +#define RALINK_INTC_RST (1<<9)
1232 +#define RALINK_MC_RST (1<<10)
1233 +#define RALINK_PCM_RST (1<<11)
1234 +#define RALINK_PIO_RST (1<<13)
1235 +#define RALINK_DMA_RST (1<<14)
1236 +#define RALINK_NAND_RST (1<<15)
1237 +#define RALINK_I2C_RST (1<<16)
1238 +#define RALINK_I2S_RST (1<<17)
1239 +#define RALINK_SPI_RST (1<<18)
1240 +#define RALINK_UART1_RST (1<<19)
1241 +#define RALINK_UART2_RST (1<<20)
1242 +#define RALINK_UART3_RST (1<<21)
1243 +#define RALINK_ETH_RST (1<<23)
1244 +#define RALINK_PCIE0_RST (1<<24)
1245 +#define RALINK_PCIE1_RST (1<<25)
1246 +#define RALINK_PCIE2_RST (1<<26)
1247 +#define RALINK_AUX_STCK_RST (1<<28)
1248 +#define RALINK_CRYPTO_RST (1<<29)
1249 +#define RALINK_SDXC_RST (1<<30)
1250 +#define RALINK_PPE_RST (1<<31)
1252 +//Clock Conf Register
1253 +#define RALINK_PCIE0_CLK_EN (1<<24)
1254 +#define RALINK_PCIE1_CLK_EN (1<<25)
1255 +#define RALINK_PCIE2_CLK_EN (1<<26)
1256 +//#define RALINK_UPHY0_CLK_EN (1<<27)
1257 +//#define RALINK_UPHY1_CLK_EN (1<<28)
1259 +//CPU PLL CFG Register
1260 +#define CPLL_SW_CONFIG (0x1UL << 31)
1261 +#define CPLL_MULT_RATIO_SHIFT 16
1262 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1263 +#define CPLL_DIV_RATIO_SHIFT 10
1264 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1265 +#define BASE_CLOCK 40 /* Mhz */
1267 +#define RALINK_TESTSTAT 0xBE000018
1268 +#define RALINK_TESTSTAT2 0xBE00001C
1270 +#elif defined (CONFIG_RALINK_MT7628)
1272 +#define RALINK_SYSCTL_BASE 0xB0000000
1273 +#define RALINK_TIMER_BASE 0xB0000100
1274 +#define RALINK_INTCL_BASE 0xB0000200
1275 +#define RALINK_MEMCTRL_BASE 0xB0000300
1276 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1277 +#define RALINK_MIPS_CNT_BASE 0x10000500
1278 +#define RALINK_PIO_BASE 0xB0000600
1279 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
1280 +#define RALINK_I2C_BASE 0xB0000900
1281 +#define RALINK_I2S_BASE 0xB0000A00
1282 +#define RALINK_SPI_BASE 0xB0000B00
1283 +#define RALINK_UART_LITE1_BASE 0x10000C00
1284 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1285 +#define RALINK_UART_LITE2_BASE 0x10000D00
1286 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1287 +#define RALINK_UART_LITE3_BASE 0x10000E00
1288 +#define RALINK_PCM_BASE 0xB0002000
1289 +#define RALINK_GDMA_BASE 0xB0002800
1290 +#define RALINK_AES_ENGINE_BASE 0xB0004000
1291 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
1292 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1293 +#define RALINK_PPE_BASE 0xB0100C00
1294 +#define RALINK_ETH_SW_BASE 0xB0110000
1295 +#define RALINK_USB_DEV_BASE 0xB0120000
1296 +#define RALINK_MSDC_BASE 0xB0130000
1297 +#define RALINK_PCI_BASE 0xB0140000
1298 +#define RALINK_11N_MAC_BASE 0xB0180000
1299 +#define RALINK_USB_HOST_BASE 0x101C0000
1301 +#define RALINK_MCNT_CFG 0xB0000500
1302 +#define RALINK_COMPARE 0xB0000504
1303 +#define RALINK_COUNT 0xB0000508
1306 +//Interrupt Controller
1307 +#define RALINK_INTCTL_SYSCTL (1<<0)
1308 +#define RALINK_INTCTL_TIMER0 (1<<1)
1309 +#define RALINK_INTCTL_WDTIMER (1<<2)
1310 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1311 +#define RALINK_INTCTL_PCM (1<<4)
1312 +#define RALINK_INTCTL_UART (1<<5)
1313 +#define RALINK_INTCTL_PIO (1<<6)
1314 +#define RALINK_INTCTL_DMA (1<<7)
1315 +#define RALINK_INTCTL_PC (1<<9)
1316 +#define RALINK_INTCTL_I2S (1<<10)
1317 +#define RALINK_INTCTL_SPI (1<<11)
1318 +#define RALINK_INTCTL_UARTLITE (1<<12)
1319 +#define RALINK_INTCTL_CRYPTO (1<<13)
1320 +#define RALINK_INTCTL_ESW (1<<17)
1321 +#define RALINK_INTCTL_UHST (1<<18)
1322 +#define RALINK_INTCTL_UDEV (1<<19)
1323 +#define RALINK_INTCTL_GLOBAL (1<<31)
1325 +//Reset Control Register
1326 +#define RALINK_SYS_RST (1<<0)
1327 +#define RALINK_TIMER_RST (1<<8)
1328 +#define RALINK_INTC_RST (1<<9)
1329 +#define RALINK_MC_RST (1<<10)
1330 +#define RALINK_PCM_RST (1<<11)
1331 +#define RALINK_UART_RST (1<<12)
1332 +#define RALINK_PIO_RST (1<<13)
1333 +#define RALINK_DMA_RST (1<<14)
1334 +#define RALINK_I2C_RST (1<<16)
1335 +#define RALINK_I2S_RST (1<<17)
1336 +#define RALINK_SPI_RST (1<<18)
1337 +#define RALINK_UARTL_RST (1<<19)
1338 +#define RALINK_FE_RST (1<<21)
1339 +#define RALINK_UHST_RST (1<<22)
1340 +#define RALINK_ESW_RST (1<<23)
1341 +#define RALINK_EPHY_RST (1<<24)
1342 +#define RALINK_UDEV_RST (1<<25)
1343 +#define RALINK_PCIE0_RST (1<<26)
1344 +#define RALINK_PCIE1_RST (1<<27)
1345 +#define RALINK_MIPS_CNT_RST (1<<28)
1346 +#define RALINK_CRYPTO_RST (1<<29)
1348 +//Clock Conf Register
1349 +#define RALINK_UPHY0_CLK_EN (1<<25)
1350 +#define RALINK_UPHY1_CLK_EN (1<<22)
1351 +#define RALINK_PCIE0_CLK_EN (1<<26)
1352 +#define RALINK_PCIE1_CLK_EN (1<<27)
1354 +//CPU PLL CFG Register
1355 +#define CPLL_SW_CONFIG (0x1UL << 31)
1356 +#define CPLL_MULT_RATIO_SHIFT 16
1357 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1358 +#define CPLL_DIV_RATIO_SHIFT 10
1359 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1360 +#define BASE_CLOCK 40 /* Mhz */
1364 Index: linux-3.14.16/arch/mips/include/asm/rt2880/serial_rt2880.h
1365 ===================================================================
1366 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1367 +++ linux-3.14.16/arch/mips/include/asm/rt2880/serial_rt2880.h 2014-08-24 15:51:48.530654066 +0200
1369 +/**************************************************************************
1371 + * BRIEF MODULE DESCRIPTION
1372 + * serial port definition for Ralink RT2880 solution
1374 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
1376 + * This program is free software; you can redistribute it and/or modify it
1377 + * under the terms of the GNU General Public License as published by the
1378 + * Free Software Foundation; either version 2 of the License, or (at your
1379 + * option) any later version.
1381 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1382 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1383 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1384 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1385 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1386 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1387 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1388 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1389 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1390 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1392 + * You should have received a copy of the GNU General Public License along
1393 + * with this program; if not, write to the Free Software Foundation, Inc.,
1394 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1397 + **************************************************************************
1398 + * May 2007 Bruce Chang
1404 + **************************************************************************
1407 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1408 +#define RT2880_UART_RBR_OFFSET 0x00
1409 +#define RT2880_UART_TBR_OFFSET 0x00
1410 +#define RT2880_UART_IER_OFFSET 0x04
1411 +#define RT2880_UART_IIR_OFFSET 0x08
1412 +#define RT2880_UART_FCR_OFFSET 0x08
1413 +#define RT2880_UART_LCR_OFFSET 0x0C
1414 +#define RT2880_UART_MCR_OFFSET 0x10
1415 +#define RT2880_UART_LSR_OFFSET 0x14
1416 +#define RT2880_UART_DLL_OFFSET 0x00
1417 +#define RT2880_UART_DLM_OFFSET 0x04
1419 +#define RT2880_UART_RBR_OFFSET 0x00
1420 +#define RT2880_UART_TBR_OFFSET 0x04
1421 +#define RT2880_UART_IER_OFFSET 0x08
1422 +#define RT2880_UART_IIR_OFFSET 0x0C
1423 +#define RT2880_UART_FCR_OFFSET 0x10
1424 +#define RT2880_UART_LCR_OFFSET 0x14
1425 +#define RT2880_UART_MCR_OFFSET 0x18
1426 +#define RT2880_UART_LSR_OFFSET 0x1C
1427 +#define RT2880_UART_DLL_OFFSET 0x2C
1428 +#define RT2880_UART_DLM_OFFSET 0x30
1431 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
1432 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
1433 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
1434 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
1435 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
1436 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
1437 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
1438 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
1439 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
1440 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
1443 +#if defined (CONFIG_RALINK_RT2880) || \
1444 + defined (CONFIG_RALINK_RT2883) || \
1445 + defined (CONFIG_RALINK_RT3883) || \
1446 + defined (CONFIG_RALINK_RT3352) || \
1447 + defined (CONFIG_RALINK_RT5350) || \
1448 + defined (CONFIG_RALINK_RT6855) || \
1449 + defined (CONFIG_RALINK_MT7620) || \
1450 + defined (CONFIG_RALINK_RT3052)
1452 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1454 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
1455 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
1457 + * Out: Fifo custom trigger levels
1461 +#define UART_IER 8 /* Out: Interrupt Enable Register */
1462 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
1466 +#define UART_IIR 12 /* In: Interrupt ID Register */
1467 +#define UART_EFR 12 /* I/O: Extended Features Register */
1468 + /* (DLAB=1, 16C660 only) */
1470 +#define UART_FCR 16 /* Out: FIFO Control Register */
1471 +#define UART_LCR 20 /* Out: Line Control Register */
1472 +#define UART_MCR 24 /* Out: Modem Control Register */
1473 +#define UART_LSR 28 /* In: Line Status Register */
1474 +#define UART_MSR 32 /* In: Modem Status Register */
1475 +#define UART_SCR 36 /* I/O: Scratch Register */
1476 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
1477 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
1478 + * unpredictable values to be written to the Divisor Latch
1480 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
1484 +#define UART_RX 0 /* In: Receive buffer */
1485 +#define UART_TX 0 /* Out: Transmit buffer */
1486 +#define UART_DLL 0 /* Out: Divisor Latch Low */
1487 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1489 + * Out: Fifo custom trigger levels */
1491 +#define UART_DLM 4 /* Out: Divisor Latch High */
1492 +#define UART_IER 4 /* Out: Interrupt Enable Register */
1493 +#define UART_FCTR 4 /* Feature Control Register */
1495 +#define UART_IIR 8 /* In: Interrupt ID Register */
1496 +#define UART_FCR 8 /* Out: FIFO Control Register */
1497 +#define UART_EFR 8 /* I/O: Extended Features Register */
1499 +#define UART_LCR 12 /* Out: Line Control Register */
1500 +#define UART_MCR 16 /* Out: Modem Control Register */
1501 +#define UART_LSR 20 /* In: Line Status Register */
1502 +#define UART_MSR 24 /* In: Modem Status Register */
1503 +#define UART_SCR 28 /* I/O: Scratch Register */
1504 +#define UART_EMSR 28 /* Extended Mode Select Register */
1510 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
1511 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1512 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1513 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1514 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1516 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
1518 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
1520 +//#define UART_IIR 2 /* In: Interrupt ID Register */
1521 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1522 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1523 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1524 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1525 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1526 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1528 +//#define UART_FCR 2 /* Out: FIFO Control Register */
1529 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1530 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1531 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1532 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1534 + * Note: The FIFO trigger levels are chip specific:
1535 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
1536 + * PC16550D: 1 4 8 14 xx xx xx xx
1537 + * TI16C550A: 1 4 8 14 xx xx xx xx
1538 + * TI16C550C: 1 4 8 14 xx xx xx xx
1539 + * ST16C550: 1 4 8 14 xx xx xx xx
1540 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
1541 + * NS16C552: 1 4 8 14 xx xx xx xx
1542 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
1543 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
1544 + * TI16C752: 8 16 56 60 8 16 32 56
1546 +#define UART_FCR_R_TRIG_00 0x00
1547 +#define UART_FCR_R_TRIG_01 0x40
1548 +#define UART_FCR_R_TRIG_10 0x80
1549 +#define UART_FCR_R_TRIG_11 0xc0
1550 +#define UART_FCR_T_TRIG_00 0x00
1551 +#define UART_FCR_T_TRIG_01 0x10
1552 +#define UART_FCR_T_TRIG_10 0x20
1553 +#define UART_FCR_T_TRIG_11 0x30
1555 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
1556 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
1557 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
1558 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
1559 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
1560 +/* 16650 definitions */
1561 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
1562 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
1563 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
1564 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
1565 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
1566 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
1567 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
1568 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
1569 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
1571 +//#define UART_LCR 3 /* Out: Line Control Register */
1573 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
1574 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
1576 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1577 +#define UART_LCR_SBC 0x40 /* Set break control */
1578 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1579 +#define UART_LCR_EPAR 0x10 /* Even parity select */
1580 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
1581 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
1582 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1583 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1584 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1585 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1587 +//#define UART_MCR 4 /* Out: Modem Control Register */
1588 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
1589 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
1590 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
1591 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
1592 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1593 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
1594 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
1595 +#define UART_MCR_RTS 0x02 /* RTS complement */
1596 +#define UART_MCR_DTR 0x01 /* DTR complement */
1598 +//#define UART_LSR 5 /* In: Line Status Register */
1599 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1600 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1601 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1602 +#define UART_LSR_FE 0x08 /* Frame error indicator */
1603 +#define UART_LSR_PE 0x04 /* Parity error indicator */
1604 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
1605 +#define UART_LSR_DR 0x01 /* Receiver data ready */
1607 +//#define UART_MSR 6 /* In: Modem Status Register */
1608 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1609 +#define UART_MSR_RI 0x40 /* Ring Indicator */
1610 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
1611 +#define UART_MSR_CTS 0x10 /* Clear to Send */
1612 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
1613 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1614 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
1615 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
1616 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1618 +//#define UART_SCR 7 /* I/O: Scratch Register */
1623 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
1624 +//#define UART_DLM 1 /* Out: Divisor Latch High */
1627 + * LCR=0xBF (or DLAB=1 for 16C660)
1629 +//#define UART_EFR 2 /* I/O: Extended Features Register */
1630 +#define UART_EFR_CTS 0x80 /* CTS flow control */
1631 +#define UART_EFR_RTS 0x40 /* RTS flow control */
1632 +#define UART_EFR_SCD 0x20 /* Special character detect */
1633 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
1635 + * the low four bits control software flow control
1639 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
1641 +#define UART_XON1 4 /* I/O: Xon character 1 */
1642 +#define UART_XON2 5 /* I/O: Xon character 2 */
1643 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
1644 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
1647 + * EFR[4]=1 MCR[6]=1, TI16C752
1649 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
1650 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
1653 + * LCR=0xBF, XR16C85x
1655 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1656 +// * In: Fifo count
1657 +// * Out: Fifo custom trigger levels */
1659 + * These are the definitions for the Programmable Trigger Register
1661 +#define UART_TRG_1 0x01
1662 +#define UART_TRG_4 0x04
1663 +#define UART_TRG_8 0x08
1664 +#define UART_TRG_16 0x10
1665 +#define UART_TRG_32 0x20
1666 +#define UART_TRG_64 0x40
1667 +#define UART_TRG_96 0x60
1668 +#define UART_TRG_120 0x78
1669 +#define UART_TRG_128 0x80
1671 +//#define UART_FCTR 1 /* Feature Control Register */
1672 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
1673 +#define UART_FCTR_RTS_4DELAY 0x01
1674 +#define UART_FCTR_RTS_6DELAY 0x02
1675 +#define UART_FCTR_RTS_8DELAY 0x03
1676 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
1677 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
1678 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
1679 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
1680 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
1681 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
1682 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
1683 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
1684 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
1687 + * LCR=0xBF, FCTR[6]=1
1689 +//#define UART_EMSR 7 /* Extended Mode Select Register */
1690 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
1691 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
1694 + * The Intel XScale on-chip UARTs define these bits
1696 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
1697 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
1698 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
1699 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
1701 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
1703 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
1704 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
1705 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
1706 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
1712 + * These register definitions are for the 16C950
1714 +#define UART_ASR 0x01 /* Additional Status Register */
1715 +#define UART_RFL 0x03 /* Receiver FIFO level */
1716 +#define UART_TFL 0x04 /* Transmitter FIFO level */
1717 +#define UART_ICR 0x05 /* Index Control Register */
1719 +/* The 16950 ICR registers */
1720 +#define UART_ACR 0x00 /* Additional Control Register */
1721 +#define UART_CPR 0x01 /* Clock Prescalar Register */
1722 +#define UART_TCR 0x02 /* Times Clock Register */
1723 +#define UART_CKS 0x03 /* Clock Select Register */
1724 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
1725 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
1726 +#define UART_FCL 0x06 /* Flow Control Level Lower */
1727 +#define UART_FCH 0x07 /* Flow Control Level Higher */
1728 +#define UART_ID1 0x08 /* ID #1 */
1729 +#define UART_ID2 0x09 /* ID #2 */
1730 +#define UART_ID3 0x0A /* ID #3 */
1731 +#define UART_REV 0x0B /* Revision */
1732 +#define UART_CSR 0x0C /* Channel Software Reset */
1733 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
1734 +#define UART_CTR 0xFF
1737 + * The 16C950 Additional Control Reigster
1739 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
1740 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
1741 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
1742 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
1743 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
1744 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
1749 + * These definitions are for the RSA-DV II/S card, from
1751 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
1754 +#define UART_RSA_BASE (-8)
1756 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
1758 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
1759 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
1760 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
1761 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
1763 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
1765 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
1766 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
1767 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
1768 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
1769 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
1771 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
1773 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
1774 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
1775 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
1776 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
1777 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
1778 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
1779 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
1780 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
1782 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
1784 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
1786 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
1788 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
1791 + * The RSA DSV/II board has two fixed clock frequencies. One is the
1792 + * standard rate, and the other is 8 times faster.
1794 +#define SERIAL_RSA_BAUD_BASE (921600)
1795 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
1798 + * Extra serial register definitions for the internal UARTs
1799 + * in TI OMAP processors.
1801 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
1802 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
1803 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
1804 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
1805 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
1806 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
1807 +#define UART_OMAP_MVER 0x14 /* Module version register */
1808 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
1809 +#define UART_OMAP_SYSS 0x16 /* System status register */
1812 Index: linux-3.14.16/arch/mips/include/asm/rt2880/sizes.h
1813 ===================================================================
1814 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1815 +++ linux-3.14.16/arch/mips/include/asm/rt2880/sizes.h 2014-08-24 15:51:48.530654066 +0200
1818 + * This program is free software; you can redistribute it and/or modify
1819 + * it under the terms of the GNU General Public License as published by
1820 + * the Free Software Foundation; either version 2 of the License, or
1821 + * (at your option) any later version.
1823 + * This program is distributed in the hope that it will be useful,
1824 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1825 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1826 + * GNU General Public License for more details.
1828 + * You should have received a copy of the GNU General Public License
1829 + * along with this program; if not, write to the Free Software
1830 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1832 +/* DO NOT EDIT!! - this file automatically generated
1833 + * from .s file by awk -f s2h.awk
1835 +/* Size definitions
1836 + * Copyright (C) ARM Limited 1998. All rights reserved.
1840 +#define __sizes_h 1
1843 +#define SZ_1K 0x00000400
1844 +#define SZ_4K 0x00001000
1845 +#define SZ_8K 0x00002000
1846 +#define SZ_16K 0x00004000
1847 +#define SZ_64K 0x00010000
1848 +#define SZ_128K 0x00020000
1849 +#define SZ_256K 0x00040000
1850 +#define SZ_512K 0x00080000
1852 +#define SZ_1M 0x00100000
1853 +#define SZ_2M 0x00200000
1854 +#define SZ_4M 0x00400000
1855 +#define SZ_8M 0x00800000
1856 +#define SZ_16M 0x01000000
1857 +#define SZ_32M 0x02000000
1858 +#define SZ_64M 0x04000000
1859 +#define SZ_128M 0x08000000
1860 +#define SZ_256M 0x10000000
1861 +#define SZ_512M 0x20000000
1863 +#define SZ_1G 0x40000000
1864 +#define SZ_2G 0x80000000
1869 Index: linux-3.14.16/arch/mips/include/asm/rt2880/surfboard.h
1870 ===================================================================
1871 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1872 +++ linux-3.14.16/arch/mips/include/asm/rt2880/surfboard.h 2014-08-24 15:51:48.530654066 +0200
1875 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1877 + * ########################################################################
1879 + * This program is free software; you can distribute it and/or modify it
1880 + * under the terms of the GNU General Public License (Version 2) as
1881 + * published by the Free Software Foundation.
1883 + * This program is distributed in the hope it will be useful, but WITHOUT
1884 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1885 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1886 + * for more details.
1888 + * You should have received a copy of the GNU General Public License along
1889 + * with this program; if not, write to the Free Software Foundation, Inc.,
1890 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1892 + * ########################################################################
1895 +#ifndef _SURFBOARD_H
1896 +#define _SURFBOARD_H
1898 +#include <asm/addrspace.h>
1903 + * Surfboard system clock.
1904 + * This is the default value and maybe overidden by System Clock passed on the
1905 + * command line (sysclk=).
1907 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
1910 + * Surfboard UART base baud rate = System Clock / 16.
1911 + * Ex. (14.7456 MHZ / 16) = 921600
1912 + * (32.0000 MHZ / 16) = 2000000
1914 +#define SURFBOARD_BAUD_DIV (16)
1915 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
1918 + * Maximum number of IDE Controllers
1919 + * Surfboard only has one ide (ide0), so only 2 drives are
1920 + * possible. (no need to check for more hwifs.)
1922 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
1923 +#define MAX_IDE_HWIFS (2) /* Graphite board */
1925 +#define GCMP_BASE_ADDR 0x1fbf8000
1926 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
1929 + * * GIC Specific definitions
1931 +#define GIC_BASE_ADDR 0x1fbc0000
1932 +#define GIC_ADDRSPACE_SZ (128 * 1024)
1933 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
1935 +/* GIC's Nomenclature for Core Interrupt Pins */
1936 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
1937 +#define GIC_CPU_INT1 1 /* . */
1938 +#define GIC_CPU_INT2 2 /* . */
1939 +#define GIC_CPU_INT3 3 /* . */
1940 +#define GIC_CPU_INT4 4 /* . */
1941 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
1943 +#endif /* !(_SURFBOARD_H) */
1944 Index: linux-3.14.16/arch/mips/include/asm/rt2880/surfboardint.h
1945 ===================================================================
1946 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1947 +++ linux-3.14.16/arch/mips/include/asm/rt2880/surfboardint.h 2014-08-24 15:51:48.530654066 +0200
1950 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1952 + * ########################################################################
1954 + * This program is free software; you can distribute it and/or modify it
1955 + * under the terms of the GNU General Public License (Version 2) as
1956 + * published by the Free Software Foundation.
1958 + * This program is distributed in the hope it will be useful, but WITHOUT
1959 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1960 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1961 + * for more details.
1963 + * You should have received a copy of the GNU General Public License along
1964 + * with this program; if not, write to the Free Software Foundation, Inc.,
1965 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1967 + * ########################################################################
1969 + * Defines for the Surfboard interrupt controller.
1972 +#ifndef _SURFBOARDINT_H
1973 +#define _SURFBOARDINT_H
1975 +/* Number of IRQ supported on hw interrupt 0. */
1976 +#if defined (CONFIG_RALINK_RT2880)
1977 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
1978 +#define SURFBOARDINT_GPIO 7 /* GPIO */
1979 +#define SURFBOARDINT_UART1 8 /* UART Lite */
1980 +#define SURFBOARDINT_UART 9 /* UART */
1981 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
1982 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
1983 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
1984 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1985 +#define SURFBOARDINT_DMA 7 /* DMA */
1986 +#define SURFBOARDINT_NAND 8 /* NAND */
1987 +#define SURFBOARDINT_PC 9 /* Performance counter */
1988 +#define SURFBOARDINT_I2S 10 /* I2S */
1989 +#define SURFBOARDINT_SDXC 14 /* SDXC */
1990 +#define SURFBOARDINT_ESW 17 /* ESW */
1991 +#define SURFBOARDINT_UART1 12 /* UART Lite */
1992 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
1993 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
1994 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
1995 +#define SURFBOARDINT_WDG 34 /* watch dog */
1996 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
1997 +#define SURFBOARDINT_PCM 36 /* PCM */
1998 +#define SURFBOARDINT_UART 37 /* UART */
1999 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
2000 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
2003 +#elif defined (CONFIG_RALINK_MT7628)
2004 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
2005 +#define SURFBOARDINT_PCM 4 /* PCM */
2006 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2007 +#define SURFBOARDINT_DMA 7 /* DMA */
2008 +#define SURFBOARDINT_PC 9 /* Performance counter */
2009 +#define SURFBOARDINT_I2S 10 /* I2S */
2010 +#define SURFBOARDINT_SPI 11 /* SPI */
2011 +#define SURFBOARDINT_AES 13 /* AES */
2012 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2013 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2014 +#define SURFBOARDINT_ESW 17 /* ESW */
2015 +#define SURFBOARDINT_USB 18 /* USB */
2016 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
2017 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
2018 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
2019 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
2020 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
2021 +#define SURFBOARDINT_WDG 23 /* WDG timer */
2022 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
2023 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
2024 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2025 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
2028 +#elif defined (CONFIG_RALINK_MT7621)
2030 +#define SURFBOARDINT_FE 3 /* FE */
2031 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
2032 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
2033 +#define SURFBOARDINT_I2C 8 /* I2C */
2034 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
2035 +#define SURFBOARDINT_PCM 10 /* PCM */
2036 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
2037 +#define SURFBOARDINT_GPIO 12 /* GPIO */
2038 +#define SURFBOARDINT_DMA 13 /* GDMA */
2039 +#define SURFBOARDINT_NAND 14 /* NAND */
2040 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
2041 +#define SURFBOARDINT_I2S 16 /* I2S */
2042 +#define SURFBOARDINT_SPI 17 /* SPI */
2043 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
2044 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
2045 +#define SURFBOARDINT_SDXC 20 /* SDXC */
2046 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
2047 +#define SURFBOARDINT_USB 22 /* USB */
2048 +#define SURFBOARDINT_ESW 31 /* Switch */
2049 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
2050 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
2051 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
2052 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
2053 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
2054 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
2055 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
2057 +#define SURFBOARDINT_WDG 29 /* WDG timer */
2058 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
2059 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
2061 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
2062 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
2063 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
2065 +#elif defined (CONFIG_RALINK_RT3883)
2066 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
2067 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2068 +#define SURFBOARDINT_DMA 7 /* DMA */
2069 +#define SURFBOARDINT_NAND 8 /* NAND */
2070 +#define SURFBOARDINT_PC 9 /* Performance counter */
2071 +#define SURFBOARDINT_I2S 10 /* I2S */
2072 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2073 +#define SURFBOARDINT_PCI 18 /* PCI */
2074 +#define SURFBOARDINT_UDEV 19 /* USB Device */
2075 +#define SURFBOARDINT_UHST 20 /* USB Host */
2076 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2077 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2078 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2079 +#define SURFBOARDINT_PCM 36 /* PCM */
2080 +#define SURFBOARDINT_UART 37 /* UART */
2083 +#define SURFBOARDINT_END 64
2084 +#define RT2880_INTERINT_START 40
2086 +/* Global interrupt bit definitions */
2087 +#define C_SURFBOARD_GLOBAL_INT 31
2088 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
2091 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
2092 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
2093 +/* end of added, bobtseng */
2096 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
2097 + * only word access are allowed.
2099 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2100 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
2101 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
2102 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
2103 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
2104 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
2105 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
2107 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
2108 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
2109 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
2110 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
2111 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
2112 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
2115 +/* bobtseng added ++, 2006.3.6. */
2116 +#define read_32bit_cp0_register(source) \
2118 + __asm__ __volatile__( \
2119 + ".set\tpush\n\t" \
2120 + ".set\treorder\n\t" \
2121 + "mfc0\t%0,"STR(source)"\n\t" \
2123 + : "=r" (__res)); \
2126 +#define write_32bit_cp0_register(register,value) \
2127 + __asm__ __volatile__( \
2128 + "mtc0\t%0,"STR(register)"\n\t" \
2132 +/* bobtseng added --, 2006.3.6. */
2134 +void surfboardint_init(void);
2135 +u32 get_surfboard_sysclk(void);
2138 +#endif /* !(_SURFBOARDINT_H) */
2139 Index: linux-3.14.16/arch/mips/include/asm/rt2880/war.h
2140 ===================================================================
2141 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2142 +++ linux-3.14.16/arch/mips/include/asm/rt2880/war.h 2014-08-24 15:51:48.534654066 +0200
2145 + * This file is subject to the terms and conditions of the GNU General Public
2146 + * License. See the file "COPYING" in the main directory of this archive
2147 + * for more details.
2149 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2151 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
2152 +#define __ASM_MIPS_MACH_MIPS_WAR_H
2154 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2155 +#define R4600_V1_HIT_CACHEOP_WAR 0
2156 +#define R4600_V2_HIT_CACHEOP_WAR 0
2157 +#define R5432_CP0_INTERRUPT_WAR 0
2158 +#define BCM1250_M3_WAR 0
2159 +#define SIBYTE_1956_WAR 0
2160 +#define MIPS4K_ICACHE_REFILL_WAR 1
2161 +#define MIPS_CACHE_SYNC_WAR 1
2162 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2163 +#define RM9000_CDEX_SMP_WAR 0
2164 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
2165 +#define R10000_LLSC_WAR 0
2166 +#define MIPS34K_MISSED_ITLB_WAR 0
2168 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
2169 Index: linux-3.14.16/drivers/net/ethernet/Kconfig
2170 ===================================================================
2171 --- linux-3.14.16.orig/drivers/net/ethernet/Kconfig 2014-08-24 15:51:48.510654065 +0200
2172 +++ linux-3.14.16/drivers/net/ethernet/Kconfig 2014-08-24 15:51:48.534654066 +0200
2174 source "drivers/net/ethernet/pasemi/Kconfig"
2175 source "drivers/net/ethernet/qlogic/Kconfig"
2176 source "drivers/net/ethernet/ralink/Kconfig"
2177 +source "drivers/net/ethernet/raeth/Kconfig"
2178 source "drivers/net/ethernet/realtek/Kconfig"
2179 source "drivers/net/ethernet/renesas/Kconfig"
2180 source "drivers/net/ethernet/rdc/Kconfig"
2181 Index: linux-3.14.16/drivers/net/ethernet/Makefile
2182 ===================================================================
2183 --- linux-3.14.16.orig/drivers/net/ethernet/Makefile 2014-08-24 15:51:48.510654065 +0200
2184 +++ linux-3.14.16/drivers/net/ethernet/Makefile 2014-08-24 15:51:48.534654066 +0200
2186 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
2187 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
2188 obj-$(CONFIG_NET_RALINK) += ralink/
2189 +obj-$(CONFIG_RAETH) += raeth/
2190 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
2191 obj-$(CONFIG_SH_ETH) += renesas/
2192 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
2193 Index: linux-3.14.16/drivers/net/ethernet/raeth/Kconfig
2194 ===================================================================
2195 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2196 +++ linux-3.14.16/drivers/net/ethernet/raeth/Kconfig 2014-08-24 15:51:48.534654066 +0200
2207 + depends on SOC_MT7621
2209 +config RALINK_MT7621
2212 + depends on SOC_MT7621
2215 + tristate "Ralink GMAC"
2216 + depends on SOC_MT7621
2218 + This driver supports Ralink gigabit ethernet family of
2223 + default y if (RALINK_MT7620 || RALINK_MT7621)
2226 +config RAETH_SCATTER_GATHER_RX_DMA
2228 + default y if (RALINK_MT7620 || RALINK_MT7621)
2233 + prompt "Network BottomHalves"
2235 + default RA_NETWORK_WORKQUEUE_BH
2237 + config RA_NETWORK_TASKLET_BH
2240 + config RA_NETWORK_WORKQUEUE_BH
2248 +#config TASKLET_WORKQUEUE_SW
2249 +# bool "Tasklet and Workqueue switch"
2250 +# depends on RA_NETWORK_TASKLET_BH
2252 +config RAETH_SKB_RECYCLE_2K
2253 + bool "SKB Recycling"
2256 +config RAETH_SPECIAL_TAG
2257 + bool "Ralink Special Tag (0x810x)"
2258 + depends on RAETH && RT_3052_ESW
2260 +#config RAETH_JUMBOFRAME
2261 +# bool "Jumbo Frame up to 4K bytes"
2262 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
2264 +config RAETH_CHECKSUM_OFFLOAD
2265 + bool "TCP/UDP/IP checksum offload"
2267 + depends on RAETH && !RALINK_RT2880
2269 +#config RAETH_SW_FC
2270 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
2275 + bool "32bytes TX/RX description"
2277 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
2279 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
2282 + bool "LRO (Large Receive Offload )"
2284 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
2286 +config RAETH_HW_VLAN_TX
2287 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
2288 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
2290 + Please disable HW_VLAN_TX if you need double vlan
2292 +config RAETH_HW_VLAN_RX
2293 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
2294 + depends on RAETH && RALINK_MT7621
2296 + Please disable HW_VLAN_RX if you need double vlan
2299 + bool "TSOV4 (Tcp Segmentaton Offload)"
2300 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
2303 + bool "TSOV6 (Tcp Segmentaton Offload)"
2304 + depends on RAETH_TSO
2306 +config RAETH_RW_PDMAPTR_FROM_VAR
2308 + default y if RALINK_RT6855A || RALINK_MT7620
2312 +# bool "QoS Feature"
2313 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
2317 + depends on RAETH_QOS
2318 + default DSCP_QOS_DSCP
2320 +config RAETH_QOS_DSCP_BASED
2322 + depends on RAETH_QOS
2324 +config RAETH_QOS_VPRI_BASED
2326 + depends on RAETH_QOS
2331 + bool "Choose QDMA instead PDMA"
2333 + depends on RAETH && RALINK_MT7621
2336 + prompt "GMAC is connected to"
2338 + default GE1_RGMII_FORCE_1000
2340 +config GE1_MII_FORCE_100
2341 + bool "MII_FORCE_100 (10/100M Switch)"
2342 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2345 + bool "MII_AN (100Phy)"
2346 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2348 +config GE1_RVMII_FORCE_100
2349 + bool "RvMII_FORCE_100 (CPU)"
2350 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2352 +config GE1_RGMII_FORCE_1000
2353 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2354 + depends on (RALINK_RT2880 || RALINK_RT3883)
2357 +config GE1_RGMII_FORCE_1000
2358 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2359 + depends on (RALINK_MT7621)
2360 + select RT_3052_ESW
2362 +config GE1_TRGMII_FORCE_1200
2363 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
2364 + depends on (RALINK_MT7621)
2365 + select RT_3052_ESW
2367 +config GE1_RGMII_AN
2368 + bool "RGMII_AN (GigaPhy)"
2369 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2371 +config GE1_RGMII_NONE
2372 + bool "NONE (NO CONNECT)"
2373 + depends on (RALINK_MT7621)
2378 + bool "Ralink Embedded Switch"
2380 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
2382 +config LAN_WAN_SUPPORT
2383 + bool "LAN/WAN Partition"
2384 + depends on RAETH_ROUTER || RT_3052_ESW
2387 + prompt "Switch Board Layout Type"
2388 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
2398 +config RALINK_VISTA_BASIC
2399 + bool 'Vista Basic Logo for IC+ 175C'
2400 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
2402 +config ESW_DOUBLE_VLAN_TAG
2404 + default y if RT_3052_ESW
2406 +config RAETH_HAS_PORT4
2407 + bool "Port 4 Support"
2408 + depends on RAETH && RALINK_MT7620
2410 + prompt "Target Mode"
2411 + depends on RAETH_HAS_PORT4
2412 + default P4_RGMII_TO_MAC_MODE
2414 + config P4_MAC_TO_PHY_MODE
2415 + bool "Giga_Phy (RGMII)"
2416 + config GE_RGMII_MT7530_P0_AN
2417 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
2418 + config GE_RGMII_MT7530_P4_AN
2419 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
2420 + config P4_RGMII_TO_MAC_MODE
2421 + bool "Giga_SW/iNIC (RGMII)"
2422 + config P4_MII_TO_MAC_MODE
2423 + bool "External_CPU (MII_RvMII)"
2424 + config P4_RMII_TO_MAC_MODE
2425 + bool "External_CPU (RvMII_MII)"
2428 +config MAC_TO_GIGAPHY_MODE_ADDR2
2429 + hex "Port4 Phy Address"
2431 + depends on P4_MAC_TO_PHY_MODE
2433 +config RAETH_HAS_PORT5
2434 + bool "Port 5 Support"
2435 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
2437 + prompt "Target Mode"
2438 + depends on RAETH_HAS_PORT5
2439 + default P5_RGMII_TO_MAC_MODE
2441 + config P5_MAC_TO_PHY_MODE
2442 + bool "Giga_Phy (RGMII)"
2443 + config P5_RGMII_TO_MAC_MODE
2444 + bool "Giga_SW/iNIC (RGMII)"
2445 + config P5_RGMII_TO_MT7530_MODE
2446 + bool "MT7530 Giga_SW (RGMII)"
2447 + depends on RALINK_MT7620
2448 + config P5_MII_TO_MAC_MODE
2449 + bool "External_CPU (MII_RvMII)"
2450 + config P5_RMII_TO_MAC_MODE
2451 + bool "External_CPU (RvMII_MII)"
2454 +config MAC_TO_GIGAPHY_MODE_ADDR
2455 + hex "GE1 Phy Address"
2457 + depends on GE1_MII_AN || GE1_RGMII_AN
2459 +config MAC_TO_GIGAPHY_MODE_ADDR
2460 + hex "Port5 Phy Address"
2462 + depends on P5_MAC_TO_PHY_MODE
2465 + bool "GMAC2 Support"
2466 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
2469 + prompt "GMAC2 is connected to"
2470 + depends on RAETH_GMAC2
2471 + default GE2_RGMII_AN
2473 +config GE2_MII_FORCE_100
2474 + bool "MII_FORCE_100 (10/100M Switch)"
2475 + depends on RAETH_GMAC2
2478 + bool "MII_AN (100Phy)"
2479 + depends on RAETH_GMAC2
2481 +config GE2_RVMII_FORCE_100
2482 + bool "RvMII_FORCE_100 (CPU)"
2483 + depends on RAETH_GMAC2
2485 +config GE2_RGMII_FORCE_1000
2486 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2487 + depends on RAETH_GMAC2
2490 +config GE2_RGMII_AN
2491 + bool "RGMII_AN (GigaPhy)"
2492 + depends on RAETH_GMAC2
2494 +config GE2_INTERNAL_GPHY
2495 + bool "Internal GigaPHY"
2496 + depends on RAETH_GMAC2
2497 + select LAN_WAN_SUPPORT
2501 +config GE_RGMII_INTERNAL_P0_AN
2503 + depends on GE2_INTERNAL_GPHY
2504 + default y if WAN_AT_P0
2506 +config GE_RGMII_INTERNAL_P4_AN
2508 + depends on GE2_INTERNAL_GPHY
2509 + default y if WAN_AT_P4
2511 +config MAC_TO_GIGAPHY_MODE_ADDR2
2513 + default 0 if GE_RGMII_INTERNAL_P0_AN
2514 + default 4 if GE_RGMII_INTERNAL_P4_AN
2515 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
2517 +config MAC_TO_GIGAPHY_MODE_ADDR2
2518 + hex "GE2 Phy Address"
2520 + depends on GE2_MII_AN || GE2_RGMII_AN
2523 +config RAETH_ROUTER
2525 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
2528 +config MAC_TO_MAC_MODE
2530 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
2531 +depends on (RALINK_RT2880 || RALINK_RT3883)
2536 +default y if GE1_RGMII_AN || GE2_RGMII_AN
2541 +default y if GE1_MII_AN || GE2_MII_AN
2542 Index: linux-3.14.16/drivers/net/ethernet/raeth/Makefile
2543 ===================================================================
2544 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2545 +++ linux-3.14.16/drivers/net/ethernet/raeth/Makefile 2014-08-24 15:51:48.542654066 +0200
2547 +obj-$(CONFIG_RAETH) += raeth.o
2548 +raeth-objs := ra_mac.o mii_mgr.o
2549 +raeth-objs += raether_pdma.o
2550 +EXTRA_CFLAGS += -DWORKQUEUE_BH
2551 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
2553 +raeth-objs += raether.o
2554 Index: linux-3.14.16/drivers/net/ethernet/raeth/ethtool_readme.txt
2555 ===================================================================
2556 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2557 +++ linux-3.14.16/drivers/net/ethernet/raeth/ethtool_readme.txt 2014-08-24 15:51:48.542654066 +0200
2560 +Ethtool readme for selecting different PHY address.
2562 +Before doing any ethtool command you should make sure the current PHY
2563 +address is expected. The default PHY address is 1(port 1).
2565 +You can change current PHY address to X(0~4) by doing follow command:
2566 +# echo X > /proc/rt2880/gmac
2568 +Ethtool command also would show the current PHY address as following.
2572 + Supported ports: [ TP MII ]
2573 + Supported link modes: 10baseT/Half 10baseT/Full
2574 + 100baseT/Half 100baseT/Full
2575 + Supports auto-negotiation: Yes
2576 + Advertised link modes: 10baseT/Half 10baseT/Full
2577 + 100baseT/Half 100baseT/Full
2578 + Advertised auto-negotiation: No
2583 + Transceiver: internal
2584 + Auto-negotiation: off
2585 + Current message level: 0x00000000 (0)
2589 +The "PHYAD" field shows the current PHY address.
2595 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2599 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2603 Index: linux-3.14.16/drivers/net/ethernet/raeth/mii_mgr.c
2604 ===================================================================
2605 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2606 +++ linux-3.14.16/drivers/net/ethernet/raeth/mii_mgr.c 2014-08-24 15:51:48.542654066 +0200
2608 +#include <linux/module.h>
2609 +#include <linux/version.h>
2610 +#include <linux/netdevice.h>
2612 +#include <linux/kernel.h>
2613 +#include <linux/sched.h>
2614 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2615 +#include <asm/rt2880/rt_mmap.h>
2618 +#include "ra2882ethreg.h"
2619 +#include "raether.h"
2622 +#define PHY_CONTROL_0 0x0004
2623 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2624 +#define enable_mdio(x)
2627 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2629 + u32 volatile status = 0;
2631 + unsigned long volatile t_start = jiffies;
2632 + u32 volatile data = 0;
2634 + /* We enable mdio gpio purpose register, and disable it when exit. */
2637 + // make sure previous read operation is complete
2639 + // 0 : Read/write operation complete
2640 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2644 + else if (time_after(jiffies, t_start + 5*HZ)) {
2646 + printk("\n MDIO Read operation is ongoing !!\n");
2651 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
2652 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2654 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2655 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2658 + // make sure read operation is complete
2659 + t_start = jiffies;
2661 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
2662 + status = sysRegRead(MDIO_PHY_CONTROL_0);
2663 + *read_data = (u32)(status & 0x0000FFFF);
2668 + else if (time_after(jiffies, t_start+5*HZ)) {
2670 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
2676 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2678 + unsigned long volatile t_start=jiffies;
2679 + u32 volatile data;
2683 + // make sure previous write operation is complete
2685 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2689 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2691 + printk("\n MDIO Write operation ongoing\n");
2695 + /*add 1 us delay to make sequencial write more robus*/
2698 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
2699 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2701 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
2702 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2704 + t_start = jiffies;
2706 + // make sure write operation is complete
2708 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
2713 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2715 + printk("\n MDIO Write operation Time Out\n");
2721 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2727 + //phase1: write page address phase
2728 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
2729 + //phase2: write address & read low word phase
2730 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
2731 + //phase3: write address & read high word phase
2732 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
2733 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
2740 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
2748 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2750 + if(phy_addr == 31)
2752 + //phase1: write page address phase
2753 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
2754 + //phase2: write address & read low word phase
2755 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
2756 + //phase3: write address & read high word phase
2757 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
2764 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
2772 +EXPORT_SYMBOL(mii_mgr_write);
2773 +EXPORT_SYMBOL(mii_mgr_read);
2774 Index: linux-3.14.16/drivers/net/ethernet/raeth/ra2882ethreg.h
2775 ===================================================================
2776 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2777 +++ linux-3.14.16/drivers/net/ethernet/raeth/ra2882ethreg.h 2014-08-24 15:51:48.542654066 +0200
2779 +#ifndef RA2882ETHREG_H
2780 +#define RA2882ETHREG_H
2782 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
2783 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
2785 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2786 +#include <asm/rt2880/rt_mmap.h>
2788 +#include "raether.h"
2790 +#ifdef WORKQUEUE_BH
2791 +#include <linux/workqueue.h>
2792 +#endif // WORKQUEUE_BH //
2793 +#ifdef CONFIG_RAETH_LRO
2794 +#include <linux/inet_lro.h>
2797 +#define MAX_PACKET_SIZE 1514
2798 +#define MIN_PACKET_SIZE 60
2800 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
2802 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
2803 +#define BIT(x) ((1 << x))
2805 +#define ETHER_ADDR_LEN 6
2807 +/* Phy Vender ID list */
2809 +#define EV_ICPLUS_PHY_ID0 0x0243
2810 +#define EV_ICPLUS_PHY_ID1 0x0D90
2811 +#define EV_MARVELL_PHY_ID0 0x0141
2812 +#define EV_MARVELL_PHY_ID1 0x0CC2
2813 +#define EV_VTSS_PHY_ID0 0x0007
2814 +#define EV_VTSS_PHY_ID1 0x0421
2819 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2820 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2822 +#define RX_COHERENT BIT(31)
2823 +#define RX_DLY_INT BIT(30)
2824 +#define TX_COHERENT BIT(29)
2825 +#define TX_DLY_INT BIT(28)
2827 +#define RX_DONE_INT1 BIT(17)
2828 +#define RX_DONE_INT0 BIT(16)
2830 +#define TX_DONE_INT3 BIT(3)
2831 +#define TX_DONE_INT2 BIT(2)
2832 +#define TX_DONE_INT1 BIT(1)
2833 +#define TX_DONE_INT0 BIT(0)
2835 +#if defined (CONFIG_RALINK_MT7621)
2836 +#define RLS_COHERENT BIT(29)
2837 +#define RLS_DLY_INT BIT(28)
2838 +#define RLS_DONE_INT BIT(0)
2842 +//#define CNT_PPE_AF BIT(31)
2843 +//#define CNT_GDM_AF BIT(29)
2844 +#define PSE_P2_FC BIT(26)
2845 +#define GDM_CRC_DROP BIT(25)
2846 +#define PSE_BUF_DROP BIT(24)
2847 +#define GDM_OTHER_DROP BIT(23)
2848 +#define PSE_P1_FC BIT(22)
2849 +#define PSE_P0_FC BIT(21)
2850 +#define PSE_FQ_EMPTY BIT(20)
2851 +#define GE1_STA_CHG BIT(18)
2852 +#define TX_COHERENT BIT(17)
2853 +#define RX_COHERENT BIT(16)
2855 +#define TX_DONE_INT3 BIT(11)
2856 +#define TX_DONE_INT2 BIT(10)
2857 +#define TX_DONE_INT1 BIT(9)
2858 +#define TX_DONE_INT0 BIT(8)
2859 +#define RX_DONE_INT1 RX_DONE_INT0
2860 +#define RX_DONE_INT0 BIT(2)
2861 +#define TX_DLY_INT BIT(1)
2862 +#define RX_DLY_INT BIT(0)
2865 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
2866 + TX_DONE_INT1 | TX_DONE_INT0 | \
2869 +#if defined (CONFIG_RALINK_MT7621)
2870 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
2871 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
2873 +#define NUM_QDMA_PAGE 256
2874 +#define QDMA_PAGE_SIZE 2048
2879 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2880 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
2881 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
2882 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
2883 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
2884 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
2885 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
2886 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
2887 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
2888 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
2889 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
2890 +#define PORT_ST_CHG BIT(26) //Port status change
2891 +#define UNSECURED_ALERT BIT(27) //Intruder alert
2892 +#define ABNORMAL_ALERT BIT(28) //Abnormal
2894 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
2895 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
2896 +#define ESW_INT_ALL (PORT_ST_CHG)
2898 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2899 + defined (CONFIG_RALINK_MT7620)
2900 +#define MIB_INT BIT(25)
2901 +#define ACL_INT BIT(24)
2902 +#define P5_LINK_CH BIT(5)
2903 +#define P4_LINK_CH BIT(4)
2904 +#define P3_LINK_CH BIT(3)
2905 +#define P2_LINK_CH BIT(2)
2906 +#define P1_LINK_CH BIT(1)
2907 +#define P0_LINK_CH BIT(0)
2909 +#define RX_GOCT_CNT BIT(4)
2910 +#define RX_GOOD_CNT BIT(6)
2911 +#define TX_GOCT_CNT BIT(17)
2912 +#define TX_GOOD_CNT BIT(19)
2914 +#define MSK_RX_GOCT_CNT BIT(4)
2915 +#define MSK_RX_GOOD_CNT BIT(6)
2916 +#define MSK_TX_GOCT_CNT BIT(17)
2917 +#define MSK_TX_GOOD_CNT BIT(19)
2918 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
2919 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
2922 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
2923 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
2924 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
2925 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
2926 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
2927 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
2928 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
2929 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
2930 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
2931 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
2932 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
2933 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
2934 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
2935 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
2936 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
2937 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
2938 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
2939 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
2941 +#if defined (CONFIG_RALINK_MT7620)
2942 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
2943 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
2947 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
2949 +#elif defined (CONFIG_RALINK_MT7621)
2951 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
2953 +#define P5_LINK_CH BIT(5)
2954 +#define P4_LINK_CH BIT(4)
2955 +#define P3_LINK_CH BIT(3)
2956 +#define P2_LINK_CH BIT(2)
2957 +#define P1_LINK_CH BIT(1)
2958 +#define P0_LINK_CH BIT(0)
2961 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
2963 +#define RX_BUF_ALLOC_SIZE 2000
2964 +#define FASTPATH_HEADROOM 64
2966 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
2968 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
2969 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
2970 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
2972 +#ifdef CONFIG_PSEUDO_SUPPORT
2973 +typedef struct _PSEUDO_ADAPTER {
2974 + struct net_device *RaethDev;
2975 + struct net_device *PseudoDev;
2976 + struct net_device_stats stat;
2977 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
2978 + struct mii_if_info mii_info;
2981 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
2983 +#define MAX_PSEUDO_ENTRY 1
2988 +/* Register Categories Definition */
2989 +#define RAFRAMEENGINE_OFFSET 0x0000
2990 +#define RAGDMA_OFFSET 0x0020
2991 +#define RAPSE_OFFSET 0x0040
2992 +#define RAGDMA2_OFFSET 0x0060
2993 +#define RACDMA_OFFSET 0x0080
2994 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2995 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2997 +#define RAPDMA_OFFSET 0x0800
2998 +#define SDM_OFFSET 0x0C00
3000 +#define RAPDMA_OFFSET 0x0100
3002 +#define RAPPE_OFFSET 0x0200
3003 +#define RACMTABLE_OFFSET 0x0400
3004 +#define RAPOLICYTABLE_OFFSET 0x1000
3007 +/* Register Map Detail */
3009 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
3011 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3014 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3015 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3016 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3017 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3019 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3020 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3021 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3022 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3024 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3025 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3026 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3027 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3029 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3030 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3031 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3032 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3034 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3035 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3036 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3037 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3039 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3040 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3041 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3042 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3044 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3045 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3046 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3047 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3048 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3049 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3050 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3051 +#define FE_INT_STATUS (INT_STATUS)
3052 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3053 +#define FE_INT_ENABLE (INT_MASK)
3054 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3055 +#define PDMA_SCH_CFG (PDMA_WRR)
3057 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3058 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3059 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3060 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3061 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3062 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3063 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3064 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3065 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3066 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3068 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3069 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3071 +/* Old FE with New PDMA */
3072 +#define PDMA_RELATED 0x0800
3074 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3075 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3076 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3077 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3079 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3080 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3081 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3082 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3084 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3085 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3086 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3087 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3089 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3090 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3091 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3092 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3094 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3095 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3096 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3097 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3099 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3100 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3101 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3102 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3104 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3105 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3106 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3107 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3108 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3109 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3110 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3111 +#define FE_INT_STATUS (INT_STATUS)
3112 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3113 +#define FE_INT_ENABLE (INT_MASK)
3114 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3115 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3117 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3118 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3119 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3120 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3121 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3122 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3124 +#if defined (CONFIG_RALINK_MT7620)
3125 +#define GDMA1_RELATED 0x0600
3126 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3127 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3128 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3129 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3130 +#elif defined (CONFIG_RALINK_MT7621)
3131 +#define GDMA1_RELATED 0x0500
3132 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3133 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3134 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3135 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3137 +#define GDMA2_RELATED 0x1500
3138 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3139 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3140 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3141 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3143 +#define GDMA1_RELATED 0x0020
3144 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3145 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3146 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3147 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3148 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
3150 +#define GDMA2_RELATED 0x0060
3151 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3152 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3153 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3154 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3155 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
3158 +#if defined (CONFIG_RALINK_MT7620)
3159 +#define PSE_RELATED 0x0500
3160 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3161 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3162 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3164 +#define PSE_RELATED 0x0040
3165 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3166 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3167 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3168 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
3169 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
3170 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
3171 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
3172 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
3176 +#if defined (CONFIG_RALINK_MT7620)
3177 +#define CDMA_RELATED 0x0400
3178 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3179 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
3180 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
3181 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
3182 +#elif defined (CONFIG_RALINK_MT7621)
3183 +#define CDMA_RELATED 0x0400
3184 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
3185 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3186 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3188 +#define CDMA_RELATED 0x0080
3189 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3190 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3191 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
3192 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
3193 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
3196 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
3199 +#if defined (CONFIG_RALINK_MT7621)
3200 +/*kurtis: add QDMA define*/
3202 +#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
3203 +#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
3205 +#define QDMA_RELATED 0x1800
3206 +#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
3207 +#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
3208 +#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
3209 +#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
3210 +#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
3211 +#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
3212 +#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
3213 +#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
3214 +#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
3215 +#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
3216 +#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
3217 +#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
3218 +#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
3219 +#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
3220 +#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
3221 +#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
3222 +#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
3223 +#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
3224 +#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
3225 +#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
3226 +#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
3227 +#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
3228 +#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
3229 +#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
3230 +#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
3231 +#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
3232 +#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
3233 +#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
3234 +#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
3235 +#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
3236 +#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
3237 +#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
3238 +#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
3239 +#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
3240 +#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
3241 +#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
3242 +#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
3243 +#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
3244 +#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
3245 +#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
3246 +#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
3247 +#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
3248 +#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
3249 +#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
3250 +#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
3251 +#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
3252 +#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
3253 +#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
3254 +#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
3255 +#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
3256 +#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
3257 +#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
3258 +#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
3259 +#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
3260 +#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
3261 +#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
3262 +#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
3263 +#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
3264 +#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
3265 +#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
3266 +#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
3267 +#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
3268 +#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
3269 +#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
3270 +#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
3271 +#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
3272 +#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
3273 +#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
3274 +#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
3275 +#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
3276 +#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
3277 +#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
3278 +#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
3279 +#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
3280 +#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
3281 +#define QDMA_RST_CFG (QDMA_RST_IDX)
3282 +#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
3283 +#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
3284 +#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
3285 +#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
3286 +#define QFE_INT_STATUS (QDMA_INT_STS)
3287 +#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
3288 +#define QFE_INT_ENABLE (QDMA_INT_MASK)
3289 +#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
3290 +#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
3291 +#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
3292 +#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
3293 +#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
3294 +#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
3295 +#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
3296 +#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
3297 +#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
3298 +#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
3299 +#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
3300 +#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
3301 +#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
3302 +#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
3303 +#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
3304 +#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
3305 +#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
3306 +#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
3307 +#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
3308 +#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
3309 +#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
3310 +#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
3311 +#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
3312 +#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
3313 +#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
3314 +#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
3315 +#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
3316 +#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
3317 +#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
3320 +#endif/*MT7621 QDMA*/
3324 +/* 1. Frame Engine Global Registers */
3325 +#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
3326 +#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
3327 +#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
3328 +#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
3329 +#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
3330 +#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
3331 +#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
3332 +#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
3335 +/* 2. GDMA Registers */
3336 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
3337 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
3338 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
3339 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
3340 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
3342 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
3343 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
3344 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
3345 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
3346 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
3349 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
3350 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
3351 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
3352 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
3353 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0)
3356 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
3357 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
3358 +/* skip ppoe sid and vlan id definition */
3362 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
3363 +#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
3364 +#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
3366 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
3368 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
3369 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
3370 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
3371 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
3373 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
3374 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
3375 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
3376 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
3378 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3379 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3380 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3381 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3383 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
3384 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
3385 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
3386 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
3388 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
3389 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
3390 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
3391 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
3393 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3394 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3395 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3396 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3400 +#define DELAY_INT_INIT 0x84048404
3401 +#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
3404 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3406 +/* 6. Counter and Meter Table */
3407 +#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
3408 +#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
3411 +#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
3413 +#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
3415 +#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
3416 +#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
3417 +#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
3418 +#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
3420 +/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
3421 +#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
3422 +#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
3423 +#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
3424 +#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
3425 +#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
3426 +#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
3427 +#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
3428 +#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
3433 +/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
3434 +#define PORT0_PKCOUNT (0xb01100e8)
3435 +#define PORT1_PKCOUNT (0xb01100ec)
3436 +#define PORT2_PKCOUNT (0xb01100f0)
3437 +#define PORT3_PKCOUNT (0xb01100f4)
3438 +#define PORT4_PKCOUNT (0xb01100f8)
3439 +#define PORT5_PKCOUNT (0xb01100fc)
3443 +#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
3446 +#define sysRegRead(phys) \
3447 + (*(volatile unsigned int *)PHYS_TO_K1(phys))
3449 +#define sysRegWrite(phys, val) \
3450 + ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
3452 +#define u_long unsigned long
3453 +#define u32 unsigned int
3454 +#define u16 unsigned short
3457 +/* ====================================== */
3458 +#define GDM1_DISPAD BIT(18)
3459 +#define GDM1_DISCRC BIT(17)
3461 +//GDMA1 uni-cast frames destination port
3462 +#define GDM1_ICS_EN (0x1 << 22)
3463 +#define GDM1_TCS_EN (0x1 << 21)
3464 +#define GDM1_UCS_EN (0x1 << 20)
3465 +#define GDM1_JMB_EN (0x1 << 19)
3466 +#define GDM1_STRPCRC (0x1 << 16)
3467 +#define GDM1_UFRC_P_CPU (0 << 12)
3468 +#if defined (CONFIG_RALINK_MT7621)
3469 +#define GDM1_UFRC_P_PPE (4 << 12)
3471 +#define GDM1_UFRC_P_PPE (6 << 12)
3474 +//GDMA1 broad-cast MAC address frames
3475 +#define GDM1_BFRC_P_CPU (0 << 8)
3476 +#if defined (CONFIG_RALINK_MT7621)
3477 +#define GDM1_BFRC_P_PPE (4 << 8)
3479 +#define GDM1_BFRC_P_PPE (6 << 8)
3482 +//GDMA1 multi-cast MAC address frames
3483 +#define GDM1_MFRC_P_CPU (0 << 4)
3484 +#if defined (CONFIG_RALINK_MT7621)
3485 +#define GDM1_MFRC_P_PPE (4 << 4)
3487 +#define GDM1_MFRC_P_PPE (6 << 4)
3490 +//GDMA1 other MAC address frames destination port
3491 +#define GDM1_OFRC_P_CPU (0 << 0)
3492 +#if defined (CONFIG_RALINK_MT7621)
3493 +#define GDM1_OFRC_P_PPE (4 << 0)
3495 +#define GDM1_OFRC_P_PPE (6 << 0)
3498 +#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3499 +/* checksum generator registers are removed */
3500 +#define ICS_GEN_EN (0 << 2)
3501 +#define UCS_GEN_EN (0 << 1)
3502 +#define TCS_GEN_EN (0 << 0)
3504 +#define ICS_GEN_EN (1 << 2)
3505 +#define UCS_GEN_EN (1 << 1)
3506 +#define TCS_GEN_EN (1 << 0)
3510 +#define MDIO_CFG_GP1_FC_TX (1 << 11)
3511 +#define MDIO_CFG_GP1_FC_RX (1 << 10)
3513 +/* ====================================== */
3514 +/* ====================================== */
3515 +#define GP1_LNK_DWN BIT(9)
3516 +#define GP1_AN_FAIL BIT(8)
3517 +/* ====================================== */
3518 +/* ====================================== */
3519 +#define PSE_RESET BIT(0)
3520 +/* ====================================== */
3521 +#define PST_DRX_IDX1 BIT(17)
3522 +#define PST_DRX_IDX0 BIT(16)
3523 +#define PST_DTX_IDX3 BIT(3)
3524 +#define PST_DTX_IDX2 BIT(2)
3525 +#define PST_DTX_IDX1 BIT(1)
3526 +#define PST_DTX_IDX0 BIT(0)
3528 +#define RX_2B_OFFSET BIT(31)
3529 +#define DESC_32B_EN BIT(8)
3530 +#define TX_WB_DDONE BIT(6)
3531 +#define RX_DMA_BUSY BIT(3)
3532 +#define TX_DMA_BUSY BIT(1)
3533 +#define RX_DMA_EN BIT(2)
3534 +#define TX_DMA_EN BIT(0)
3536 +#define PDMA_BT_SIZE_4DWORDS (0<<4)
3537 +#define PDMA_BT_SIZE_8DWORDS (1<<4)
3538 +#define PDMA_BT_SIZE_16DWORDS (2<<4)
3539 +#define PDMA_BT_SIZE_32DWORDS (3<<4)
3544 +#define MACCFG_RXEN (1<<2)
3545 +#define MACCFG_TXEN (1<<3)
3546 +#define MACCFG_PROMISC (1<<18)
3547 +#define MACCFG_RXMCAST (1<<19)
3548 +#define MACCFG_FDUPLEX (1<<20)
3549 +#define MACCFG_PORTSEL (1<<27)
3550 +#define MACCFG_HBEATDIS (1<<28)
3553 +#define DMACTL_SR (1<<1) /* Start/Stop Receive */
3554 +#define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */
3556 +#define DMACFG_SWR (1<<0) /* Software Reset */
3557 +#define DMACFG_BURST32 (32<<8)
3559 +#define DMASTAT_TS 0x00700000 /* Transmit Process State */
3560 +#define DMASTAT_RS 0x000e0000 /* Receive Process State */
3562 +#define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
3566 +/* Descriptor bits.
3568 +#define R_OWN 0x80000000 /* Own Bit */
3569 +#define RD_RER 0x02000000 /* Receive End Of Ring */
3570 +#define RD_LS 0x00000100 /* Last Descriptor */
3571 +#define RD_ES 0x00008000 /* Error Summary */
3572 +#define RD_CHAIN 0x01000000 /* Chained */
3575 +#define T_OWN 0x80000000 /* Own Bit */
3576 +#define TD_ES 0x00008000 /* Error Summary */
3579 +#define TD_LS 0x40000000 /* Last Segment */
3580 +#define TD_FS 0x20000000 /* First Segment */
3581 +#define TD_TER 0x08000000 /* Transmit End Of Ring */
3582 +#define TD_CHAIN 0x01000000 /* Chained */
3585 +#define TD_SET 0x08000000 /* Setup Packet */
3588 +#define POLL_DEMAND 1
3590 +#define RSTCTL (0x34)
3591 +#define RSTCTL_RSTENET1 (1<<19)
3592 +#define RSTCTL_RSTENET2 (1<<20)
3594 +#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
3595 +#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
3596 +#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
3597 +#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
3599 +// Define Whole FE Reset Register
3600 +#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
3602 +/*=========================================
3603 + PDMA RX Descriptor Format define
3604 +=========================================*/
3606 +//-------------------------------------------------
3607 +typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
3609 +struct _PDMA_RXD_INFO1_
3611 + unsigned int PDP0;
3613 +//-------------------------------------------------
3614 +typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
3616 +struct _PDMA_RXD_INFO2_
3618 + unsigned int PLEN1 : 14;
3619 + unsigned int LS1 : 1;
3620 + unsigned int TAG : 1;
3621 + unsigned int PLEN0 : 14;
3622 + unsigned int LS0 : 1;
3623 + unsigned int DDONE_bit : 1;
3625 +//-------------------------------------------------
3626 +typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
3628 +struct _PDMA_RXD_INFO3_
3630 + unsigned int VID:16;
3631 + unsigned int TPID:16;
3633 +//-------------------------------------------------
3634 +typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
3636 +struct _PDMA_RXD_INFO4_
3638 +#if defined (CONFIG_RALINK_MT7620)
3639 + unsigned int FOE_Entry : 14;
3640 + unsigned int CRSN : 5;
3641 + unsigned int SPORT : 3;
3642 + unsigned int L4F : 1;
3643 + unsigned int L4VLD : 1;
3644 + unsigned int TACK : 1;
3645 + unsigned int IP4F : 1;
3646 + unsigned int IP4 : 1;
3647 + unsigned int IP6 : 1;
3648 + unsigned int UN_USE1 : 4;
3649 +#elif defined (CONFIG_RALINK_MT7621)
3650 + unsigned int FOE_Entry : 14;
3651 + unsigned int CRSN : 5;
3652 + unsigned int SP : 4;
3653 + unsigned int L4F : 1;
3654 + unsigned int L4VLD : 1;
3655 + unsigned int TACK : 1;
3656 + unsigned int IP4F : 1;
3657 + unsigned int IP4 : 1;
3658 + unsigned int IP6 : 1;
3659 + unsigned int UN_USE1 : 3;
3661 + unsigned int FOE_Entry : 14;
3662 + unsigned int FVLD : 1;
3663 + unsigned int UN_USE1 : 1;
3664 + unsigned int AI : 8;
3665 + unsigned int SP : 3;
3666 + unsigned int AIS : 1;
3667 + unsigned int L4F : 1;
3668 + unsigned int IPF : 1;
3669 + unsigned int L4FVLD_bit : 1;
3670 + unsigned int IPFVLD_bit : 1;
3675 +struct PDMA_rxdesc {
3676 + PDMA_RXD_INFO1_T rxd_info1;
3677 + PDMA_RXD_INFO2_T rxd_info2;
3678 + PDMA_RXD_INFO3_T rxd_info3;
3679 + PDMA_RXD_INFO4_T rxd_info4;
3680 +#ifdef CONFIG_32B_DESC
3681 + unsigned int rxd_info5;
3682 + unsigned int rxd_info6;
3683 + unsigned int rxd_info7;
3684 + unsigned int rxd_info8;
3688 +/*=========================================
3689 + PDMA TX Descriptor Format define
3690 +=========================================*/
3691 +//-------------------------------------------------
3692 +typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
3694 +struct _PDMA_TXD_INFO1_
3696 + unsigned int SDP0;
3698 +//-------------------------------------------------
3699 +typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
3701 +struct _PDMA_TXD_INFO2_
3703 + unsigned int SDL1 : 14;
3704 + unsigned int LS1_bit : 1;
3705 + unsigned int BURST_bit : 1;
3706 + unsigned int SDL0 : 14;
3707 + unsigned int LS0_bit : 1;
3708 + unsigned int DDONE_bit : 1;
3710 +//-------------------------------------------------
3711 +typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
3713 +struct _PDMA_TXD_INFO3_
3715 + unsigned int SDP1;
3717 +//-------------------------------------------------
3718 +typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
3720 +struct _PDMA_TXD_INFO4_
3722 +#if defined (CONFIG_RALINK_MT7620)
3723 + unsigned int VPRI_VIDX : 8;
3724 + unsigned int SIDX : 4;
3725 + unsigned int INSP : 1;
3726 + unsigned int RESV : 2;
3727 + unsigned int UDF : 5;
3728 + unsigned int FP_BMAP : 8;
3729 + unsigned int TSO : 1;
3730 + unsigned int TUI_CO : 3;
3731 +#elif defined (CONFIG_RALINK_MT7621)
3732 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3733 + unsigned int RESV : 2;
3734 + unsigned int UDF : 6;
3735 + unsigned int FPORT : 3;
3736 + unsigned int TSO : 1;
3737 + unsigned int TUI_CO : 3;
3739 + unsigned int VPRI_VIDX : 8;
3740 + unsigned int SIDX : 4;
3741 + unsigned int INSP : 1;
3742 + unsigned int RESV : 1;
3743 + unsigned int UN_USE3 : 2;
3744 + unsigned int QN : 3;
3745 + unsigned int UN_USE2 : 1;
3746 + unsigned int UDF : 4;
3747 + unsigned int PN : 3;
3748 + unsigned int UN_USE1 : 1;
3749 + unsigned int TSO : 1;
3750 + unsigned int TUI_CO : 3;
3755 +struct PDMA_txdesc {
3756 + PDMA_TXD_INFO1_T txd_info1;
3757 + PDMA_TXD_INFO2_T txd_info2;
3758 + PDMA_TXD_INFO3_T txd_info3;
3759 + PDMA_TXD_INFO4_T txd_info4;
3760 +#ifdef CONFIG_32B_DESC
3761 + unsigned int txd_info5;
3762 + unsigned int txd_info6;
3763 + unsigned int txd_info7;
3764 + unsigned int txd_info8;
3769 +#if defined (CONFIG_RALINK_MT7621)
3770 +/*=========================================
3771 + QDMA TX Descriptor Format define
3772 +=========================================*/
3773 +//-------------------------------------------------
3774 +typedef struct _QDMA_TXD_INFO1_ QDMA_TXD_INFO1_T;
3776 +struct _QDMA_TXD_INFO1_
3780 +//-------------------------------------------------
3781 +typedef struct _QDMA_TXD_INFO2_ QDMA_TXD_INFO2_T;
3783 +struct _QDMA_TXD_INFO2_
3787 +//-------------------------------------------------
3788 +typedef struct _QDMA_TXD_INFO3_ QDMA_TXD_INFO3_T;
3790 +struct _QDMA_TXD_INFO3_
3792 + unsigned int QID : 4;
3793 + unsigned int RESV : 10;
3794 + unsigned int SWC_bit : 1;
3795 + unsigned int BURST_bit : 1;
3796 + unsigned int SDL : 14;
3797 + unsigned int LS_bit : 1;
3798 + unsigned int OWN_bit : 1;
3800 +//-------------------------------------------------
3801 +typedef struct _QDMA_TXD_INFO4_ QDMA_TXD_INFO4_T;
3803 +struct _QDMA_TXD_INFO4_
3805 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3806 + unsigned int RESV : 2;
3807 + unsigned int UDF : 6;
3808 + unsigned int FPORT : 3;
3809 + unsigned int TSO : 1;
3810 + unsigned int TUI_CO : 3;
3814 +struct QDMA_txdesc {
3815 + QDMA_TXD_INFO1_T txd_info1;
3816 + QDMA_TXD_INFO2_T txd_info2;
3817 + QDMA_TXD_INFO3_T txd_info3;
3818 + QDMA_TXD_INFO4_T txd_info4;
3819 +#ifdef CONFIG_32B_DESC
3820 + unsigned int txd_info5;
3821 + unsigned int txd_info6;
3822 + unsigned int txd_info7;
3823 + unsigned int txd_info8;
3828 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
3830 +#define PHY_Enable_Auto_Nego 0x1000
3831 +#define PHY_Restart_Auto_Nego 0x0200
3833 +/* PHY_STAT_REG = 1; */
3834 +#define PHY_Auto_Neco_Comp 0x0020
3835 +#define PHY_Link_Status 0x0004
3837 +/* PHY_AUTO_NEGO_REG = 4; */
3838 +#define PHY_Cap_10_Half 0x0020
3839 +#define PHY_Cap_10_Full 0x0040
3840 +#define PHY_Cap_100_Half 0x0080
3841 +#define PHY_Cap_100_Full 0x0100
3843 +/* proc definition */
3845 +#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
3846 + !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621)
3847 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
3848 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
3849 +#define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
3850 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
3853 +#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
3854 +#if defined (CONFIG_RALINK_RT2880)
3855 +#define PROCREG_DIR "rt2880"
3856 +#elif defined (CONFIG_RALINK_RT3052)
3857 +#define PROCREG_DIR "rt3052"
3858 +#elif defined (CONFIG_RALINK_RT3352)
3859 +#define PROCREG_DIR "rt3352"
3860 +#elif defined (CONFIG_RALINK_RT5350)
3861 +#define PROCREG_DIR "rt5350"
3862 +#elif defined (CONFIG_RALINK_RT2883)
3863 +#define PROCREG_DIR "rt2883"
3864 +#elif defined (CONFIG_RALINK_RT3883)
3865 +#define PROCREG_DIR "rt3883"
3866 +#elif defined (CONFIG_RALINK_RT6855)
3867 +#define PROCREG_DIR "rt6855"
3868 +#elif defined (CONFIG_RALINK_MT7620)
3869 +#define PROCREG_DIR "mt7620"
3870 +#elif defined (CONFIG_RALINK_MT7621)
3871 +#define PROCREG_DIR "mt7621"
3872 +#elif defined (CONFIG_RALINK_MT7628)
3873 +#define PROCREG_DIR "mt7628"
3874 +#elif defined (CONFIG_RALINK_RT6855A)
3875 +#define PROCREG_DIR "rt6855a"
3877 +#define PROCREG_DIR "rt2880"
3879 +#define PROCREG_SKBFREE "skb_free"
3880 +#define PROCREG_TXRING "tx_ring"
3881 +#define PROCREG_RXRING "rx_ring"
3882 +#define PROCREG_NUM_OF_TXD "num_of_txd"
3883 +#define PROCREG_TSO_LEN "tso_len"
3884 +#define PROCREG_LRO_STATS "lro_stats"
3885 +#define PROCREG_GMAC "gmac"
3886 +#define PROCREG_GMAC2 "gmac2"
3887 +#define PROCREG_CP0 "cp0"
3888 +#define PROCREG_RAQOS "qos"
3889 +#define PROCREG_READ_VAL "regread_value"
3890 +#define PROCREG_WRITE_VAL "regwrite_value"
3891 +#define PROCREG_ADDR "reg_addr"
3892 +#define PROCREG_CTL "procreg_control"
3893 +#define PROCREG_RXDONE_INTR "rxdone_intr_count"
3894 +#define PROCREG_ESW_INTR "esw_intr_count"
3895 +#define PROCREG_ESW_CNT "esw_cnt"
3896 +#define PROCREG_SNMP "snmp"
3897 +#if defined (TASKLET_WORKQUEUE_SW)
3898 +#define PROCREG_SCHE "schedule"
3900 +#define PROCREG_QDMA "qdma"
3902 +struct rt2880_reg_op_data {
3904 + unsigned int reg_addr;
3906 + unsigned int reg_value;
3909 +#ifdef CONFIG_RAETH_LRO
3910 +struct lro_counters {
3911 + u32 lro_aggregated;
3916 +struct lro_para_struct {
3917 + unsigned int lan_ip1;
3920 +#endif // CONFIG_RAETH_LRO //
3925 +typedef struct end_device
3928 + unsigned int tx_cpu_owner_idx0;
3929 + unsigned int rx_cpu_owner_idx0;
3930 + unsigned int fe_int_status;
3931 + unsigned int tx_full;
3933 +#if !defined (CONFIG_RAETH_QDMA)
3934 + unsigned int phy_tx_ring0;
3937 + struct sk_buff *free_skb[NUM_TX_DESC];
3938 + unsigned int tx_dma_ptr;
3939 + unsigned int tx_cpu_ptr;
3940 + unsigned int free_txd_num;
3941 + unsigned int free_txd_head;
3942 + unsigned int free_txd_tail;
3943 + struct QDMA_txdesc *txd_pool;
3944 + dma_addr_t phy_txd_pool;
3945 +// unsigned int phy_txd_pool;
3946 + unsigned int txd_pool_info[NUM_TX_DESC];
3949 + unsigned int phy_rx_ring0, phy_rx_ring1;
3951 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
3952 + defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
3953 + defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
3954 + defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3955 + //send signal to user application to notify link status changed
3956 + struct work_struct kill_sig_wq;
3959 + struct work_struct reset_task;
3960 +#ifdef WORKQUEUE_BH
3961 + struct work_struct rx_wq;
3963 +#if defined (TASKLET_WORKQUEUE_SW)
3964 + struct work_struct rx_wq;
3966 +#endif // WORKQUEUE_BH //
3968 +#if defined(CONFIG_RAETH_QOS)
3969 + struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC];
3970 + unsigned int free_idx[NUM_TX_RINGS];
3972 + struct sk_buff* skb_free[NUM_TX_DESC];
3973 + unsigned int free_idx;
3976 + struct net_device_stats stat; /* The new statistics table. */
3977 + spinlock_t page_lock; /* Page register locks */
3978 + struct PDMA_txdesc *tx_ring0;
3979 +#if defined(CONFIG_RAETH_QOS)
3980 + struct PDMA_txdesc *tx_ring1;
3981 + struct PDMA_txdesc *tx_ring2;
3982 + struct PDMA_txdesc *tx_ring3;
3984 + struct PDMA_rxdesc *rx_ring0;
3985 + struct sk_buff *netrx0_skbuf[NUM_RX_DESC];
3986 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
3987 + struct PDMA_rxdesc *rx_ring1;
3988 + struct sk_buff *netrx1_skbuf[NUM_RX_DESC];
3990 +#ifdef CONFIG_RAETH_NAPI
3992 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
3993 + struct napi_struct napi;
3996 +#ifdef CONFIG_PSEUDO_SUPPORT
3997 + struct net_device *PseudoDev;
3998 + unsigned int isPseudo;
4000 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
4001 + struct mii_if_info mii_info;
4003 +#ifdef CONFIG_RAETH_LRO
4004 + struct lro_counters lro_counters;
4005 + struct net_lro_mgr lro_mgr;
4006 + struct net_lro_desc lro_arr[8];
4008 +#ifdef CONFIG_RAETH_HW_VLAN_RX
4009 + struct vlan_group *vlgrp;
4011 +} END_DEVICE, *pEND_DEVICE;
4014 +#define RAETH_VERSION "v3.0"
4018 +#ifdef CONFIG_RAETH_QDMA
4019 +#define DMA_GLO_CFG QDMA_GLO_CFG
4020 +#define GDMA1_FWD_PORT 0x5555
4021 +#define GDMA2_FWD_PORT 0x5555
4022 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
4023 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
4024 +#define RAETH_FE_INT_STATUS QFE_INT_STATUS
4025 +#define RAETH_FE_INT_ALL QFE_INT_ALL
4026 +#define RAETH_FE_INT_ENABLE QFE_INT_ENABLE
4027 +#define RAETH_FE_INT_DLY_INIT QFE_INT_DLY_INIT
4028 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT
4029 +#define RAETH_TX_DLY_INT RLS_DLY_INT
4030 +#define RAETH_TX_DONE_INT0 RLS_DONE_INT
4031 +#define RAETH_DLY_INT_CFG QDMA_DELAY_INT
4033 +#define DMA_GLO_CFG PDMA_GLO_CFG
4034 +#define GDMA1_FWD_PORT 0x0000
4035 +#define GDMA2_FWD_PORT 0x0000
4036 +#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
4037 +#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
4038 +#define RAETH_FE_INT_STATUS FE_INT_STATUS
4039 +#define RAETH_FE_INT_ALL FE_INT_ALL
4040 +#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
4041 +#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
4042 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
4043 +#define RAETH_TX_DLY_INT TX_DLY_INT
4044 +#define RAETH_TX_DONE_INT0 TX_DONE_INT0
4045 +#define RAETH_DLY_INT_CFG DLY_INT_CFG
4047 Index: linux-3.14.16/drivers/net/ethernet/raeth/ra_ioctl.h
4048 ===================================================================
4049 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4050 +++ linux-3.14.16/drivers/net/ethernet/raeth/ra_ioctl.h 2014-08-24 15:51:48.542654066 +0200
4052 +#ifndef _RAETH_IOCTL_H
4053 +#define _RAETH_IOCTL_H
4055 +/* ioctl commands */
4056 +#define RAETH_ESW_REG_READ 0x89F1
4057 +#define RAETH_ESW_REG_WRITE 0x89F2
4058 +#define RAETH_MII_READ 0x89F3
4059 +#define RAETH_MII_WRITE 0x89F4
4060 +#define RAETH_ESW_INGRESS_RATE 0x89F5
4061 +#define RAETH_ESW_EGRESS_RATE 0x89F6
4062 +#define RAETH_ESW_PHY_DUMP 0x89F7
4063 +#define RAETH_QDMA_REG_READ 0x89F8
4064 +#define RAETH_QDMA_REG_WRITE 0x89F9
4065 +#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
4066 +#define RAETH_QDMA_READ_CPU_CLK 0x89FB
4068 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4069 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4071 +#define REG_ESW_WT_MAC_MFC 0x10
4072 +#define REG_ESW_WT_MAC_ATA1 0x74
4073 +#define REG_ESW_WT_MAC_ATA2 0x78
4074 +#define REG_ESW_WT_MAC_ATWD 0x7C
4075 +#define REG_ESW_WT_MAC_ATC 0x80
4077 +#define REG_ESW_TABLE_TSRA1 0x84
4078 +#define REG_ESW_TABLE_TSRA2 0x88
4079 +#define REG_ESW_TABLE_ATRD 0x8C
4082 +#define REG_ESW_VLAN_VTCR 0x90
4083 +#define REG_ESW_VLAN_VAWD1 0x94
4084 +#define REG_ESW_VLAN_VAWD2 0x98
4087 +#define REG_ESW_VLAN_ID_BASE 0x100
4089 +//#define REG_ESW_VLAN_ID_BASE 0x50
4090 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4091 +#define REG_ESW_TABLE_SEARCH 0x24
4092 +#define REG_ESW_TABLE_STATUS0 0x28
4093 +#define REG_ESW_TABLE_STATUS1 0x2C
4094 +#define REG_ESW_TABLE_STATUS2 0x30
4095 +#define REG_ESW_WT_MAC_AD0 0x34
4096 +#define REG_ESW_WT_MAC_AD1 0x38
4097 +#define REG_ESW_WT_MAC_AD2 0x3C
4100 +/* rt3052 embedded ethernet switch registers */
4101 +#define REG_ESW_VLAN_ID_BASE 0x50
4102 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4103 +#define REG_ESW_TABLE_SEARCH 0x24
4104 +#define REG_ESW_TABLE_STATUS0 0x28
4105 +#define REG_ESW_TABLE_STATUS1 0x2C
4106 +#define REG_ESW_TABLE_STATUS2 0x30
4107 +#define REG_ESW_WT_MAC_AD0 0x34
4108 +#define REG_ESW_WT_MAC_AD1 0x38
4109 +#define REG_ESW_WT_MAC_AD2 0x3C
4113 +#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
4114 +#define REG_ESW_MAX 0x16C
4115 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4116 + defined (CONFIG_RALINK_MT7620)
4117 +#define REG_ESW_MAX 0x7FFFF
4118 +#else //RT305x, RT3350
4119 +#define REG_ESW_MAX 0xFC
4121 +#define REG_HQOS_MAX 0x3FFF
4124 +typedef struct rt3052_esw_reg {
4129 +typedef struct ralink_mii_ioctl_data {
4134 +} ra_mii_ioctl_data;
4136 +typedef struct rt335x_esw_reg {
4137 + unsigned int on_off;
4138 + unsigned int port;
4139 + unsigned int bw;/*Mbps*/
4144 Index: linux-3.14.16/drivers/net/ethernet/raeth/ra_mac.c
4145 ===================================================================
4146 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4147 +++ linux-3.14.16/drivers/net/ethernet/raeth/ra_mac.c 2014-08-24 15:51:48.542654066 +0200
4149 +#include <linux/module.h>
4150 +#include <linux/version.h>
4151 +#include <linux/kernel.h>
4152 +#include <linux/sched.h>
4153 +#include <linux/types.h>
4154 +#include <linux/fcntl.h>
4155 +#include <linux/interrupt.h>
4156 +#include <linux/ptrace.h>
4157 +#include <linux/ioport.h>
4158 +#include <linux/in.h>
4159 +#include <linux/slab.h>
4160 +#include <linux/string.h>
4161 +#include <linux/signal.h>
4162 +#include <linux/irq.h>
4163 +#include <linux/ctype.h>
4165 +#include <asm/io.h>
4166 +#include <asm/bitops.h>
4167 +#include <asm/io.h>
4168 +#include <asm/dma.h>
4170 +#include <asm/rt2880/surfboardint.h> /* for cp0 reg access, added by bobtseng */
4172 +#include <linux/errno.h>
4173 +#include <linux/init.h>
4174 +//#include <linux/mca.h>
4176 +#include <linux/netdevice.h>
4177 +#include <linux/etherdevice.h>
4178 +#include <linux/skbuff.h>
4180 +#include <linux/init.h>
4181 +#include <linux/module.h>
4182 +#include <linux/proc_fs.h>
4183 +#include <asm/uaccess.h>
4185 +#if defined(CONFIG_USER_SNMPD)
4186 +#include <linux/seq_file.h>
4191 +#include "ra2882ethreg.h"
4192 +#include "raether.h"
4193 +#include "ra_mac.h"
4195 +extern struct net_device *dev_raether;
4198 +void ra2880stop(END_DEVICE *ei_local)
4200 + unsigned int regValue;
4201 + printk("ra2880stop()...");
4203 + regValue = sysRegRead(PDMA_GLO_CFG);
4204 + regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
4205 + sysRegWrite(PDMA_GLO_CFG, regValue);
4206 + printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regValue);
4210 +void ei_irq_clear(void)
4212 + sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
4213 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_STATUS", FE_INT_STATUS, 0xFFFFFFFF);
4216 +void rt2880_gmac_hard_reset(void)
4218 + sysRegWrite(RSTCTRL, RALINK_FE_RST);
4219 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, RALINK_FE_RST);
4220 + sysRegWrite(RSTCTRL, 0);
4221 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, 0);
4224 +void ra2880EnableInterrupt()
4226 + unsigned int regValue = sysRegRead(FE_INT_ENABLE);
4227 + sysRegWrite(FE_INT_ENABLE, regValue);
4228 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_ENABLE", FE_INT_ENABLE, regValue);
4231 +void ra2880MacAddressSet(unsigned char p[6])
4233 + unsigned long regValue;
4235 + regValue = (p[0] << 8) | (p[1]);
4236 + sysRegWrite(GDMA1_MAC_ADRH, regValue);
4237 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRH", GDMA1_MAC_ADRH, regValue);
4239 + regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
4240 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRL", GDMA1_MAC_ADRL, regValue);
4241 + sysRegWrite(GDMA1_MAC_ADRL, regValue);
4247 Index: linux-3.14.16/drivers/net/ethernet/raeth/ra_mac.h
4248 ===================================================================
4249 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4250 +++ linux-3.14.16/drivers/net/ethernet/raeth/ra_mac.h 2014-08-24 15:51:48.542654066 +0200
4255 +void ra2880stop(END_DEVICE *ei_local);
4256 +void ra2880MacAddressSet(unsigned char p[6]);
4257 +void ra2880Mac2AddressSet(unsigned char p[6]);
4258 +void ethtool_init(struct net_device *dev);
4260 +void ra2880EnableInterrupt(void);
4262 +void dump_qos(void);
4263 +void dump_reg(void);
4264 +void dump_cp0(void);
4266 +int debug_proc_init(void);
4267 +void debug_proc_exit(void);
4269 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4270 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4271 +void enable_auto_negotiate(int unused);
4273 +void enable_auto_negotiate(int ge);
4276 +void rt2880_gmac_hard_reset(void);
4278 +int TsoLenUpdate(int tso_len);
4279 +int NumOfTxdUpdate(int num_of_txd);
4281 +#ifdef CONFIG_RAETH_LRO
4282 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
4284 +int getnext(const char *src, int separator, char *dest);
4285 +int str_to_ip(unsigned int *ip, const char *str);
4287 Index: linux-3.14.16/drivers/net/ethernet/raeth/raether.c
4288 ===================================================================
4289 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4290 +++ linux-3.14.16/drivers/net/ethernet/raeth/raether.c 2014-08-24 16:00:48.998667292 +0200
4292 +#include <linux/module.h>
4293 +#include <linux/version.h>
4294 +#include <linux/kernel.h>
4295 +#include <linux/types.h>
4296 +#include <linux/pci.h>
4297 +#include <linux/interrupt.h>
4298 +#include <linux/init.h>
4299 +#include <linux/skbuff.h>
4300 +#include <linux/if_vlan.h>
4301 +#include <linux/if_ether.h>
4302 +#include <linux/fs.h>
4303 +#include <asm/uaccess.h>
4304 +#include <linux/delay.h>
4305 +#include <linux/sched.h>
4307 +#include <asm/rt2880/rt_mmap.h>
4308 +#include "ra2882ethreg.h"
4309 +#include "raether.h"
4310 +#include "ra_mac.h"
4311 +#include "ra_ioctl.h"
4313 +static int rt2880_eth_recv(struct net_device* dev);
4316 +void setup_internal_gsw(void);
4318 +#define MAX_RX_LENGTH 1536
4320 +struct net_device *dev_raether;
4322 +static int rx_dma_owner_idx;
4323 +static int rx_dma_owner_idx0;
4324 +static int pending_recv;
4325 +static struct PDMA_rxdesc *rx_ring;
4326 +static unsigned long tx_ring_full=0;
4328 +#define KSEG1 0xa0000000
4329 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
4330 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
4332 +extern int fe_dma_init(struct net_device *dev);
4333 +extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
4334 +extern void ei_xmit_housekeeping(unsigned long unused);
4335 +extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
4337 +static int ei_set_mac_addr(struct net_device *dev, void *p)
4339 + struct sockaddr *addr = p;
4341 + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4343 + if(netif_running(dev))
4346 + ra2880MacAddressSet(addr->sa_data);
4351 +void set_fe_dma_glo_cfg(void)
4353 + int dma_glo_cfg=0;
4355 + dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
4357 + dma_glo_cfg |= (RX_2B_OFFSET);
4359 + sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
4360 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "DMA_GLO_CFG", DMA_GLO_CFG, dma_glo_cfg);
4363 +int forward_config(struct net_device *dev)
4365 + unsigned int regVal, regCsg;
4367 + regVal = sysRegRead(GDMA1_FWD_CFG);
4368 + regCsg = sysRegRead(CDMA_CSG_CFG);
4370 + //set unicast/multicast/broadcast frame to cpu
4371 + regVal &= ~0xFFFF;
4372 + regVal |= GDMA1_FWD_PORT;
4375 + //disable ipv4 header checksum check
4376 + regVal &= ~GDM1_ICS_EN;
4377 + regCsg &= ~ICS_GEN_EN;
4379 + //disable tcp checksum check
4380 + regVal &= ~GDM1_TCS_EN;
4381 + regCsg &= ~TCS_GEN_EN;
4383 + //disable udp checksum check
4384 + regVal &= ~GDM1_UCS_EN;
4385 + regCsg &= ~UCS_GEN_EN;
4388 + dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
4391 + sysRegWrite(GDMA1_FWD_CFG, regVal);
4392 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "GDMA1_FWD_CFG", GDMA1_FWD_CFG, regVal);
4393 + sysRegWrite(CDMA_CSG_CFG, regCsg);
4394 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "CDMA_CSG_CFG", CDMA_CSG_CFG, regCsg);
4397 + sysRegWrite(FE_RST_GL, regVal);
4398 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, regVal);
4399 + sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
4400 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, 1);
4402 + regCsg = sysRegRead(CDMA_CSG_CFG);
4403 + printk("CDMA_CSG_CFG = %0X\n",regCsg);
4404 + regVal = sysRegRead(GDMA1_FWD_CFG);
4405 + printk("GDMA1_FWD_CFG = %0X\n",regVal);
4411 +static int rt2880_eth_recv(struct net_device* dev)
4413 + struct sk_buff *skb, *rx_skb;
4414 + unsigned int length = 0;
4415 + unsigned long RxProcessed;
4418 + int bReschedule = 0;
4419 + END_DEVICE* ei_local = netdev_priv(dev);
4425 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4429 + if (RxProcessed++ > NUM_RX_MAX_PROCESS)
4431 + // need to reschedule rx handle
4438 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
4439 + rx_ring = ei_local->rx_ring0;
4440 + rx_dma_owner_idx = rx_dma_owner_idx0;
4445 + /* skb processing */
4446 + length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
4447 + rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
4448 + rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
4449 + rx_skb->len = length;
4451 + rx_skb->data += NET_IP_ALIGN;
4453 + rx_skb->tail = rx_skb->data + length;
4455 + rx_skb->dev = dev;
4456 + rx_skb->protocol = eth_type_trans(rx_skb,dev);
4458 + rx_skb->ip_summed = CHECKSUM_NONE;
4461 + /* We have to check the free memory size is big enough
4462 + * before pass the packet to cpu*/
4463 + skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
4465 + if (unlikely(skb == NULL))
4467 + printk(KERN_ERR "skb not available...\n");
4468 + ei_local->stat.rx_dropped++;
4478 + ei_local->stat.rx_packets++;
4479 + ei_local->stat.rx_bytes += length;
4483 + rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
4484 + rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
4485 + rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
4486 + rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
4488 + /* Move point to next RXD which wants to alloc*/
4489 + sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4490 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_RX_CALC_IDX0", RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4491 + ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
4493 + /* Update to Next packet point that was received.
4495 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4498 + return bReschedule;
4501 +void ei_receive_workq(struct work_struct *work)
4503 + struct net_device *dev = dev_raether;
4504 + END_DEVICE *ei_local = netdev_priv(dev);
4505 + unsigned long reg_int_mask=0;
4506 + int bReschedule=0;
4509 + if(tx_ring_full==0){
4510 + bReschedule = rt2880_eth_recv(dev);
4513 + schedule_work(&ei_local->rx_wq);
4515 + reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
4516 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4517 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4520 + schedule_work(&ei_local->rx_wq);
4525 +static irqreturn_t ei_interrupt(int irq, void *dev_id)
4527 + unsigned long reg_int_val;
4528 + unsigned long reg_int_mask=0;
4529 + unsigned int recv = 0;
4530 + unsigned int transmit __maybe_unused = 0;
4531 + unsigned long flags;
4533 + struct net_device *dev = (struct net_device *) dev_id;
4534 + END_DEVICE *ei_local = netdev_priv(dev);
4538 + printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
4543 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4544 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
4546 + if((reg_int_val & RX_DLY_INT))
4549 + if (reg_int_val & RAETH_TX_DLY_INT)
4552 + sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4553 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_STATUS", RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4555 + ei_xmit_housekeeping(0);
4557 + if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
4559 + reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
4560 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4561 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4563 + schedule_work(&ei_local->rx_wq);
4565 + else if (recv == 1 && tx_ring_full==1)
4569 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4571 + return IRQ_HANDLED;
4574 +static void esw_link_status_changed(int port_no, void *dev_id)
4576 + unsigned int reg_val;
4577 + mii_mgr_read(31, (0x3008 + (port_no*0x100)), ®_val);
4578 + if(reg_val & 0x1) {
4579 + printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
4581 + printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
4586 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
4588 + unsigned long flags;
4589 + unsigned int reg_int_val;
4590 + struct net_device *dev = (struct net_device *) dev_id;
4591 + END_DEVICE *ei_local = netdev_priv(dev);
4593 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4594 + mii_mgr_read(31, 0x700c, ®_int_val);
4596 + if (reg_int_val & P4_LINK_CH) {
4597 + esw_link_status_changed(4, dev_id);
4600 + if (reg_int_val & P3_LINK_CH) {
4601 + esw_link_status_changed(3, dev_id);
4603 + if (reg_int_val & P2_LINK_CH) {
4604 + esw_link_status_changed(2, dev_id);
4606 + if (reg_int_val & P1_LINK_CH) {
4607 + esw_link_status_changed(1, dev_id);
4609 + if (reg_int_val & P0_LINK_CH) {
4610 + esw_link_status_changed(0, dev_id);
4613 + mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
4614 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4615 + return IRQ_HANDLED;
4620 +static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
4622 + return ei_start_xmit(skb, dev, 1);
4625 +static int ei_change_mtu(struct net_device *dev, int new_mtu)
4627 + unsigned long flags;
4628 + END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
4630 + if ( ei_local == NULL ) {
4631 + printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
4635 + spin_lock_irqsave(&ei_local->page_lock, flags);
4637 + if ( (new_mtu > 4096) || (new_mtu < 64)) {
4638 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4642 + if ( new_mtu > 1500 ) {
4643 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4647 + dev->mtu = new_mtu;
4649 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4654 +static const struct net_device_ops ei_netdev_ops = {
4655 + .ndo_init = rather_probe,
4656 + .ndo_open = ei_open,
4657 + .ndo_stop = ei_close,
4658 + .ndo_start_xmit = ei_start_xmit_fake,
4659 + .ndo_set_mac_address = eth_mac_addr,
4660 + .ndo_change_mtu = ei_change_mtu,
4661 + .ndo_validate_addr = eth_validate_addr,
4664 +void ra2880_setup_dev_fptable(struct net_device *dev)
4666 + RAETH_PRINT(__FUNCTION__ "is called!\n");
4668 + dev->netdev_ops = &ei_netdev_ops;
4669 +#define TX_TIMEOUT (5*HZ)
4670 + dev->watchdog_timeo = TX_TIMEOUT;
4674 +void fe_reset(void)
4677 + val = sysRegRead(RSTCTRL);
4679 + val = val | RALINK_FE_RST;
4680 + sysRegWrite(RSTCTRL, val);
4681 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4682 + val = val & ~(RALINK_FE_RST);
4683 + sysRegWrite(RSTCTRL, val);
4684 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4687 +void ei_reset_task(struct work_struct *work)
4689 + struct net_device *dev = dev_raether;
4697 +void ei_tx_timeout(struct net_device *dev)
4699 + END_DEVICE *ei_local = netdev_priv(dev);
4701 + schedule_work(&ei_local->reset_task);
4704 +int __init rather_probe(struct net_device *dev)
4706 + END_DEVICE *ei_local = netdev_priv(dev);
4707 + struct sockaddr addr;
4708 + unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
4711 + memcpy(addr.sa_data, mac_addr01234, 5);
4712 + addr.sa_data[5] = prandom_u32()&0xFF;
4713 + ei_set_mac_addr(dev, &addr);
4714 + spin_lock_init(&ei_local->page_lock);
4721 +int ei_open(struct net_device *dev)
4724 + unsigned long flags;
4725 + END_DEVICE *ei_local;
4728 + if (!try_module_get(THIS_MODULE))
4730 + printk("%s: Cannot reserve module\n", __FUNCTION__);
4733 + printk("Raeth %s (",RAETH_VERSION);
4734 + printk("Workqueue");
4737 + ei_local = netdev_priv(dev); // get device pointer from System
4738 + // unsigned int flags;
4740 + if (ei_local == NULL)
4742 + printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
4746 + /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
4747 + for ( i = 0; i < NUM_RX_DESC; i++)
4749 + ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
4750 + if (ei_local->netrx0_skbuf[i] == NULL ) {
4751 + printk("rx skbuff buffer allocation failed!");
4756 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4758 + fe_sw_init(); //initialize fe and switch register
4759 + err = request_irq( dev->irq, ei_interrupt, 0, dev->name, dev); // try to fix irq in open
4763 + if ( dev->dev_addr != NULL) {
4764 + ra2880MacAddressSet((void *)(dev->dev_addr));
4766 + printk("dev->dev_addr is empty !\n");
4768 + mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
4769 + err = request_irq(31, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
4773 + sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4774 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_DLY_INT_CFG", RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4775 + sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4776 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4778 + INIT_WORK(&ei_local->reset_task, ei_reset_task);
4780 + INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
4782 + netif_start_queue(dev);
4785 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4788 + forward_config(dev);
4792 +int ei_close(struct net_device *dev)
4795 + END_DEVICE *ei_local = netdev_priv(dev); // device pointer
4796 + unsigned long flags;
4797 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4799 + cancel_work_sync(&ei_local->reset_task);
4800 + netif_stop_queue(dev);
4801 + ra2880stop(ei_local);
4804 + cancel_work_sync(&ei_local->rx_wq);
4805 + free_irq(dev->irq, dev);
4806 + free_irq(31, dev);
4807 + for ( i = 0; i < NUM_RX_DESC; i++)
4809 + if (ei_local->netrx0_skbuf[i] != NULL) {
4810 + dev_kfree_skb(ei_local->netrx0_skbuf[i]);
4811 + ei_local->netrx0_skbuf[i] = NULL;
4814 + if (ei_local->tx_ring0 != NULL) {
4815 + pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
4817 + pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
4819 + printk("Free TX/RX Ring Memory!\n");
4822 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4824 + module_put(THIS_MODULE);
4829 +void setup_internal_gsw(void)
4834 + /* reduce RGMII2 PAD driving strength */
4835 + *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
4837 + //RGMII1=Normal mode
4838 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
4840 + //GMAC1= RGMII mode
4841 + *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
4843 + //enable MDIO to control MT7530
4844 + regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
4845 + regValue &= ~(0x3 << 12);
4846 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
4851 + mii_mgr_read(i, 0x0 ,®Value);
4852 + regValue |= (0x1<<11);
4853 + mii_mgr_write(i, 0x0, regValue);
4855 + mii_mgr_write(31, 0x7000, 0x3); //reset switch
4858 + if(sysRegRead(0xbe00000c)==0x00030101) {
4859 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e30b);//(GE1, Force 1000M/FD, FC ON)
4860 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e30b);
4861 + mii_mgr_write(31, 0x3600, 0x5e30b);
4863 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e33b);//(GE1, Force 1000M/FD, FC ON)
4864 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e33b);
4865 + mii_mgr_write(31, 0x3600, 0x5e33b);
4868 + sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
4869 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x200", RALINK_ETH_SW_BASE+0x200, 0x00008000);
4871 + //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
4872 + mii_mgr_read(31, 0x7804 ,®Value);
4873 + regValue &= ~(1<<8); //Enable Port 6
4874 + regValue |= (1<<6); //Disable Port 5
4875 + regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
4877 + regValue |= (1<<16);//change HW-TRAP
4878 + printk("change HW-TRAP to 0x%x!!!!!!!!!!!!",regValue);
4879 + mii_mgr_write(31, 0x7804 ,regValue);
4880 + regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
4881 + regValue = (regValue >> 6) & 0x7;
4882 + if(regValue >= 6) { //25Mhz Xtal
4884 + } else if(regValue >=3) { //40Mhz
4886 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock
4887 + mii_mgr_write(0, 14, 0x410);
4888 + mii_mgr_write(0, 13, 0x401f);
4889 + mii_mgr_write(0, 14, 0x0);
4891 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL
4892 + mii_mgr_write(0, 14, 0x40d);
4893 + mii_mgr_write(0, 13, 0x401f);
4894 + mii_mgr_write(0, 14, 0x2020);
4896 + mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz
4897 + mii_mgr_write(0, 14, 0x40e);
4898 + mii_mgr_write(0, 13, 0x401f);
4899 + mii_mgr_write(0, 14, 0x119);
4901 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL
4902 + mii_mgr_write(0, 14, 0x40d);
4903 + mii_mgr_write(0, 13, 0x401f);
4904 + mii_mgr_write(0, 14, 0x2820);
4906 + udelay(20); //suggest by CD
4908 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock
4909 + mii_mgr_write(0, 14, 0x410);
4910 + mii_mgr_write(0, 13, 0x401f);
4911 + }else { //20Mhz Xtal
4916 + mii_mgr_write(0, 14, 0x1); /*RGMII*/
4919 + mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M
4920 + mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M
4922 + mii_mgr_write(31, 0x7b00, 8); // delay setting for 100M
4923 + mii_mgr_write(31, 0x7b04, 0x14); // for 100M
4926 + mii_mgr_write(31, 0x7a54, 0x44); //lower driving
4927 + mii_mgr_write(31, 0x7a5c, 0x44); //lower driving
4928 + mii_mgr_write(31, 0x7a64, 0x44); //lower driving
4929 + mii_mgr_write(31, 0x7a6c, 0x44); //lower driving
4930 + mii_mgr_write(31, 0x7a74, 0x44); //lower driving
4931 + mii_mgr_write(31, 0x7a7c, 0x44); //lower driving
4936 + mii_mgr_read(i, 0x0 ,®Value);
4937 + regValue &= ~(0x1<<11);
4938 + mii_mgr_write(i, 0x0, regValue);
4941 + mii_mgr_read(31, 0x7808 ,®Value);
4942 + regValue |= (3<<16); //Enable INTR
4943 + mii_mgr_write(31, 0x7808 ,regValue);
4946 +int __init ra2882eth_init(void)
4949 + struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
4953 + strcpy(dev->name, DEV_NAME);
4954 + dev->irq = IRQ_ENET0;
4955 + dev->addr_len = 6;
4956 + dev->base_addr = RALINK_FRAME_ENGINE_BASE;
4958 + rather_probe(dev);
4959 + ra2880_setup_dev_fptable(dev);
4961 + if ( register_netdev(dev) != 0) {
4962 + printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
4967 + dev_raether = dev;
4971 +void fe_sw_init(void)
4973 + setup_internal_gsw();
4977 +void ra2882eth_cleanup_module(void)
4980 +EXPORT_SYMBOL(set_fe_dma_glo_cfg);
4981 +module_init(ra2882eth_init);
4982 +module_exit(ra2882eth_cleanup_module);
4983 +MODULE_LICENSE("GPL");
4984 Index: linux-3.14.16/drivers/net/ethernet/raeth/raether.h
4985 ===================================================================
4986 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4987 +++ linux-3.14.16/drivers/net/ethernet/raeth/raether.h 2014-08-24 15:51:48.542654066 +0200
4989 +#ifndef RA2882ETHEND_H
4990 +#define RA2882ETHEND_H
4992 +#ifdef DSP_VIA_NONCACHEABLE
4993 +#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */
4995 +#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */
4998 +#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000))
4999 +#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800))
5001 +#if defined(CONFIG_RALINK_RT2880)
5002 +#define NUM_TX_RINGS 1
5004 +#define NUM_TX_RINGS 4
5006 +#ifdef MEMORY_OPTIMIZATION
5007 +#ifdef CONFIG_RAETH_ROUTER
5008 +#define NUM_RX_DESC 128
5009 +#define NUM_TX_DESC 128
5010 +#elif CONFIG_RT_3052_ESW
5011 +#define NUM_RX_DESC 64
5012 +#define NUM_TX_DESC 64
5014 +#define NUM_RX_DESC 128
5015 +#define NUM_TX_DESC 128
5017 +//#define NUM_RX_MAX_PROCESS 32
5018 +#define NUM_RX_MAX_PROCESS 64
5020 +#if defined (CONFIG_RAETH_ROUTER)
5021 +#define NUM_RX_DESC 256
5022 +#define NUM_TX_DESC 256
5023 +#elif defined (CONFIG_RT_3052_ESW)
5024 +#define NUM_RX_DESC 256
5025 +#define NUM_TX_DESC 256
5027 +#define NUM_RX_DESC 256
5028 +#define NUM_TX_DESC 256
5030 +#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
5031 +#define NUM_RX_MAX_PROCESS 2
5033 +#define NUM_RX_MAX_PROCESS 16
5037 +#define DEV_NAME "eth0"
5038 +#define DEV2_NAME "eth3"
5040 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
5041 +#define GMAC0_OFFSET 0xE000
5042 +#define GMAC2_OFFSET 0xE006
5044 +#define GMAC0_OFFSET 0x28
5045 +#define GMAC2_OFFSET 0x22
5048 +#if defined(CONFIG_RALINK_RT6855A)
5049 +#define IRQ_ENET0 22
5051 +#define IRQ_ENET0 11 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
5054 +#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
5055 +#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
5057 +//#define RAETH_DEBUG
5059 +#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
5061 +#define RAETH_PRINT(fmt, args...) { }
5064 +struct net_device_stats *ra_get_stats(struct net_device *dev);
5066 +void ei_tx_timeout(struct net_device *dev);
5067 +int rather_probe(struct net_device *dev);
5068 +int ei_open(struct net_device *dev);
5069 +int ei_close(struct net_device *dev);
5071 +int ra2882eth_init(void);
5072 +void ra2882eth_cleanup_module(void);
5074 +void ei_xmit_housekeeping(unsigned long data);
5076 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
5077 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
5078 +void fe_sw_init(void);
5081 Index: linux-3.14.16/drivers/net/ethernet/raeth/raether_pdma.c
5082 ===================================================================
5083 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5084 +++ linux-3.14.16/drivers/net/ethernet/raeth/raether_pdma.c 2014-08-24 15:51:48.542654066 +0200
5086 +#include <linux/module.h>
5087 +#include <linux/version.h>
5088 +#include <linux/kernel.h>
5089 +#include <linux/types.h>
5090 +#include <linux/pci.h>
5091 +#include <linux/init.h>
5092 +#include <linux/skbuff.h>
5093 +#include <linux/if_vlan.h>
5094 +#include <linux/if_ether.h>
5095 +#include <linux/fs.h>
5096 +#include <asm/uaccess.h>
5097 +#include <linux/delay.h>
5098 +#include <linux/sched.h>
5099 +#include <asm/rt2880/rt_mmap.h>
5100 +#include "ra2882ethreg.h"
5101 +#include "raether.h"
5102 +#include "ra_mac.h"
5104 +#define MAX_RX_LENGTH 1536
5106 +extern int reg_dbg;
5107 +extern struct net_device *dev_raether;
5108 +static unsigned long tx_ring_full=0;
5110 +#define KSEG1 0xa0000000
5111 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5112 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5114 +extern void set_fe_dma_glo_cfg(void);
5116 +int fe_dma_init(struct net_device *dev)
5120 + unsigned int regVal;
5121 + END_DEVICE* ei_local = netdev_priv(dev);
5125 + regVal = sysRegRead(PDMA_GLO_CFG);
5126 + if((regVal & RX_DMA_BUSY))
5128 + printk("\n RX_DMA_BUSY !!! ");
5131 + if((regVal & TX_DMA_BUSY))
5133 + printk("\n TX_DMA_BUSY !!! ");
5139 + for (i=0;i<NUM_TX_DESC;i++){
5140 + ei_local->skb_free[i]=0;
5142 + ei_local->free_idx =0;
5143 + ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
5144 + printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
5146 + for (i=0; i < NUM_TX_DESC; i++) {
5147 + memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
5148 + ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
5149 + ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
5153 + /* Initial RX Ring 0*/
5154 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5155 + for (i = 0; i < NUM_RX_DESC; i++) {
5156 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5157 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5158 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5159 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5160 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5162 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5165 + regVal = sysRegRead(PDMA_GLO_CFG);
5166 + regVal &= 0x000000FF;
5167 + sysRegWrite(PDMA_GLO_CFG, regVal);
5168 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regVal);
5170 + regVal=sysRegRead(PDMA_GLO_CFG);
5172 + /* Tell the adapter where the TX/RX rings are located. */
5173 + sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5174 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_BASE_PTR0", TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5175 + sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5176 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_MAX_CNT0", TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5177 + sysRegWrite(TX_CTX_IDX0, 0);
5178 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_CTX_IDX0", TX_CTX_IDX0, 0);
5179 + sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
5180 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DTX_IDX0);
5182 + sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5183 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_BASE_PTR0", RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5184 + sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5185 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_MAX_CNT0", RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5186 + sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5187 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_CALC_IDX0", RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5188 + sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
5189 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DRX_IDX0);
5191 + set_fe_dma_glo_cfg();
5196 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5198 + unsigned int length=skb->len;
5199 + END_DEVICE* ei_local = netdev_priv(dev);
5200 + unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
5202 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5204 + ei_local->stat.tx_errors++;
5207 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
5208 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
5209 + if (gmac_no == 1) {
5210 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
5212 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
5214 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
5215 + tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
5216 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5218 + ei_local->stat.tx_errors++;
5220 + sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
5223 + ei_local->stat.tx_packets++;
5224 + ei_local->stat.tx_bytes += length;
5230 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5232 + END_DEVICE *ei_local = netdev_priv(dev);
5233 + unsigned long flags;
5234 + unsigned long tx_cpu_owner_idx;
5235 + unsigned int tx_cpu_owner_idx_next;
5236 + unsigned int num_of_txd;
5237 + unsigned int tx_cpu_owner_idx_next2;
5239 + dev->trans_start = jiffies; /* save the timestamp */
5240 + spin_lock_irqsave(&ei_local->page_lock, flags);
5241 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5243 + tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
5245 + tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
5247 + if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
5248 + rt2880_eth_send(dev, skb, gmac_no);
5250 + tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
5252 + if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
5255 + ei_local->stat.tx_dropped++;
5257 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5261 + ei_local->skb_free[tx_cpu_owner_idx] = skb;
5262 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5266 +void ei_xmit_housekeeping(unsigned long unused)
5268 + struct net_device *dev = dev_raether;
5269 + END_DEVICE *ei_local = netdev_priv(dev);
5270 + struct PDMA_txdesc *tx_desc;
5271 + unsigned long skb_free_idx;
5272 + unsigned long tx_dtx_idx __maybe_unused;
5273 + unsigned long reg_int_mask=0;
5275 + tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
5276 + tx_desc = ei_local->tx_ring0;
5277 + skb_free_idx = ei_local->free_idx;
5278 + if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
5279 + while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
5280 + dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
5281 + ei_local->skb_free[skb_free_idx]=0;
5282 + skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
5285 + netif_wake_queue(dev);
5287 + ei_local->free_idx = skb_free_idx;
5290 + reg_int_mask=sysRegRead(FE_INT_ENABLE);
5291 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
5294 +EXPORT_SYMBOL(ei_start_xmit);
5295 +EXPORT_SYMBOL(ei_xmit_housekeeping);
5296 +EXPORT_SYMBOL(fe_dma_init);
5297 +EXPORT_SYMBOL(rt2880_eth_send);
5298 Index: linux-3.14.16/drivers/net/ethernet/raeth/raether_qdma.c
5299 ===================================================================
5300 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5301 +++ linux-3.14.16/drivers/net/ethernet/raeth/raether_qdma.c 2014-08-24 15:51:48.542654066 +0200
5303 +#include <linux/module.h>
5304 +#include <linux/version.h>
5305 +#include <linux/kernel.h>
5306 +#include <linux/types.h>
5307 +#include <linux/pci.h>
5308 +#include <linux/init.h>
5309 +#include <linux/skbuff.h>
5310 +#include <linux/if_vlan.h>
5311 +#include <linux/if_ether.h>
5312 +#include <linux/fs.h>
5313 +#include <asm/uaccess.h>
5314 +#include <asm/rt2880/surfboardint.h>
5315 +#if defined (CONFIG_RAETH_TSO)
5316 +#include <linux/tcp.h>
5317 +#include <net/ipv6.h>
5318 +#include <linux/ip.h>
5319 +#include <net/ip.h>
5320 +#include <net/tcp.h>
5321 +#include <linux/in.h>
5322 +#include <linux/ppp_defs.h>
5323 +#include <linux/if_pppox.h>
5325 +#include <linux/delay.h>
5326 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5327 +#include <linux/sched.h>
5330 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
5331 +#include <asm/rt2880/rt_mmap.h>
5333 +#include <linux/libata-compat.h>
5336 +#include "ra2882ethreg.h"
5337 +#include "raether.h"
5338 +#include "ra_mac.h"
5339 +#include "ra_ioctl.h"
5340 +#include "ra_rfrw.h"
5341 +#ifdef CONFIG_RAETH_NETLINK
5342 +#include "ra_netlink.h"
5344 +#if defined (CONFIG_RAETH_QOS)
5345 +#include "ra_qos.h"
5348 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5349 +#include "../../../net/nat/hw_nat/ra_nat.h"
5352 +#if defined (TASKLET_WORKQUEUE_SW)
5354 +int working_schedule;
5358 +#if !defined(CONFIG_RA_NAT_NONE)
5361 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
5362 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
5365 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
5368 +#include <asm/mipsregs.h>
5369 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
5370 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
5371 +#endif /* CONFIG_RA_CLASSIFIER */
5373 +#if defined (CONFIG_RALINK_RT3052_MP2)
5374 +int32_t mcast_rx(struct sk_buff * skb);
5375 +int32_t mcast_tx(struct sk_buff * skb);
5378 +#ifdef RA_MTD_RW_BY_NUM
5379 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
5381 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
5384 +/* gmac driver feature set config */
5385 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
5388 +#define DELAY_INT 1
5391 +//#define CONFIG_UNH_TEST
5392 +/* end of config */
5394 +#if defined (CONFIG_RAETH_JUMBOFRAME)
5395 +#define MAX_RX_LENGTH 4096
5397 +#define MAX_RX_LENGTH 1536
5400 +extern struct net_device *dev_raether;
5402 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5403 +static int rx_dma_owner_idx1;
5404 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5405 +static int rx_calc_idx1;
5408 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5409 +static int rx_calc_idx0;
5410 +static unsigned long tx_cpu_owner_idx0=0;
5412 +static unsigned long tx_ring_full=0;
5414 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
5415 +#include "ra_ethtool.h"
5416 +extern struct ethtool_ops ra_ethtool_ops;
5417 +#ifdef CONFIG_PSEUDO_SUPPORT
5418 +extern struct ethtool_ops ra_virt_ethtool_ops;
5419 +#endif // CONFIG_PSEUDO_SUPPORT //
5420 +#endif // (CONFIG_ETHTOOL //
5422 +#ifdef CONFIG_RALINK_VISTA_BASIC
5423 +int is_switch_175c = 1;
5426 +//skb->mark to queue mapping table
5427 +extern unsigned int M2Q_table[64];
5430 +#define KSEG1 0xa0000000
5431 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5432 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5434 +extern void set_fe_dma_glo_cfg(void);
5439 + * @brief: get the TXD index from its address
5443 + * @return: TXD index
5446 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
5448 + struct net_device *dev = dev_raether;
5449 + END_DEVICE *ei_local = netdev_priv(dev);
5451 + ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
5452 + ctx_offset = (*cpu_ptr - ei_local->txd_pool);
5454 + return ctx_offset;
5460 + * @brief get free TXD from TXD queue
5466 +static int get_free_txd(struct QDMA_txdesc **free_txd)
5468 + struct net_device *dev = dev_raether;
5469 + END_DEVICE *ei_local = netdev_priv(dev);
5470 + unsigned int tmp_idx;
5472 + if(ei_local->free_txd_num > 0){
5473 + tmp_idx = ei_local->free_txd_head;
5474 + ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
5475 + ei_local->free_txd_num -= 1;
5476 + *free_txd = &ei_local->txd_pool[tmp_idx];
5479 + return NUM_TX_DESC;
5484 + * @brief add free TXD into TXD queue
5490 +int put_free_txd(int free_txd_idx)
5492 + struct net_device *dev = dev_raether;
5493 + END_DEVICE *ei_local = netdev_priv(dev);
5494 + ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
5495 + ei_local->free_txd_tail = free_txd_idx;
5496 + ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
5497 + ei_local->free_txd_num += 1;
5501 +/*define qdma initial alloc*/
5510 +bool qdma_tx_desc_alloc(void)
5512 + struct net_device *dev = dev_raether;
5513 + END_DEVICE *ei_local = netdev_priv(dev);
5514 + struct QDMA_txdesc *free_txd = NULL;
5515 + unsigned int txd_idx;
5519 + ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
5520 + printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
5522 + if (ei_local->txd_pool == NULL) {
5523 + printk("adapter->txd_pool allocation failed!\n");
5526 + printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
5527 + //set all txd_pool_info to 0.
5528 + for ( i = 0; i < NUM_TX_DESC; i++)
5530 + ei_local->skb_free[i]= 0;
5531 + ei_local->txd_pool_info[i] = i + 1;
5532 + ei_local->txd_pool[i].txd_info3.LS_bit = 1;
5533 + ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
5536 + ei_local->free_txd_head = 0;
5537 + ei_local->free_txd_tail = NUM_TX_DESC - 1;
5538 + ei_local->free_txd_num = NUM_TX_DESC;
5541 + //get free txd from txd pool
5542 + txd_idx = get_free_txd(&free_txd);
5543 + if( txd_idx == NUM_TX_DESC) {
5544 + printk("get_free_txd fail\n");
5548 + //add null TXD for transmit
5549 + ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
5550 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5551 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5552 + sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
5554 + //get free txd from txd pool
5556 + txd_idx = get_free_txd(&free_txd);
5557 + if( txd_idx == NUM_TX_DESC) {
5558 + printk("get_free_txd fail\n");
5561 + // add null TXD for release
5562 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
5563 + sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
5565 + printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
5567 + printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n");
5568 + printk("----------------+---------+--------\n");
5570 + printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
5571 + ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
5576 +bool fq_qdma_init(void)
5578 + struct QDMA_txdesc *free_head = NULL;
5579 + unsigned int free_head_phy;
5580 + unsigned int free_tail_phy;
5581 + unsigned int *free_page_head = NULL;
5582 + unsigned int free_page_head_phy;
5585 + free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
5586 + if (unlikely(free_head == NULL)){
5587 + printk(KERN_ERR "QDMA FQ decriptor not available...\n");
5590 + memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
5592 + free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
5593 + if (unlikely(free_page_head == NULL)){
5594 + printk(KERN_ERR "QDMA FQ pager not available...\n");
5597 + for (i=0; i < NUM_QDMA_PAGE; i++) {
5598 + free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
5599 + if(i < (NUM_QDMA_PAGE-1)){
5600 + free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
5604 + printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
5605 + printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
5606 + printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
5607 + printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
5610 + free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
5613 + free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
5615 + printk("free_head_phy is 0x%x!!!\n", free_head_phy);
5616 + printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
5617 + sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
5618 + sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
5619 + sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
5620 + sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
5624 +int fe_dma_init(struct net_device *dev)
5628 + unsigned int regVal;
5629 + END_DEVICE* ei_local = netdev_priv(dev);
5635 + regVal = sysRegRead(QDMA_GLO_CFG);
5636 + if((regVal & RX_DMA_BUSY))
5638 + printk("\n RX_DMA_BUSY !!! ");
5641 + if((regVal & TX_DMA_BUSY))
5643 + printk("\n TX_DMA_BUSY !!! ");
5648 + /*tx desc alloc, add a NULL TXD to HW*/
5650 + qdma_tx_desc_alloc();
5653 + /* Initial RX Ring 0*/
5654 +#ifdef CONFIG_32B_DESC
5655 + ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5656 + ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
5658 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5660 + for (i = 0; i < NUM_RX_DESC; i++) {
5661 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5662 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5663 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5664 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5665 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5667 + ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
5669 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5671 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5673 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5674 + /* Initial RX Ring 1*/
5675 +#ifdef CONFIG_32B_DESC
5676 + ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5677 + ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
5679 + ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
5681 + for (i = 0; i < NUM_RX_DESC; i++) {
5682 + memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
5683 + ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
5684 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5685 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5686 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5688 + ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
5690 + ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5692 + printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
5695 + regVal = sysRegRead(QDMA_GLO_CFG);
5696 + regVal &= 0x000000FF;
5697 + sysRegWrite(QDMA_GLO_CFG, regVal);
5698 + regVal=sysRegRead(QDMA_GLO_CFG);
5700 + /* Tell the adapter where the TX/RX rings are located. */
5702 + sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5703 + sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_RX_DESC));
5704 + sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5705 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5706 + rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0);
5708 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
5709 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5710 + sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
5711 + sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_RX_DESC));
5712 + sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5713 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5714 + rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1);
5716 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
5719 + set_fe_dma_glo_cfg();
5724 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5726 + unsigned int length=skb->len;
5727 + END_DEVICE* ei_local = netdev_priv(dev);
5729 + struct QDMA_txdesc *cpu_ptr;
5731 + struct QDMA_txdesc *dma_ptr __maybe_unused;
5732 + struct QDMA_txdesc *free_txd;
5734 +#if defined (CONFIG_RAETH_TSO)
5735 + struct iphdr *iph = NULL;
5736 + struct QDMA_txdesc *init_cpu_ptr;
5737 + struct tcphdr *th = NULL;
5738 + struct skb_frag_struct *frag;
5739 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5742 +#endif // CONFIG_RAETH_TSO //
5744 +#if defined (CONFIG_RAETH_TSOV6)
5745 + struct ipv6hdr *ip6h = NULL;
5748 +#ifdef CONFIG_PSEUDO_SUPPORT
5749 + PSEUDO_ADAPTER *pAd;
5751 + cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
5752 + dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
5753 + ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
5754 + ei_local->skb_free[ctx_offset] = skb;
5755 +#if defined (CONFIG_RAETH_TSO)
5756 + init_cpu_ptr = cpu_ptr;
5757 + init_txd_idx = ctx_offset;
5760 +#if !defined (CONFIG_RAETH_TSO)
5763 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5764 + cpu_ptr->txd_info3.SDL = skb->len;
5766 + if (gmac_no == 1) {
5767 + cpu_ptr->txd_info4.FPORT = 1;
5769 + cpu_ptr->txd_info4.FPORT = 2;
5773 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5775 + iph = (struct iphdr *)skb_network_header(skb);
5776 + if (iph->tos == 0xe0)
5777 + cpu_ptr->txd_info3.QID = 3;
5778 + else if (iph->tos == 0xa0)
5779 + cpu_ptr->txd_info3.QID = 2;
5780 + else if (iph->tos == 0x20)
5781 + cpu_ptr->txd_info3.QID = 1;
5783 + cpu_ptr->txd_info3.QID = 0;
5786 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5787 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5788 + cpu_ptr->txd_info4.TUI_CO = 7;
5790 + cpu_ptr->txd_info4.TUI_CO = 0;
5794 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5795 + if(vlan_tx_tag_present(skb)) {
5796 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5798 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5802 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5803 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5804 + if(ra_sw_nat_hook_rx!= NULL){
5805 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5806 + FOE_MAGIC_TAG(skb) = 0;
5811 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5812 + cpu_ptr->txd_info4.UDF = 0x2F;
5815 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5816 + cpu_ptr->txd_info3.SWC_bit = 1;
5818 + //3. get NULL TXD and decrease free_tx_num by 1.
5819 + ctx_offset = get_free_txd(&free_txd);
5820 + if(ctx_offset == NUM_TX_DESC) {
5821 + printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
5825 + //4. hook new TXD in the end of queue
5826 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5829 + //5. move CPU_PTR to new TXD
5830 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5831 + cpu_ptr->txd_info3.OWN_bit = 0;
5832 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5835 + printk("----------------------------------------------\n");
5836 + printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
5837 + printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
5838 + printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
5839 + printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
5842 +#else //#if !defined (CONFIG_RAETH_TSO)
5843 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5844 + cpu_ptr->txd_info3.SDL = (length - skb->data_len);
5845 + cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
5846 + if (gmac_no == 1) {
5847 + cpu_ptr->txd_info4.FPORT = 1;
5849 + cpu_ptr->txd_info4.FPORT = 2;
5852 + cpu_ptr->txd_info4.TSO = 0;
5853 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5854 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5855 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5856 + cpu_ptr->txd_info4.TUI_CO = 7;
5858 + cpu_ptr->txd_info4.TUI_CO = 0;
5862 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5863 + if(vlan_tx_tag_present(skb)) {
5864 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5866 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5870 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5871 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5872 + if(ra_sw_nat_hook_rx!= NULL){
5873 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5874 + FOE_MAGIC_TAG(skb) = 0;
5879 + cpu_ptr->txd_info3.SWC_bit = 1;
5881 + ctx_offset = get_free_txd(&free_txd);
5882 + if(ctx_offset == NUM_TX_DESC) {
5883 + printk("get_free_txd fail\n");
5886 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5887 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5889 + if(nr_frags > 0) {
5890 + for(i=0;i<nr_frags;i++) {
5891 + frag = &skb_shinfo(skb)->frags[i];
5892 + cpu_ptr = free_txd;
5893 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5894 + cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
5895 + cpu_ptr->txd_info3.SDL = frag->size;
5896 + cpu_ptr->txd_info3.LS_bit = (i==nr_frags-1)?1:0;
5897 + cpu_ptr->txd_info3.OWN_bit = 0;
5898 + cpu_ptr->txd_info3.SWC_bit = 1;
5899 + ei_local->skb_free[ctx_offset] = (i==nr_frags-1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5901 + ctx_offset = get_free_txd(&free_txd);
5902 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5903 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5905 + ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5908 + if(skb_shinfo(skb)->gso_segs > 1) {
5910 +// TsoLenUpdate(skb->len);
5912 + /* TCP over IPv4 */
5913 + iph = (struct iphdr *)skb_network_header(skb);
5914 +#if defined (CONFIG_RAETH_TSOV6)
5915 + /* TCP over IPv6 */
5916 + ip6h = (struct ipv6hdr *)skb_network_header(skb);
5918 + if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
5919 + th = (struct tcphdr *)skb_transport_header(skb);
5921 + init_cpu_ptr->txd_info4.TSO = 1;
5923 + th->check = htons(skb_shinfo(skb)->gso_size);
5924 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5927 +#if defined (CONFIG_RAETH_TSOV6)
5928 + /* TCP over IPv6 */
5929 + //ip6h = (struct ipv6hdr *)skb_network_header(skb);
5930 + else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
5931 + th = (struct tcphdr *)skb_transport_header(skb);
5932 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5933 + init_cpu_ptr->txd_info4.TSO = 1;
5935 + init_cpu_ptr->txd_info4.TSO = 1;
5937 + th->check = htons(skb_shinfo(skb)->gso_size);
5938 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5944 +// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5946 + init_cpu_ptr->txd_info3.OWN_bit = 0;
5947 +#endif // CONFIG_RAETH_TSO //
5949 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5951 +#ifdef CONFIG_PSEUDO_SUPPORT
5952 + if (gmac_no == 2) {
5953 + if (ei_local->PseudoDev != NULL) {
5954 + pAd = netdev_priv(ei_local->PseudoDev);
5955 + pAd->stat.tx_packets++;
5956 + pAd->stat.tx_bytes += length;
5962 + ei_local->stat.tx_packets++;
5963 + ei_local->stat.tx_bytes += skb->len;
5968 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5970 + END_DEVICE *ei_local = netdev_priv(dev);
5971 + unsigned long flags;
5972 + unsigned int num_of_txd;
5973 +#if defined (CONFIG_RAETH_TSO)
5974 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5976 +#ifdef CONFIG_PSEUDO_SUPPORT
5977 + PSEUDO_ADAPTER *pAd;
5980 +#if !defined(CONFIG_RA_NAT_NONE)
5981 + if(ra_sw_nat_hook_tx!= NULL)
5983 + spin_lock_irqsave(&ei_local->page_lock, flags);
5984 + if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
5985 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5988 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5996 + dev->trans_start = jiffies; /* save the timestamp */
5997 + spin_lock_irqsave(&ei_local->page_lock, flags);
5998 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
6001 +//check free_txd_num before calling rt288_eth_send()
6003 +#if defined (CONFIG_RAETH_TSO)
6004 + num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
6009 +#if defined(CONFIG_RALINK_MT7621)
6010 + if(sysRegRead(0xbe00000c)==0x00030101) {
6011 + ei_xmit_housekeeping(0);
6016 + if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
6018 + rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
6019 + if (ei_local->free_txd_num < 3)
6021 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
6022 + netif_stop_queue(dev);
6023 +#ifdef CONFIG_PSEUDO_SUPPORT
6024 + netif_stop_queue(ei_local->PseudoDev);
6030 +#ifdef CONFIG_PSEUDO_SUPPORT
6033 + if (ei_local->PseudoDev != NULL)
6035 + pAd = netdev_priv(ei_local->PseudoDev);
6036 + pAd->stat.tx_dropped++;
6040 + ei_local->stat.tx_dropped++;
6042 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6045 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6049 +void ei_xmit_housekeeping(unsigned long unused)
6051 + struct net_device *dev = dev_raether;
6052 + END_DEVICE *ei_local = netdev_priv(dev);
6053 +#ifndef CONFIG_RAETH_NAPI
6054 + unsigned long reg_int_mask=0;
6056 + struct QDMA_txdesc *dma_ptr = NULL;
6057 + struct QDMA_txdesc *cpu_ptr = NULL;
6058 + struct QDMA_txdesc *tmp_ptr = NULL;
6059 + unsigned int htx_offset = 0;
6061 + dma_ptr = PHYS_TO_VIRT(sysRegRead(QTX_DRX_PTR));
6062 + cpu_ptr = PHYS_TO_VIRT(sysRegRead(QTX_CRX_PTR));
6063 + if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6064 + while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6066 + //1. keep cpu next TXD
6067 + tmp_ptr = PHYS_TO_VIRT(cpu_ptr->txd_info2.NDP);
6068 + htx_offset = GET_TXD_OFFSET(&tmp_ptr);
6069 + //2. free skb meomry
6070 +#if defined (CONFIG_RAETH_TSO)
6071 + if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) {
6072 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6075 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6079 + htx_offset = GET_TXD_OFFSET(&cpu_ptr);
6080 + put_free_txd(htx_offset);
6082 + netif_wake_queue(dev);
6083 +#ifdef CONFIG_PSEUDO_SUPPORT
6084 + netif_wake_queue(ei_local->PseudoDev);
6088 + //4. update cpu_ptr to next ptr
6089 + cpu_ptr = tmp_ptr;
6092 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(cpu_ptr));
6093 +#ifndef CONFIG_RAETH_NAPI
6094 + reg_int_mask=sysRegRead(QFE_INT_ENABLE);
6095 +#if defined (DELAY_INT)
6096 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
6099 + sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
6101 +#endif //CONFIG_RAETH_NAPI//
6104 +EXPORT_SYMBOL(ei_start_xmit);
6105 +EXPORT_SYMBOL(ei_xmit_housekeeping);
6106 +EXPORT_SYMBOL(fe_dma_init);
6107 +EXPORT_SYMBOL(rt2880_eth_send);
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