1 From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
6 Add support for Ralink FE and ESW.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 32 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 566 ++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 30 +
20 drivers/net/ethernet/ralink/mdio.c | 244 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/mt7530.c | 579 ++++++++
25 drivers/net/ethernet/ralink/mt7530.h | 20 +
26 drivers/net/ethernet/ralink/ralink_soc_eth.c | 844 +++++++++++
27 drivers/net/ethernet/ralink/ralink_soc_eth.h | 384 +++++
28 drivers/net/ethernet/ralink/soc_mt7620.c | 172 +++
29 drivers/net/ethernet/ralink/soc_rt2880.c | 52 +
30 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
31 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
32 22 files changed, 4926 insertions(+)
33 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
34 create mode 100644 drivers/net/ethernet/ralink/Kconfig
35 create mode 100644 drivers/net/ethernet/ralink/Makefile
36 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
37 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
38 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
39 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio.h
42 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
43 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
44 create mode 100644 drivers/net/ethernet/ralink/mt7530.c
45 create mode 100644 drivers/net/ethernet/ralink/mt7530.h
46 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
47 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
48 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
49 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
50 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
51 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
54 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
57 + * Ralink RT305x SoC platform device registration
59 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
61 + * This program is free software; you can redistribute it and/or modify it
62 + * under the terms of the GNU General Public License version 2 as published
63 + * by the Free Software Foundation.
66 +#ifndef _RT305X_ESW_PLATFORM_H
67 +#define _RT305X_ESW_PLATFORM_H
70 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
71 + RT305X_ESW_VLAN_CONFIG_LLLLW,
72 + RT305X_ESW_VLAN_CONFIG_WLLLL,
75 +struct rt305x_esw_platform_data
78 + u32 reg_initval_fct2;
79 + u32 reg_initval_fpa2;
82 +#endif /* _RT305X_ESW_PLATFORM_H */
83 --- a/arch/mips/ralink/rt305x.c
84 +++ b/arch/mips/ralink/rt305x.c
85 @@ -199,6 +199,7 @@ void __init ralink_clk_init(void)
88 ralink_clk_add("cpu", cpu_rate);
89 + ralink_clk_add("sys", sys_rate);
90 ralink_clk_add("10000b00.spi", sys_rate);
91 ralink_clk_add("10000100.timer", wdt_rate);
92 ralink_clk_add("10000120.watchdog", wdt_rate);
93 --- a/drivers/net/ethernet/Kconfig
94 +++ b/drivers/net/ethernet/Kconfig
95 @@ -134,6 +134,7 @@ config ETHOC
96 source "drivers/net/ethernet/packetengines/Kconfig"
97 source "drivers/net/ethernet/pasemi/Kconfig"
98 source "drivers/net/ethernet/qlogic/Kconfig"
99 +source "drivers/net/ethernet/ralink/Kconfig"
100 source "drivers/net/ethernet/realtek/Kconfig"
101 source "drivers/net/ethernet/renesas/Kconfig"
102 source "drivers/net/ethernet/rdc/Kconfig"
103 --- a/drivers/net/ethernet/Makefile
104 +++ b/drivers/net/ethernet/Makefile
105 @@ -56,6 +56,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
106 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
107 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
108 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
109 +obj-$(CONFIG_NET_RALINK) += ralink/
110 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
111 obj-$(CONFIG_SH_ETH) += renesas/
112 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
114 +++ b/drivers/net/ethernet/ralink/Kconfig
117 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
120 + This driver supports the ethernet mac inside the ralink wisocs
124 +config NET_RALINK_MDIO
125 + def_bool NET_RALINK
126 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
129 +config NET_RALINK_MDIO_RT2880
130 + def_bool NET_RALINK
131 + depends on (SOC_RT288X || SOC_RT3883)
132 + select NET_RALINK_MDIO
134 +config NET_RALINK_ESW_RT3052
135 + def_bool NET_RALINK
136 + depends on SOC_RT305X
140 +config NET_RALINK_GSW_MT7620
141 + def_bool NET_RALINK
142 + depends on SOC_MT7620
144 + select NET_RALINK_MDIO
149 +++ b/drivers/net/ethernet/ralink/Makefile
152 +# Makefile for the Ralink SoCs built-in ethernet macs
155 +ralink-eth-y += ralink_soc_eth.o
157 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
158 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
160 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
161 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
163 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
164 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
165 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
166 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
168 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
170 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
173 + * This program is free software; you can redistribute it and/or modify
174 + * it under the terms of the GNU General Public License as published by
175 + * the Free Software Foundation; version 2 of the License
177 + * This program is distributed in the hope that it will be useful,
178 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
179 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
180 + * GNU General Public License for more details.
182 + * You should have received a copy of the GNU General Public License
183 + * along with this program; if not, write to the Free Software
184 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
186 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
189 +#include <linux/module.h>
190 +#include <linux/kernel.h>
191 +#include <linux/types.h>
192 +#include <linux/dma-mapping.h>
193 +#include <linux/init.h>
194 +#include <linux/skbuff.h>
195 +#include <linux/etherdevice.h>
196 +#include <linux/ethtool.h>
197 +#include <linux/platform_device.h>
198 +#include <linux/of_device.h>
199 +#include <linux/clk.h>
200 +#include <linux/of_net.h>
201 +#include <linux/of_mdio.h>
203 +#include <asm/mach-ralink/ralink_regs.h>
205 +#include "ralink_soc_eth.h"
207 +#include <linux/ioport.h>
208 +#include <linux/switch.h>
209 +#include <linux/mii.h>
211 +#include <ralink_regs.h>
212 +#include <asm/mach-ralink/rt305x.h>
213 +#include <asm/mach-ralink/rt305x_esw_platform.h>
216 + * HW limitations for this switch:
217 + * - No large frame support (PKT_MAX_LEN at most 1536)
218 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
219 + * though this might be possible using the undocumented PPE.
222 +#define RT305X_ESW_REG_ISR 0x00
223 +#define RT305X_ESW_REG_IMR 0x04
224 +#define RT305X_ESW_REG_FCT0 0x08
225 +#define RT305X_ESW_REG_PFC1 0x14
226 +#define RT305X_ESW_REG_ATS 0x24
227 +#define RT305X_ESW_REG_ATS0 0x28
228 +#define RT305X_ESW_REG_ATS1 0x2c
229 +#define RT305X_ESW_REG_ATS2 0x30
230 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
231 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
232 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
233 +#define RT305X_ESW_REG_POA 0x80
234 +#define RT305X_ESW_REG_FPA 0x84
235 +#define RT305X_ESW_REG_SOCPC 0x8c
236 +#define RT305X_ESW_REG_POC0 0x90
237 +#define RT305X_ESW_REG_POC1 0x94
238 +#define RT305X_ESW_REG_POC2 0x98
239 +#define RT305X_ESW_REG_SGC 0x9c
240 +#define RT305X_ESW_REG_STRT 0xa0
241 +#define RT305X_ESW_REG_PCR0 0xc0
242 +#define RT305X_ESW_REG_PCR1 0xc4
243 +#define RT305X_ESW_REG_FPA2 0xc8
244 +#define RT305X_ESW_REG_FCT2 0xcc
245 +#define RT305X_ESW_REG_SGC2 0xe4
246 +#define RT305X_ESW_REG_P0LED 0xa4
247 +#define RT305X_ESW_REG_P1LED 0xa8
248 +#define RT305X_ESW_REG_P2LED 0xac
249 +#define RT305X_ESW_REG_P3LED 0xb0
250 +#define RT305X_ESW_REG_P4LED 0xb4
251 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
252 +#define RT305X_ESW_REG_P1PC 0xec
253 +#define RT305X_ESW_REG_P2PC 0xf0
254 +#define RT305X_ESW_REG_P3PC 0xf4
255 +#define RT305X_ESW_REG_P4PC 0xf8
256 +#define RT305X_ESW_REG_P5PC 0xfc
258 +#define RT305X_ESW_LED_LINK 0
259 +#define RT305X_ESW_LED_100M 1
260 +#define RT305X_ESW_LED_DUPLEX 2
261 +#define RT305X_ESW_LED_ACTIVITY 3
262 +#define RT305X_ESW_LED_COLLISION 4
263 +#define RT305X_ESW_LED_LINKACT 5
264 +#define RT305X_ESW_LED_DUPLCOLL 6
265 +#define RT305X_ESW_LED_10MACT 7
266 +#define RT305X_ESW_LED_100MACT 8
267 +/* Additional led states not in datasheet: */
268 +#define RT305X_ESW_LED_BLINK 10
269 +#define RT305X_ESW_LED_ON 12
271 +#define RT305X_ESW_LINK_S 25
272 +#define RT305X_ESW_DUPLEX_S 9
273 +#define RT305X_ESW_SPD_S 0
275 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
276 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
277 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
279 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
281 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
282 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
284 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
285 +#define RT305X_ESW_PVIDC_PVID_S 12
287 +#define RT305X_ESW_VLANI_VID_M 0xfff
288 +#define RT305X_ESW_VLANI_VID_S 12
290 +#define RT305X_ESW_VMSC_MSC_M 0xff
291 +#define RT305X_ESW_VMSC_MSC_S 8
293 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
294 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
295 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
296 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
298 +#define RT305X_ESW_POC0_EN_BP_S 0
299 +#define RT305X_ESW_POC0_EN_FC_S 8
300 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
301 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
302 +#define RT305X_ESW_POC0_DIS_PORT_S 23
304 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
305 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
306 +#define RT305X_ESW_POC2_ENAGING_S 8
307 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
309 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
310 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
311 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
312 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
314 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
315 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
316 +#define RT305X_ESW_PFC1_EN_TOS_S 24
318 +#define RT305X_ESW_VLAN_NONE 0xfff
320 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
321 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
323 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
324 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
326 +#define RT305X_ESW_POA_LINK_MASK 0x1f
327 +#define RT305X_ESW_POA_LINK_SHIFT 25
329 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
330 +#define RT305X_ESW_PORT0 0
331 +#define RT305X_ESW_PORT1 1
332 +#define RT305X_ESW_PORT2 2
333 +#define RT305X_ESW_PORT3 3
334 +#define RT305X_ESW_PORT4 4
335 +#define RT305X_ESW_PORT5 5
336 +#define RT305X_ESW_PORT6 6
338 +#define RT305X_ESW_PORTS_NONE 0
340 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
341 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
342 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
344 +#define RT305X_ESW_PORTS_INTERNAL \
345 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
346 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
347 + BIT(RT305X_ESW_PORT4))
349 +#define RT305X_ESW_PORTS_NOCPU \
350 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
352 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
354 +#define RT305X_ESW_PORTS_ALL \
355 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
357 +#define RT305X_ESW_NUM_VLANS 16
358 +#define RT305X_ESW_NUM_VIDS 4096
359 +#define RT305X_ESW_NUM_PORTS 7
360 +#define RT305X_ESW_NUM_LANWAN 6
361 +#define RT305X_ESW_NUM_LEDS 5
363 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
364 +#define RT5350_EWS_REG_LED_POLARITY 0x168
365 +#define RT5350_RESET_EPHY BIT(24)
366 +#define SYSC_REG_RESET_CTRL 0x34
369 + /* Global attributes. */
370 + RT305X_ESW_ATTR_ENABLE_VLAN,
371 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
372 + RT305X_ESW_ATTR_BC_STATUS,
373 + RT305X_ESW_ATTR_LED_FREQ,
374 + /* Port attributes. */
375 + RT305X_ESW_ATTR_PORT_DISABLE,
376 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
377 + RT305X_ESW_ATTR_PORT_UNTAG,
378 + RT305X_ESW_ATTR_PORT_LED,
379 + RT305X_ESW_ATTR_PORT_LAN,
380 + RT305X_ESW_ATTR_PORT_RECV_BAD,
381 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
382 + RT5350_ESW_ATTR_PORT_TR_BAD,
383 + RT5350_ESW_ATTR_PORT_TR_GOOD,
400 + struct device *dev;
401 + void __iomem *base;
403 + const struct rt305x_esw_platform_data *pdata;
404 + /* Protects against concurrent register rmw operations. */
405 + spinlock_t reg_rw_lock;
407 + unsigned char port_map;
408 + unsigned int reg_initval_fct2;
409 + unsigned int reg_initval_fpa2;
410 + unsigned int reg_led_polarity;
413 + struct switch_dev swdev;
414 + bool global_vlan_enable;
415 + bool alt_vlan_disable;
416 + int bc_storm_protect;
418 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
419 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
423 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
425 + __raw_writel(val, esw->base + reg);
428 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
430 + return __raw_readl(esw->base + reg);
433 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
438 + t = __raw_readl(esw->base + reg) & ~mask;
439 + __raw_writel(t | val, esw->base + reg);
442 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
445 + unsigned long flags;
447 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
448 + esw_rmw_raw(esw, reg, mask, val);
449 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
452 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
455 + unsigned long t_start = jiffies;
459 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
460 + RT305X_ESW_PCR1_WT_DONE))
462 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
468 + write_data &= 0xffff;
470 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
471 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
472 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
473 + RT305X_ESW_REG_PCR0);
477 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
478 + RT305X_ESW_PCR1_WT_DONE)
481 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
488 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
492 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
497 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
498 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
499 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
504 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
508 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
510 + RT305X_ESW_REG_VLANI(vlan / 2),
511 + RT305X_ESW_VLANI_VID_M << s,
512 + (vid & RT305X_ESW_VLANI_VID_M) << s);
515 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
519 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
520 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
521 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
524 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
528 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
530 + RT305X_ESW_REG_PVIDC(port / 2),
531 + RT305X_ESW_PVIDC_PVID_M << s,
532 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
535 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
539 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
540 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
541 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
546 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
550 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
552 + RT305X_ESW_REG_VMSC(vlan / 4),
553 + RT305X_ESW_VMSC_MSC_M << s,
554 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
557 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
560 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
561 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
562 + RT305X_ESW_POC0_DIS_PORT_M;
565 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
568 + unsigned enable_mask;
572 + old_mask = esw_get_port_disable(esw);
573 + changed = old_mask ^ disable_mask;
574 + enable_mask = old_mask & disable_mask;
576 + /* enable before writing to MII */
577 + esw_rmw(esw, RT305X_ESW_REG_POC0,
578 + (RT305X_ESW_POC0_DIS_PORT_M <<
579 + RT305X_ESW_POC0_DIS_PORT_S),
580 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
582 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
583 + if (!(changed & (1 << i)))
585 + if (disable_mask & (1 << i)) {
587 + rt305x_mii_write(esw, i, MII_BMCR,
591 + rt305x_mii_write(esw, i, MII_BMCR,
599 + /* disable after writing to MII */
600 + esw_rmw(esw, RT305X_ESW_REG_POC0,
601 + (RT305X_ESW_POC0_DIS_PORT_M <<
602 + RT305X_ESW_POC0_DIS_PORT_S),
603 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
606 +static void esw_set_gsc(struct rt305x_esw *esw)
608 + esw_rmw(esw, RT305X_ESW_REG_SGC,
609 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
610 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
611 + esw_rmw(esw, RT305X_ESW_REG_SGC,
612 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
613 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
616 +static int esw_apply_config(struct switch_dev *dev);
618 +static void esw_hw_init(struct rt305x_esw *esw)
621 + u8 port_disable = 0;
622 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
624 + /* vodoo from original driver */
625 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
626 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
627 + /* Port priority 1 for all ports, vlan enabled. */
628 + esw_w32(esw, 0x00005555 |
629 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
630 + RT305X_ESW_REG_PFC1);
632 + /* Enable Back Pressure, and Flow Control */
634 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
635 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
636 + RT305X_ESW_REG_POC0);
638 + /* Enable Aging, and VLAN TAG removal */
640 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
641 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
642 + RT305X_ESW_REG_POC2);
644 + if (esw->reg_initval_fct2)
645 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
647 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
650 + * 300s aging timer, max packet len 1536, broadcast storm prevention
651 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
652 + * pressure jam, GMII disable was_transmit, back pressure disabled,
653 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
656 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
658 + /* Setup SoC Port control register */
660 + (RT305X_ESW_SOCPC_CRC_PADDING |
661 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
662 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
663 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
664 + RT305X_ESW_REG_SOCPC);
666 + if (esw->reg_initval_fpa2)
667 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
669 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
670 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
672 + /* Force Link/Activity on ports */
673 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
674 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
675 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
676 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
677 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
679 + /* Copy disabled port configuration from bootloader setup */
680 + port_disable = esw_get_port_disable(esw);
681 + for (i = 0; i < 6; i++)
682 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
684 + if (soc_is_rt3352()) {
686 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
687 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
688 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
690 + rt305x_mii_write(esw, 0, 31, 0x8000);
691 + for (i = 0; i < 5; i++) {
692 + if (esw->ports[i].disable) {
693 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
695 + rt305x_mii_write(esw, i, MII_BMCR,
700 + /* TX10 waveform coefficient LSB=0 disable PHY */
701 + rt305x_mii_write(esw, i, 26, 0x1601);
702 + /* TX100/TX10 AD/DA current bias */
703 + rt305x_mii_write(esw, i, 29, 0x7016);
704 + /* TX100 slew rate control */
705 + rt305x_mii_write(esw, i, 30, 0x0038);
708 + /* select global register */
709 + rt305x_mii_write(esw, 0, 31, 0x0);
710 + /* enlarge agcsel threshold 3 and threshold 2 */
711 + rt305x_mii_write(esw, 0, 1, 0x4a40);
712 + /* enlarge agcsel threshold 5 and threshold 4 */
713 + rt305x_mii_write(esw, 0, 2, 0x6254);
714 + /* enlarge agcsel threshold */
715 + rt305x_mii_write(esw, 0, 3, 0xa17f);
716 + rt305x_mii_write(esw, 0,12, 0x7eaa);
717 + /* longer TP_IDL tail length */
718 + rt305x_mii_write(esw, 0, 14, 0x65);
719 + /* increased squelch pulse count threshold. */
720 + rt305x_mii_write(esw, 0, 16, 0x0684);
721 + /* set TX10 signal amplitude threshold to minimum */
722 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
723 + /* set squelch amplitude to higher threshold */
724 + rt305x_mii_write(esw, 0, 18, 0x40ba);
725 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
726 + rt305x_mii_write(esw, 0, 22, 0x253f);
727 + /* set PLL/Receive bias current are calibrated */
728 + rt305x_mii_write(esw, 0, 27, 0x2fda);
729 + /* change PLL/Receive bias current to internal(RT3350) */
730 + rt305x_mii_write(esw, 0, 28, 0xc410);
731 + /* change PLL bias current to internal(RT3052_MP3) */
732 + rt305x_mii_write(esw, 0, 29, 0x598b);
733 + /* select local register */
734 + rt305x_mii_write(esw, 0, 31, 0x8000);
735 + } else if (soc_is_rt5350()) {
737 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
738 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
739 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
741 + /* set the led polarity */
742 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
744 + /* local registers */
745 + rt305x_mii_write(esw, 0, 31, 0x8000);
746 + for (i = 0; i < 5; i++) {
747 + if (esw->ports[i].disable) {
748 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
750 + rt305x_mii_write(esw, i, MII_BMCR,
755 + /* TX10 waveform coefficient LSB=0 disable PHY */
756 + rt305x_mii_write(esw, i, 26, 0x1601);
757 + /* TX100/TX10 AD/DA current bias */
758 + rt305x_mii_write(esw, i, 29, 0x7015);
759 + /* TX100 slew rate control */
760 + rt305x_mii_write(esw, i, 30, 0x0038);
763 + /* global registers */
764 + rt305x_mii_write(esw, 0, 31, 0x0);
765 + /* enlarge agcsel threshold 3 and threshold 2 */
766 + rt305x_mii_write(esw, 0, 1, 0x4a40);
767 + /* enlarge agcsel threshold 5 and threshold 4 */
768 + rt305x_mii_write(esw, 0, 2, 0x6254);
769 + /* enlarge agcsel threshold 6 */
770 + rt305x_mii_write(esw, 0, 3, 0xa17f);
771 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
772 + /* longer TP_IDL tail length */
773 + rt305x_mii_write(esw, 0, 14, 0x65);
774 + /* increased squelch pulse count threshold. */
775 + rt305x_mii_write(esw, 0, 16, 0x0684);
776 + /* set TX10 signal amplitude threshold to minimum */
777 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
778 + /* set squelch amplitude to higher threshold */
779 + rt305x_mii_write(esw, 0, 18, 0x40ba);
780 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
781 + rt305x_mii_write(esw, 0, 22, 0x253f);
782 + /* set PLL/Receive bias current are calibrated */
783 + rt305x_mii_write(esw, 0, 27, 0x2fda);
784 + /* change PLL/Receive bias current to internal(RT3350) */
785 + rt305x_mii_write(esw, 0, 28, 0xc410);
786 + /* change PLL bias current to internal(RT3052_MP3) */
787 + rt305x_mii_write(esw, 0, 29, 0x598b);
788 + /* select local register */
789 + rt305x_mii_write(esw, 0, 31, 0x8000);
791 + rt305x_mii_write(esw, 0, 31, 0x8000);
792 + for (i = 0; i < 5; i++) {
793 + if (esw->ports[i].disable) {
794 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
796 + rt305x_mii_write(esw, i, MII_BMCR,
801 + /* TX10 waveform coefficient */
802 + rt305x_mii_write(esw, i, 26, 0x1601);
803 + /* TX100/TX10 AD/DA current bias */
804 + rt305x_mii_write(esw, i, 29, 0x7058);
805 + /* TX100 slew rate control */
806 + rt305x_mii_write(esw, i, 30, 0x0018);
810 + /* select global register */
811 + rt305x_mii_write(esw, 0, 31, 0x0);
812 + /* tune TP_IDL tail and head waveform */
813 + rt305x_mii_write(esw, 0, 22, 0x052f);
814 + /* set TX10 signal amplitude threshold to minimum */
815 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
816 + /* set squelch amplitude to higher threshold */
817 + rt305x_mii_write(esw, 0, 18, 0x40ba);
818 + /* longer TP_IDL tail length */
819 + rt305x_mii_write(esw, 0, 14, 0x65);
820 + /* select local register */
821 + rt305x_mii_write(esw, 0, 31, 0x8000);
825 + port_map = esw->port_map;
827 + port_map = RT305X_ESW_PMAP_LLLLLL;
830 + * Unused HW feature, but still nice to be consistent here...
831 + * This is also exported to userspace ('lan' attribute) so it's
832 + * conveniently usable to decide which ports go into the wan vlan by
835 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
836 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
837 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
839 + /* make the switch leds blink */
840 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
841 + esw->ports[i].led = 0x05;
843 + /* Apply the empty config. */
844 + esw_apply_config(&esw->swdev);
846 + /* Only unmask the port change interrupt */
847 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
850 +static irqreturn_t esw_interrupt(int irq, void *_esw)
852 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
855 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
856 + if (status & RT305X_ESW_PORT_ST_CHG) {
857 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
858 + link >>= RT305X_ESW_POA_LINK_SHIFT;
859 + link &= RT305X_ESW_POA_LINK_MASK;
860 + dev_info(esw->dev, "link changed 0x%02X\n", link);
862 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
864 + return IRQ_HANDLED;
867 +static int esw_apply_config(struct switch_dev *dev)
869 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
876 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
878 + if (esw->global_vlan_enable) {
879 + vid = esw->vlans[i].vid;
880 + vmsc = esw->vlans[i].ports;
882 + vid = RT305X_ESW_VLAN_NONE;
883 + vmsc = RT305X_ESW_PORTS_NONE;
885 + esw_set_vlan_id(esw, i, vid);
886 + esw_set_vmsc(esw, i, vmsc);
889 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
891 + disable |= esw->ports[i].disable << i;
892 + if (esw->global_vlan_enable) {
893 + doubletag |= esw->ports[i].doubletag << i;
895 + untag |= esw->ports[i].untag << i;
896 + pvid = esw->ports[i].pvid;
898 + int x = esw->alt_vlan_disable ? 0 : 1;
899 + doubletag |= x << i;
904 + esw_set_pvid(esw, i, pvid);
905 + if (i < RT305X_ESW_NUM_LEDS)
906 + esw_w32(esw, esw->ports[i].led,
907 + RT305X_ESW_REG_P0LED + 4*i);
911 + esw_set_port_disable(esw, disable);
912 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
913 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
914 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
915 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
916 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
917 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
918 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
919 + esw_rmw(esw, RT305X_ESW_REG_POC2,
920 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
921 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
923 + if (!esw->global_vlan_enable) {
925 + * Still need to put all ports into vlan 0 or they'll be
927 + * NOTE: vlan 0 is special, no vlan tag is prepended
929 + esw_set_vlan_id(esw, 0, 0);
930 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
936 +static int esw_reset_switch(struct switch_dev *dev)
938 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
940 + esw->global_vlan_enable = 0;
941 + memset(esw->ports, 0, sizeof(esw->ports));
942 + memset(esw->vlans, 0, sizeof(esw->vlans));
948 +static int esw_get_vlan_enable(struct switch_dev *dev,
949 + const struct switch_attr *attr,
950 + struct switch_val *val)
952 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
954 + val->value.i = esw->global_vlan_enable;
959 +static int esw_set_vlan_enable(struct switch_dev *dev,
960 + const struct switch_attr *attr,
961 + struct switch_val *val)
963 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
965 + esw->global_vlan_enable = val->value.i != 0;
970 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
971 + const struct switch_attr *attr,
972 + struct switch_val *val)
974 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
976 + val->value.i = esw->alt_vlan_disable;
981 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
982 + const struct switch_attr *attr,
983 + struct switch_val *val)
985 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
987 + esw->alt_vlan_disable = val->value.i != 0;
993 +rt305x_esw_set_bc_status(struct switch_dev *dev,
994 + const struct switch_attr *attr,
995 + struct switch_val *val)
997 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
999 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1005 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1006 + const struct switch_attr *attr,
1007 + struct switch_val *val)
1009 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1011 + val->value.i = esw->bc_storm_protect;
1017 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1018 + const struct switch_attr *attr,
1019 + struct switch_val *val)
1021 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1023 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1029 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1030 + const struct switch_attr *attr,
1031 + struct switch_val *val)
1033 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 + val->value.i = esw->led_frequency;
1040 +static int esw_get_port_link(struct switch_dev *dev,
1042 + struct switch_port_link *link)
1044 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1047 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1050 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1052 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1053 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1054 + if (port < RT305X_ESW_NUM_LEDS) {
1055 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1057 + if (port == RT305X_ESW_NUM_PORTS - 1)
1059 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1063 + link->speed = SWITCH_PORT_SPEED_10;
1066 + link->speed = SWITCH_PORT_SPEED_100;
1069 + case 3: /* forced gige speed can be 2 or 3 */
1070 + link->speed = SWITCH_PORT_SPEED_1000;
1073 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1080 +static int esw_get_port_bool(struct switch_dev *dev,
1081 + const struct switch_attr *attr,
1082 + struct switch_val *val)
1084 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1085 + int idx = val->port_vlan;
1086 + u32 x, reg, shift;
1088 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1091 + switch (attr->id) {
1092 + case RT305X_ESW_ATTR_PORT_DISABLE:
1093 + reg = RT305X_ESW_REG_POC0;
1094 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1096 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1097 + reg = RT305X_ESW_REG_SGC2;
1098 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1100 + case RT305X_ESW_ATTR_PORT_UNTAG:
1101 + reg = RT305X_ESW_REG_POC2;
1102 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1104 + case RT305X_ESW_ATTR_PORT_LAN:
1105 + reg = RT305X_ESW_REG_SGC2;
1106 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1107 + if (idx >= RT305X_ESW_NUM_LANWAN)
1114 + x = esw_r32(esw, reg);
1115 + val->value.i = (x >> (idx + shift)) & 1;
1120 +static int esw_set_port_bool(struct switch_dev *dev,
1121 + const struct switch_attr *attr,
1122 + struct switch_val *val)
1124 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1125 + int idx = val->port_vlan;
1127 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1128 + val->value.i < 0 || val->value.i > 1)
1131 + switch (attr->id) {
1132 + case RT305X_ESW_ATTR_PORT_DISABLE:
1133 + esw->ports[idx].disable = val->value.i;
1135 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1136 + esw->ports[idx].doubletag = val->value.i;
1138 + case RT305X_ESW_ATTR_PORT_UNTAG:
1139 + esw->ports[idx].untag = val->value.i;
1148 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1149 + const struct switch_attr *attr,
1150 + struct switch_val *val)
1152 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1153 + int idx = val->port_vlan;
1154 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1157 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1159 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1160 + val->value.i = (reg >> shift) & 0xffff;
1166 +esw_get_port_tr_badgood(struct switch_dev *dev,
1167 + const struct switch_attr *attr,
1168 + struct switch_val *val)
1170 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1172 + int idx = val->port_vlan;
1173 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1176 + if (!soc_is_rt5350())
1179 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1182 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1183 + val->value.i = (reg >> shift) & 0xffff;
1188 +static int esw_get_port_led(struct switch_dev *dev,
1189 + const struct switch_attr *attr,
1190 + struct switch_val *val)
1192 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1193 + int idx = val->port_vlan;
1195 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1196 + idx >= RT305X_ESW_NUM_LEDS)
1199 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1204 +static int esw_set_port_led(struct switch_dev *dev,
1205 + const struct switch_attr *attr,
1206 + struct switch_val *val)
1208 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1209 + int idx = val->port_vlan;
1211 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1214 + esw->ports[idx].led = val->value.i;
1219 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1221 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1223 + if (port >= RT305X_ESW_NUM_PORTS)
1226 + *val = esw_get_pvid(esw, port);
1231 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1233 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1235 + if (port >= RT305X_ESW_NUM_PORTS)
1238 + esw->ports[port].pvid = val;
1243 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1245 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1247 + int vlan_idx = -1;
1252 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1256 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1257 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1258 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1264 + if (vlan_idx == -1)
1267 + vmsc = esw_get_vmsc(esw, vlan_idx);
1268 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1270 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1271 + struct switch_port *p;
1272 + int port_mask = 1 << i;
1274 + if (!(vmsc & port_mask))
1277 + p = &val->value.ports[val->len++];
1279 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1282 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1288 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1290 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1292 + int vlan_idx = -1;
1295 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1296 + val->len > RT305X_ESW_NUM_PORTS)
1299 + /* one of the already defined vlans? */
1300 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1301 + if (esw->vlans[i].vid == val->port_vlan &&
1302 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1308 + /* select a free slot */
1309 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1310 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1314 + /* bail if all slots are in use */
1315 + if (vlan_idx == -1)
1318 + ports = RT305X_ESW_PORTS_NONE;
1319 + for (i = 0; i < val->len; i++) {
1320 + struct switch_port *p = &val->value.ports[i];
1321 + int port_mask = 1 << p->id;
1322 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1324 + if (p->id >= RT305X_ESW_NUM_PORTS)
1327 + ports |= port_mask;
1328 + esw->ports[p->id].untag = untagged;
1330 + esw->vlans[vlan_idx].ports = ports;
1331 + if (ports == RT305X_ESW_PORTS_NONE)
1332 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1334 + esw->vlans[vlan_idx].vid = val->port_vlan;
1339 +static const struct switch_attr esw_global[] = {
1341 + .type = SWITCH_TYPE_INT,
1342 + .name = "enable_vlan",
1343 + .description = "VLAN mode (1:enabled)",
1345 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1346 + .get = esw_get_vlan_enable,
1347 + .set = esw_set_vlan_enable,
1350 + .type = SWITCH_TYPE_INT,
1351 + .name = "alternate_vlan_disable",
1352 + .description = "Use en_vlan instead of doubletag to disable"
1355 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1356 + .get = esw_get_alt_vlan_disable,
1357 + .set = esw_set_alt_vlan_disable,
1360 + .type = SWITCH_TYPE_INT,
1361 + .name = "bc_storm_protect",
1362 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1364 + .id = RT305X_ESW_ATTR_BC_STATUS,
1365 + .get = rt305x_esw_get_bc_status,
1366 + .set = rt305x_esw_set_bc_status,
1369 + .type = SWITCH_TYPE_INT,
1370 + .name = "led_frequency",
1371 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1373 + .id = RT305X_ESW_ATTR_LED_FREQ,
1374 + .get = rt305x_esw_get_led_freq,
1375 + .set = rt305x_esw_set_led_freq,
1379 +static const struct switch_attr esw_port[] = {
1381 + .type = SWITCH_TYPE_INT,
1382 + .name = "disable",
1383 + .description = "Port state (1:disabled)",
1385 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1386 + .get = esw_get_port_bool,
1387 + .set = esw_set_port_bool,
1390 + .type = SWITCH_TYPE_INT,
1391 + .name = "doubletag",
1392 + .description = "Double tagging for incoming vlan packets "
1395 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1396 + .get = esw_get_port_bool,
1397 + .set = esw_set_port_bool,
1400 + .type = SWITCH_TYPE_INT,
1402 + .description = "Untag (1:strip outgoing vlan tag)",
1404 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1405 + .get = esw_get_port_bool,
1406 + .set = esw_set_port_bool,
1409 + .type = SWITCH_TYPE_INT,
1411 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1412 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1413 + " 8:100mact, 10:blink, 11:off, 12:on)",
1415 + .id = RT305X_ESW_ATTR_PORT_LED,
1416 + .get = esw_get_port_led,
1417 + .set = esw_set_port_led,
1420 + .type = SWITCH_TYPE_INT,
1422 + .description = "HW port group (0:wan, 1:lan)",
1424 + .id = RT305X_ESW_ATTR_PORT_LAN,
1425 + .get = esw_get_port_bool,
1428 + .type = SWITCH_TYPE_INT,
1429 + .name = "recv_bad",
1430 + .description = "Receive bad packet counter",
1431 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1432 + .get = esw_get_port_recv_badgood,
1435 + .type = SWITCH_TYPE_INT,
1436 + .name = "recv_good",
1437 + .description = "Receive good packet counter",
1438 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1439 + .get = esw_get_port_recv_badgood,
1442 + .type = SWITCH_TYPE_INT,
1445 + .description = "Transmit bad packet counter. rt5350 only",
1446 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1447 + .get = esw_get_port_tr_badgood,
1450 + .type = SWITCH_TYPE_INT,
1451 + .name = "tr_good",
1453 + .description = "Transmit good packet counter. rt5350 only",
1454 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1455 + .get = esw_get_port_tr_badgood,
1459 +static const struct switch_attr esw_vlan[] = {
1462 +static const struct switch_dev_ops esw_ops = {
1464 + .attr = esw_global,
1465 + .n_attr = ARRAY_SIZE(esw_global),
1469 + .n_attr = ARRAY_SIZE(esw_port),
1473 + .n_attr = ARRAY_SIZE(esw_vlan),
1475 + .get_vlan_ports = esw_get_vlan_ports,
1476 + .set_vlan_ports = esw_set_vlan_ports,
1477 + .get_port_pvid = esw_get_port_pvid,
1478 + .set_port_pvid = esw_set_port_pvid,
1479 + .get_port_link = esw_get_port_link,
1480 + .apply_config = esw_apply_config,
1481 + .reset_switch = esw_reset_switch,
1484 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1485 + /* All ports are LAN ports. */
1486 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1487 + .reg_initval_fct2 = 0x00d6500c,
1489 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1490 + * turbo mii off, rgmi 3.3v off
1492 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1494 + .reg_initval_fpa2 = 0x3f502b28,
1497 +static const struct of_device_id ralink_esw_match[] = {
1498 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1501 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1503 +static int esw_probe(struct platform_device *pdev)
1505 + struct device_node *np = pdev->dev.of_node;
1506 + const struct rt305x_esw_platform_data *pdata;
1507 + const __be32 *port_map, *reg_init;
1508 + struct rt305x_esw *esw;
1509 + struct switch_dev *swdev;
1510 + struct resource *res, *irq;
1513 + pdata = pdev->dev.platform_data;
1515 + const struct of_device_id *match;
1516 + match = of_match_device(ralink_esw_match, &pdev->dev);
1518 + pdata = (struct rt305x_esw_platform_data *) match->data;
1523 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1525 + dev_err(&pdev->dev, "no memory resource found\n");
1529 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1531 + dev_err(&pdev->dev, "no irq resource found\n");
1535 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1537 + dev_err(&pdev->dev, "no memory for private data\n");
1541 + esw->dev = &pdev->dev;
1542 + esw->irq = irq->start;
1543 + esw->base = ioremap(res->start, resource_size(res));
1545 + dev_err(&pdev->dev, "ioremap failed\n");
1550 + port_map = of_get_property(np, "ralink,portmap", NULL);
1552 + esw->port_map = be32_to_cpu(*port_map);
1554 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1556 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1558 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1560 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1562 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1564 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1566 + swdev = &esw->swdev;
1567 + swdev->of_node = pdev->dev.of_node;
1568 + swdev->name = "rt305x-esw";
1569 + swdev->alias = "rt305x";
1570 + swdev->cpu_port = RT305X_ESW_PORT6;
1571 + swdev->ports = RT305X_ESW_NUM_PORTS;
1572 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1573 + swdev->ops = &esw_ops;
1575 + err = register_switch(swdev, NULL);
1577 + dev_err(&pdev->dev, "register_switch failed\n");
1581 + platform_set_drvdata(pdev, esw);
1583 + esw->pdata = pdata;
1584 + spin_lock_init(&esw->reg_rw_lock);
1588 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1589 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1590 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1595 + iounmap(esw->base);
1601 +static int esw_remove(struct platform_device *pdev)
1603 + struct rt305x_esw *esw;
1605 + esw = platform_get_drvdata(pdev);
1607 + unregister_switch(&esw->swdev);
1608 + platform_set_drvdata(pdev, NULL);
1609 + iounmap(esw->base);
1616 +static struct platform_driver esw_driver = {
1617 + .probe = esw_probe,
1618 + .remove = esw_remove,
1620 + .name = "rt305x-esw",
1621 + .owner = THIS_MODULE,
1622 + .of_match_table = ralink_esw_match,
1626 +int __init rtesw_init(void)
1628 + return platform_driver_register(&esw_driver);
1631 +void rtesw_exit(void)
1633 + platform_driver_unregister(&esw_driver);
1636 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1639 + * This program is free software; you can redistribute it and/or modify
1640 + * it under the terms of the GNU General Public License as published by
1641 + * the Free Software Foundation; version 2 of the License
1643 + * This program is distributed in the hope that it will be useful,
1644 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1645 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1646 + * GNU General Public License for more details.
1648 + * You should have received a copy of the GNU General Public License
1649 + * along with this program; if not, write to the Free Software
1650 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1652 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1655 +#ifndef _RALINK_ESW_RT3052_H__
1656 +#define _RALINK_ESW_RT3052_H__
1658 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1660 +int __init rtesw_init(void);
1661 +void rtesw_exit(void);
1665 +static inline int __init rtesw_init(void) { return 0; }
1666 +static inline void rtesw_exit(void) { }
1671 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1674 + * This program is free software; you can redistribute it and/or modify
1675 + * it under the terms of the GNU General Public License as published by
1676 + * the Free Software Foundation; version 2 of the License
1678 + * This program is distributed in the hope that it will be useful,
1679 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1680 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1681 + * GNU General Public License for more details.
1683 + * You should have received a copy of the GNU General Public License
1684 + * along with this program; if not, write to the Free Software
1685 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1687 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1690 +#include <linux/module.h>
1691 +#include <linux/kernel.h>
1692 +#include <linux/types.h>
1693 +#include <linux/dma-mapping.h>
1694 +#include <linux/init.h>
1695 +#include <linux/skbuff.h>
1696 +#include <linux/etherdevice.h>
1697 +#include <linux/ethtool.h>
1698 +#include <linux/platform_device.h>
1699 +#include <linux/of_device.h>
1700 +#include <linux/clk.h>
1701 +#include <linux/of_net.h>
1702 +#include <linux/of_mdio.h>
1703 +#include <linux/of_irq.h>
1704 +#include <linux/of_address.h>
1705 +#include <linux/switch.h>
1707 +#include <asm/mach-ralink/ralink_regs.h>
1709 +#include "ralink_soc_eth.h"
1711 +#include <linux/ioport.h>
1712 +#include <linux/switch.h>
1713 +#include <linux/mii.h>
1715 +#include <ralink_regs.h>
1716 +#include <asm/mach-ralink/mt7620.h>
1718 +#include "ralink_soc_eth.h"
1719 +#include "gsw_mt7620a.h"
1720 +#include "mt7530.h"
1723 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1725 +#define MT7620A_GSW_REG_PIAC 0x7004
1727 +#define GSW_NUM_VLANS 16
1728 +#define GSW_NUM_VIDS 4096
1729 +#define GSW_NUM_PORTS 7
1730 +#define GSW_PORT6 6
1732 +#define GSW_MDIO_ACCESS BIT(31)
1733 +#define GSW_MDIO_READ BIT(19)
1734 +#define GSW_MDIO_WRITE BIT(18)
1735 +#define GSW_MDIO_START BIT(16)
1736 +#define GSW_MDIO_ADDR_SHIFT 20
1737 +#define GSW_MDIO_REG_SHIFT 25
1739 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1740 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1741 +#define GSW_REG_SMACCR0 0x3fE4
1742 +#define GSW_REG_SMACCR1 0x3fE8
1743 +#define GSW_REG_CKGCR 0x3ff0
1745 +#define GSW_REG_IMR 0x7008
1746 +#define GSW_REG_ISR 0x700c
1748 +#define SYSC_REG_CFG1 0x14
1750 +#define PORT_IRQ_ST_CHG 0x7f
1752 +#define SYSCFG1 0x14
1754 +#define ESW_PHY_POLLING 0x7000
1756 +#define PMCR_IPG BIT(18)
1757 +#define PMCR_MAC_MODE BIT(16)
1758 +#define PMCR_FORCE BIT(15)
1759 +#define PMCR_TX_EN BIT(14)
1760 +#define PMCR_RX_EN BIT(13)
1761 +#define PMCR_BACKOFF BIT(9)
1762 +#define PMCR_BACKPRES BIT(8)
1763 +#define PMCR_RX_FC BIT(5)
1764 +#define PMCR_TX_FC BIT(4)
1765 +#define PMCR_SPEED(_x) (_x << 2)
1766 +#define PMCR_DUPLEX BIT(1)
1767 +#define PMCR_LINK BIT(0)
1769 +#define PHY_AN_EN BIT(31)
1770 +#define PHY_PRE_EN BIT(30)
1771 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1774 + /* Global attributes. */
1775 + GSW_ATTR_ENABLE_VLAN,
1776 + /* Port attributes. */
1777 + GSW_ATTR_PORT_UNTAG,
1785 +struct mt7620_gsw {
1786 + struct device *dev;
1787 + void __iomem *base;
1790 + long unsigned int autopoll;
1793 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1795 + iowrite32(val, gsw->base + reg);
1798 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1800 + return ioread32(gsw->base + reg);
1803 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1805 + unsigned long t_start = jiffies;
1808 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1810 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1815 + printk(KERN_ERR "mdio: MDIO timeout\n");
1819 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1822 + if (mt7620_mii_busy_wait(gsw))
1825 + write_data &= 0xffff;
1827 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1828 + (phy_register << GSW_MDIO_REG_SHIFT) |
1829 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1830 + MT7620A_GSW_REG_PIAC);
1832 + if (mt7620_mii_busy_wait(gsw))
1838 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1842 + if (mt7620_mii_busy_wait(gsw))
1845 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1846 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1847 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1848 + MT7620A_GSW_REG_PIAC);
1850 + if (mt7620_mii_busy_wait(gsw))
1853 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1858 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1860 + struct fe_priv *priv = bus->priv;
1861 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1863 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1866 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1868 + struct fe_priv *priv = bus->priv;
1869 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1871 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1874 +static unsigned char *fe_speed_str(int speed)
1891 +int mt7620a_has_carrier(struct fe_priv *priv)
1893 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1896 + for (i = 0; i < GSW_PORT6; i++)
1897 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1902 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1907 + if (mt7620a_has_carrier(priv))
1908 + netif_carrier_on(priv->netdev);
1910 + netif_carrier_off(priv->netdev);
1913 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1915 + if (priv->link[port])
1916 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1917 + port, fe_speed_str(priv->phy->speed[port]),
1918 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1920 + netdev_info(priv->netdev, "port %d link down\n", port);
1921 + mt7620a_handle_carrier(priv);
1924 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1926 + struct fe_priv *priv = (struct fe_priv *) _priv;
1927 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1929 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1931 + status = gsw_r32(gsw, GSW_REG_ISR);
1932 + if (status & PORT_IRQ_ST_CHG)
1933 + for (i = 0; i <= max; i++) {
1934 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1935 + int link = status & 0x1;
1937 + if (link != priv->link[i]) {
1939 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1940 + i, fe_speed_str((status >> 2) & 3),
1941 + (status & 0x2) ? "Full" : "Half");
1943 + netdev_info(priv->netdev, "port %d link down\n", i);
1946 + priv->link[i] = link;
1948 + mt7620a_handle_carrier(priv);
1950 + gsw_w32(gsw, status, GSW_REG_ISR);
1952 + return IRQ_HANDLED;
1955 +static int mt7620_is_bga(void)
1957 + u32 bga = rt_sysc_r32(0x0c);
1959 + return (bga >> 16) & 1;
1962 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1965 + int lsb = -1, msb = 0;
1967 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1973 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1976 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1978 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1979 + const __be32 *_id = of_get_property(np, "reg", NULL);
1980 + int phy_mode, size, id;
1982 + u32 val, mask = 0;
1983 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1985 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
1987 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
1989 + pr_err("%s: invalid port id\n", np->name);
1993 + id = be32_to_cpu(*_id);
1998 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
1999 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2000 + pr_err("%s: invalid fixed link property\n", np->name);
2001 + priv->phy->phy_fixed[id] = NULL;
2005 + phy_mode = of_get_phy_mode(np);
2006 + switch (phy_mode) {
2007 + case PHY_INTERFACE_MODE_RGMII:
2010 + case PHY_INTERFACE_MODE_MII:
2013 + case PHY_INTERFACE_MODE_RMII:
2017 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2021 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2022 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2025 + val = rt_sysc_r32(SYSCFG1);
2026 + val &= ~(3 << shift);
2027 + val |= mask << shift;
2028 + rt_sysc_w32(val, SYSCFG1);
2030 + if (priv->phy->phy_fixed[id]) {
2031 + const __be32 *link = priv->phy->phy_fixed[id];
2035 + priv->phy->speed[id] = be32_to_cpup(link++);
2036 + tx_fc = be32_to_cpup(link++);
2037 + rx_fc = be32_to_cpup(link++);
2038 + priv->phy->duplex[id] = be32_to_cpup(link++);
2039 + priv->link[id] = 1;
2041 + switch (priv->phy->speed[id]) {
2052 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2053 + priv->phy->phy_fixed[id] = 0;
2056 + val = PMCR_SPEED(val);
2057 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2058 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2060 + val |= PMCR_TX_FC;
2062 + val |= PMCR_RX_FC;
2063 + if (priv->phy->duplex[id])
2064 + val |= PMCR_DUPLEX;
2065 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2066 + dev_info(priv->device, "using fixed link parameters\n");
2070 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2071 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2072 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2074 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2075 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2076 + gsw->autopoll |= BIT(id);
2077 + gsw_auto_poll(gsw);
2082 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2084 + u32 is_BGA = mt7620_is_bga();
2086 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2087 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2089 + /*correct PHY setting L3.0 BGA*/
2090 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2092 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2094 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2096 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2098 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2099 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2100 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2101 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2102 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2103 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2105 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2106 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2108 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2110 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2111 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2112 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2113 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2114 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2115 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2117 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2118 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2119 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2120 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2121 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2122 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2124 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2125 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2127 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2128 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2129 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2130 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2131 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2133 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2134 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2135 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2136 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2137 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2138 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2139 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2140 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2141 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2143 + /* CPU Port6 Force Link 1G, FC ON */
2144 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2145 + /* Set Port6 CPU Port */
2146 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2148 + /* setup port 4 */
2149 + if (gsw->port4 == PORT4_EPHY) {
2150 + u32 val = rt_sysc_r32(SYSCFG1);
2152 + rt_sysc_w32(val, SYSCFG1);
2153 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2154 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2155 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2156 + pr_info("gsw: setting port4 to ephy mode\n");
2160 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2162 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2163 + unsigned long flags;
2165 + spin_lock_irqsave(&priv->page_lock, flags);
2166 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2167 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2169 + spin_unlock_irqrestore(&priv->page_lock, flags);
2172 +static struct of_device_id gsw_match[] = {
2173 + { .compatible = "ralink,mt7620a-gsw" },
2177 +int mt7620_gsw_config(struct fe_priv *priv)
2179 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2181 + /* is the mt7530 internal or external */
2182 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2183 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2185 + mt7530_probe(priv->device, gsw->base, NULL);
2190 +int mt7620_gsw_probe(struct fe_priv *priv)
2192 + struct mt7620_gsw *gsw;
2193 + struct device_node *np;
2194 + const char *port4 = NULL;
2196 + np = of_find_matching_node(NULL, gsw_match);
2198 + dev_err(priv->device, "no gsw node found\n");
2201 + np = of_node_get(np);
2203 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2205 + dev_err(priv->device, "no gsw memory for private data\n");
2209 + gsw->irq = irq_of_parse_and_map(np, 0);
2211 + dev_err(priv->device, "no gsw irq resource found\n");
2215 + gsw->base = of_iomap(np, 0);
2217 + dev_err(priv->device, "gsw ioremap failed\n");
2221 + gsw->dev = priv->device;
2222 + priv->soc->swpriv = gsw;
2224 + of_property_read_string(np, "ralink,port4", &port4);
2225 + if (port4 && !strcmp(port4, "ephy"))
2226 + gsw->port4 = PORT4_EPHY;
2227 + else if (port4 && !strcmp(port4, "gmac"))
2228 + gsw->port4 = PORT4_EXT;
2234 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2235 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2240 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2243 + * This program is free software; you can redistribute it and/or modify
2244 + * it under the terms of the GNU General Public License as published by
2245 + * the Free Software Foundation; version 2 of the License
2247 + * This program is distributed in the hope that it will be useful,
2248 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2249 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2250 + * GNU General Public License for more details.
2252 + * You should have received a copy of the GNU General Public License
2253 + * along with this program; if not, write to the Free Software
2254 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2256 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2259 +#ifndef _RALINK_GSW_MT7620_H__
2260 +#define _RALINK_GSW_MT7620_H__
2262 +extern int mt7620_gsw_config(struct fe_priv *priv);
2263 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2264 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2265 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2266 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2267 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2268 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2269 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2273 +++ b/drivers/net/ethernet/ralink/mdio.c
2276 + * This program is free software; you can redistribute it and/or modify
2277 + * it under the terms of the GNU General Public License as published by
2278 + * the Free Software Foundation; version 2 of the License
2280 + * This program is distributed in the hope that it will be useful,
2281 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2282 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2283 + * GNU General Public License for more details.
2285 + * You should have received a copy of the GNU General Public License
2286 + * along with this program; if not, write to the Free Software
2287 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2289 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2292 +#include <linux/module.h>
2293 +#include <linux/kernel.h>
2294 +#include <linux/types.h>
2295 +#include <linux/dma-mapping.h>
2296 +#include <linux/init.h>
2297 +#include <linux/skbuff.h>
2298 +#include <linux/etherdevice.h>
2299 +#include <linux/ethtool.h>
2300 +#include <linux/platform_device.h>
2301 +#include <linux/phy.h>
2302 +#include <linux/of_device.h>
2303 +#include <linux/clk.h>
2304 +#include <linux/of_net.h>
2305 +#include <linux/of_mdio.h>
2307 +#include "ralink_soc_eth.h"
2310 +static int fe_mdio_reset(struct mii_bus *bus)
2316 +static void fe_phy_link_adjust(struct net_device *dev)
2318 + struct fe_priv *priv = netdev_priv(dev);
2319 + unsigned long flags;
2322 + spin_lock_irqsave(&priv->phy->lock, flags);
2323 + for (i = 0; i < 8; i++) {
2324 + if (priv->phy->phy_node[i]) {
2325 + struct phy_device *phydev = priv->phy->phy[i];
2326 + int status_change = 0;
2329 + if (priv->phy->duplex[i] != phydev->duplex ||
2330 + priv->phy->speed[i] != phydev->speed)
2331 + status_change = 1;
2333 + if (phydev->link != priv->link[i])
2334 + status_change = 1;
2336 + switch (phydev->speed) {
2340 + priv->link[i] = phydev->link;
2341 + priv->phy->duplex[i] = phydev->duplex;
2342 + priv->phy->speed[i] = phydev->speed;
2344 + if (status_change && priv->soc->mdio_adjust_link)
2345 + priv->soc->mdio_adjust_link(priv, i);
2352 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2354 + const __be32 *_port = NULL;
2355 + struct phy_device *phydev;
2356 + int phy_mode, port;
2358 + _port = of_get_property(phy_node, "reg", NULL);
2360 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2361 + pr_err("%s: invalid port id\n", phy_node->name);
2364 + port = be32_to_cpu(*_port);
2365 + phy_mode = of_get_phy_mode(phy_node);
2366 + if (phy_mode < 0) {
2367 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2368 + priv->phy->phy_node[port] = NULL;
2372 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2374 + if (IS_ERR(phydev)) {
2375 + dev_err(priv->device, "could not connect to PHY\n");
2376 + priv->phy->phy_node[port] = NULL;
2377 + return PTR_ERR(phydev);
2380 + phydev->supported &= PHY_GBIT_FEATURES;
2381 + phydev->advertising = phydev->supported;
2382 + phydev->no_auto_carrier_off = 1;
2384 + dev_info(priv->device,
2385 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2386 + port, dev_name(&phydev->dev), phydev->phy_id,
2387 + phydev->drv->name);
2389 + priv->phy->phy[port] = phydev;
2390 + priv->link[port] = 0;
2395 +static int fe_phy_connect(struct fe_priv *priv)
2400 +static void fe_phy_disconnect(struct fe_priv *priv)
2402 + unsigned long flags;
2405 + for (i = 0; i < 8; i++)
2406 + if (priv->phy->phy_fixed[i]) {
2407 + spin_lock_irqsave(&priv->phy->lock, flags);
2408 + priv->link[i] = 0;
2409 + if (priv->soc->mdio_adjust_link)
2410 + priv->soc->mdio_adjust_link(priv, i);
2411 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2412 + } else if (priv->phy->phy[i]) {
2413 + phy_disconnect(priv->phy->phy[i]);
2417 +static void fe_phy_start(struct fe_priv *priv)
2419 + unsigned long flags;
2422 + for (i = 0; i < 8; i++) {
2423 + if (priv->phy->phy_fixed[i]) {
2424 + spin_lock_irqsave(&priv->phy->lock, flags);
2425 + priv->link[i] = 1;
2426 + if (priv->soc->mdio_adjust_link)
2427 + priv->soc->mdio_adjust_link(priv, i);
2428 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2429 + } else if (priv->phy->phy[i]) {
2430 + phy_start(priv->phy->phy[i]);
2435 +static void fe_phy_stop(struct fe_priv *priv)
2437 + unsigned long flags;
2440 + for (i = 0; i < 8; i++)
2441 + if (priv->phy->phy_fixed[i]) {
2442 + spin_lock_irqsave(&priv->phy->lock, flags);
2443 + priv->link[i] = 0;
2444 + if (priv->soc->mdio_adjust_link)
2445 + priv->soc->mdio_adjust_link(priv, i);
2446 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2447 + } else if (priv->phy->phy[i]) {
2448 + phy_stop(priv->phy->phy[i]);
2452 +static struct fe_phy phy_ralink = {
2453 + .connect = fe_phy_connect,
2454 + .disconnect = fe_phy_disconnect,
2455 + .start = fe_phy_start,
2456 + .stop = fe_phy_stop,
2459 +int fe_mdio_init(struct fe_priv *priv)
2461 + struct device_node *mii_np;
2464 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2467 + spin_lock_init(&phy_ralink.lock);
2468 + priv->phy = &phy_ralink;
2470 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2472 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2476 + if (!of_device_is_available(mii_np)) {
2478 + goto err_put_node;
2481 + priv->mii_bus = mdiobus_alloc();
2482 + if (priv->mii_bus == NULL) {
2484 + goto err_put_node;
2487 + priv->mii_bus->name = "mdio";
2488 + priv->mii_bus->read = priv->soc->mdio_read;
2489 + priv->mii_bus->write = priv->soc->mdio_write;
2490 + priv->mii_bus->reset = fe_mdio_reset;
2491 + priv->mii_bus->irq = priv->mii_irq;
2492 + priv->mii_bus->priv = priv;
2493 + priv->mii_bus->parent = priv->device;
2495 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2496 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2498 + goto err_free_bus;
2503 + kfree(priv->mii_bus);
2505 + of_node_put(mii_np);
2506 + priv->mii_bus = NULL;
2510 +void fe_mdio_cleanup(struct fe_priv *priv)
2512 + if (!priv->mii_bus)
2515 + mdiobus_unregister(priv->mii_bus);
2516 + of_node_put(priv->mii_bus->dev.of_node);
2517 + kfree(priv->mii_bus);
2520 +++ b/drivers/net/ethernet/ralink/mdio.h
2523 + * This program is free software; you can redistribute it and/or modify
2524 + * it under the terms of the GNU General Public License as published by
2525 + * the Free Software Foundation; version 2 of the License
2527 + * This program is distributed in the hope that it will be useful,
2528 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2529 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2530 + * GNU General Public License for more details.
2532 + * You should have received a copy of the GNU General Public License
2533 + * along with this program; if not, write to the Free Software
2534 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2536 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2539 +#ifndef _RALINK_MDIO_H__
2540 +#define _RALINK_MDIO_H__
2542 +#ifdef CONFIG_NET_RALINK_MDIO
2543 +extern int fe_mdio_init(struct fe_priv *priv);
2544 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2545 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2547 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2548 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2552 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
2555 + * This program is free software; you can redistribute it and/or modify
2556 + * it under the terms of the GNU General Public License as published by
2557 + * the Free Software Foundation; version 2 of the License
2559 + * This program is distributed in the hope that it will be useful,
2560 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2561 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2562 + * GNU General Public License for more details.
2564 + * You should have received a copy of the GNU General Public License
2565 + * along with this program; if not, write to the Free Software
2566 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2568 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2571 +#include <linux/module.h>
2572 +#include <linux/kernel.h>
2573 +#include <linux/types.h>
2574 +#include <linux/dma-mapping.h>
2575 +#include <linux/init.h>
2576 +#include <linux/skbuff.h>
2577 +#include <linux/etherdevice.h>
2578 +#include <linux/ethtool.h>
2579 +#include <linux/platform_device.h>
2580 +#include <linux/phy.h>
2581 +#include <linux/of_device.h>
2582 +#include <linux/clk.h>
2583 +#include <linux/of_net.h>
2584 +#include <linux/of_mdio.h>
2586 +#include "ralink_soc_eth.h"
2587 +#include "mdio_rt2880.h"
2590 +#define FE_MDIO_RETRY 1000
2592 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2594 + switch (priv->phy->speed[0]) {
2606 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2610 + if (!priv->link[0]) {
2611 + netif_carrier_off(priv->netdev);
2612 + netdev_info(priv->netdev, "link down\n");
2616 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2617 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2618 + FE_MDIO_CFG_GP1_FRC_EN;
2620 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2621 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2623 + if (priv->phy->tx_fc[0])
2624 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2626 + if (priv->phy->rx_fc[0])
2627 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2629 + switch (priv->phy->speed[0]) {
2631 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2634 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2637 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2643 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2645 + netif_carrier_on(priv->netdev);
2646 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2647 + rt2880_speed_str(priv),
2648 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2651 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2655 + retries = FE_MDIO_RETRY;
2659 + t = fe_r32(FE_MDIO_ACCESS);
2660 + if ((t & (0x1 << 31)) == 0)
2663 + if (retries-- == 0)
2669 + dev_err(priv->device, "MDIO operation timed out\n");
2670 + return -ETIMEDOUT;
2673 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2675 + struct fe_priv *priv = bus->priv;
2679 + err = rt2880_mdio_wait_ready(priv);
2683 + t = (phy_addr << 24) | (phy_reg << 16);
2684 + fe_w32(t, FE_MDIO_ACCESS);
2686 + fe_w32(t, FE_MDIO_ACCESS);
2688 + err = rt2880_mdio_wait_ready(priv);
2692 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2693 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2695 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2698 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2700 + struct fe_priv *priv = bus->priv;
2704 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2705 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2707 + err = rt2880_mdio_wait_ready(priv);
2711 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2712 + fe_w32(t, FE_MDIO_ACCESS);
2714 + fe_w32(t, FE_MDIO_ACCESS);
2716 + return rt2880_mdio_wait_ready(priv);
2719 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2721 + const __be32 *id = of_get_property(np, "reg", NULL);
2722 + const __be32 *link;
2726 + if (!id || (be32_to_cpu(*id) != 0)) {
2727 + pr_err("%s: invalid port id\n", np->name);
2731 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2732 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2733 + pr_err("%s: invalid fixed link property\n", np->name);
2734 + priv->phy->phy_fixed[0] = NULL;
2738 + phy_mode = of_get_phy_mode(np);
2739 + switch (phy_mode) {
2740 + case PHY_INTERFACE_MODE_RGMII:
2742 + case PHY_INTERFACE_MODE_MII:
2744 + case PHY_INTERFACE_MODE_RMII:
2747 + if (!priv->phy->phy_fixed[0])
2748 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2752 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2753 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2756 + if (priv->phy->phy_fixed[0]) {
2757 + link = priv->phy->phy_fixed[0];
2758 + priv->phy->speed[0] = be32_to_cpup(link++);
2759 + priv->phy->duplex[0] = be32_to_cpup(link++);
2760 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2761 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2763 + priv->link[0] = 1;
2764 + switch (priv->phy->speed[0]) {
2772 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2773 + priv->phy->phy_fixed[0] = 0;
2776 + dev_info(priv->device, "using fixed link parameters\n");
2777 + rt2880_mdio_link_adjust(priv, 0);
2780 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2781 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2787 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
2790 + * This program is free software; you can redistribute it and/or modify
2791 + * it under the terms of the GNU General Public License as published by
2792 + * the Free Software Foundation; version 2 of the License
2794 + * This program is distributed in the hope that it will be useful,
2795 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2796 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2797 + * GNU General Public License for more details.
2799 + * You should have received a copy of the GNU General Public License
2800 + * along with this program; if not, write to the Free Software
2801 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2803 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2806 +#ifndef _RALINK_MDIO_RT2880_H__
2807 +#define _RALINK_MDIO_RT2880_H__
2809 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2810 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2811 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2812 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2816 +++ b/drivers/net/ethernet/ralink/mt7530.c
2819 + * This program is free software; you can redistribute it and/or
2820 + * modify it under the terms of the GNU General Public License
2821 + * as published by the Free Software Foundation; either version 2
2822 + * of the License, or (at your option) any later version.
2824 + * This program is distributed in the hope that it will be useful,
2825 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2826 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2827 + * GNU General Public License for more details.
2829 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2832 +#include <linux/if.h>
2833 +#include <linux/module.h>
2834 +#include <linux/init.h>
2835 +#include <linux/list.h>
2836 +#include <linux/if_ether.h>
2837 +#include <linux/skbuff.h>
2838 +#include <linux/netdevice.h>
2839 +#include <linux/netlink.h>
2840 +#include <linux/bitops.h>
2841 +#include <net/genetlink.h>
2842 +#include <linux/switch.h>
2843 +#include <linux/delay.h>
2844 +#include <linux/phy.h>
2845 +#include <linux/netdevice.h>
2846 +#include <linux/etherdevice.h>
2847 +#include <linux/lockdep.h>
2848 +#include <linux/workqueue.h>
2849 +#include <linux/of_device.h>
2851 +#include "mt7530.h"
2853 +#define MT7530_CPU_PORT 6
2854 +#define MT7530_NUM_PORTS 8
2855 +#define MT7530_NUM_VLANS 16
2856 +#define MT7530_MAX_VID 4095
2857 +#define MT7530_MIN_VID 0
2860 +#define REG_ESW_VLAN_VTCR 0x90
2861 +#define REG_ESW_VLAN_VAWD1 0x94
2862 +#define REG_ESW_VLAN_VAWD2 0x98
2863 +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
2865 +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
2866 +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
2867 +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
2869 +/* vlan egress mode */
2871 + ETAG_CTRL_UNTAG = 0,
2872 + ETAG_CTRL_TAG = 2,
2873 + ETAG_CTRL_SWAP = 1,
2874 + ETAG_CTRL_STACK = 3,
2877 +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
2878 +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
2879 +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
2881 + /* Global attributes. */
2882 + MT7530_ATTR_ENABLE_VLAN,
2885 +struct mt7530_port_entry {
2889 +struct mt7530_vlan_entry {
2895 +struct mt7530_priv {
2896 + void __iomem *base;
2897 + struct mii_bus *bus;
2898 + struct switch_dev swdev;
2900 + bool global_vlan_enable;
2901 + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
2902 + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
2905 +struct mt7530_mapping {
2907 + u16 pvids[MT7530_NUM_PORTS];
2908 + u8 members[MT7530_NUM_VLANS];
2909 + u8 etags[MT7530_NUM_VLANS];
2910 + u16 vids[MT7530_NUM_VLANS];
2911 +} mt7530_defaults[] = {
2914 + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2915 + .members = { 0, 0x6f, 0x50 },
2916 + .etags = { 0, 0x40, 0x40 },
2917 + .vids = { 0, 1, 2 },
2920 + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2921 + .members = { 0, 0x7e, 0x41 },
2922 + .etags = { 0, 0x40, 0x40 },
2923 + .vids = { 0, 1, 2 },
2927 +struct mt7530_mapping*
2928 +mt7530_find_mapping(struct device_node *np)
2933 + if (of_property_read_string(np, "ralink,port-map", &map))
2936 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
2937 + if (!strcmp(map, mt7530_defaults[i].name))
2938 + return &mt7530_defaults[i];
2944 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
2948 + mt7530->global_vlan_enable = 1;
2950 + for (i = 0; i < MT7530_NUM_PORTS; i++)
2951 + mt7530->port_entries[i].pvid = map->pvids[i];
2953 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
2954 + mt7530->vlan_entries[i].member = map->members[i];
2955 + mt7530->vlan_entries[i].etags = map->etags[i];
2956 + mt7530->vlan_entries[i].vid = map->vids[i];
2961 +mt7530_reset_switch(struct switch_dev *dev)
2963 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2966 + memset(priv->port_entries, 0, sizeof(priv->port_entries));
2967 + memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
2969 + /* set default vid of each vlan to the same number of vlan, so the vid
2970 + * won't need be set explicitly.
2972 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
2973 + priv->vlan_entries[i].vid = i;
2980 +mt7530_get_vlan_enable(struct switch_dev *dev,
2981 + const struct switch_attr *attr,
2982 + struct switch_val *val)
2984 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2986 + val->value.i = priv->global_vlan_enable;
2992 +mt7530_set_vlan_enable(struct switch_dev *dev,
2993 + const struct switch_attr *attr,
2994 + struct switch_val *val)
2996 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
2998 + priv->global_vlan_enable = val->value.i != 0;
3004 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3010 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3011 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3012 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
3014 + return (high << 16) | (low & 0xffff);
3017 + val = ioread32(priv->base + reg);
3018 + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3024 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3027 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3028 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
3029 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3033 + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3034 + iowrite32(val, priv->base + reg);
3038 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3042 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3044 + for (i = 0; i < 20; i++) {
3045 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3047 + if ((val & BIT(31)) == 0)
3053 + printk("mt7530: vtcr timeout\n");
3057 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3059 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3061 + if (port >= MT7530_NUM_PORTS)
3064 + *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3071 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3073 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3075 + if (port >= MT7530_NUM_PORTS)
3078 + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3081 + priv->port_entries[port].pvid = pvid;
3087 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3089 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3096 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3099 + mt7530_vtcr(priv, 0, val->port_vlan);
3101 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3105 + etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3107 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3108 + struct switch_port *p;
3111 + if (!(member & BIT(i)))
3114 + p = &val->value.ports[val->len++];
3117 + etag = (etags >> (i * 2)) & 0x3;
3119 + if (etag == ETAG_CTRL_TAG)
3120 + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3121 + else if (etag != ETAG_CTRL_UNTAG)
3122 + printk("vlan egress tag control neither untag nor tag.\n");
3129 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3131 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3136 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3137 + val->len > MT7530_NUM_PORTS)
3140 + for (i = 0; i < val->len; i++) {
3141 + struct switch_port *p = &val->value.ports[i];
3143 + if (p->id >= MT7530_NUM_PORTS)
3146 + member |= BIT(p->id);
3148 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3149 + etags |= BIT(p->id);
3151 + priv->vlan_entries[val->port_vlan].member = member;
3152 + priv->vlan_entries[val->port_vlan].etags = etags;
3158 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3159 + struct switch_val *val)
3161 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3165 + vlan = val->port_vlan;
3166 + vid = (u16)val->value.i;
3168 + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3171 + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3174 + priv->vlan_entries[vlan].vid = vid;
3179 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3180 + struct switch_val *val)
3182 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3186 + vlan = val->port_vlan;
3188 + vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3193 + val->value.i = vid;
3198 +mt7530_apply_config(struct switch_dev *dev)
3200 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3203 + if (!priv->global_vlan_enable) {
3204 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3205 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3207 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3208 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x8100000c);
3213 + /* set all ports as security mode */
3214 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3215 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3217 + /* set all ports as user port */
3218 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3219 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3221 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3222 + u16 vid = priv->vlan_entries[i].vid;
3223 + u8 member = priv->vlan_entries[i].member;
3224 + u8 etags = priv->vlan_entries[i].etags;
3228 + val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3234 + val |= (vid << 12);
3236 + mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3238 + /* vlan port membership */
3240 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3241 + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3242 + REG_ESW_VLAN_VAWD1_VALID);
3244 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3248 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
3249 + if (etags & BIT(j))
3250 + val |= ETAG_CTRL_TAG << (j * 2);
3252 + val |= ETAG_CTRL_UNTAG << (j * 2);
3254 + mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3256 + /* write to vlan table */
3257 + mt7530_vtcr(priv, 1, i);
3260 + /* Port Default PVID */
3261 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3263 + val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3265 + val |= priv->port_entries[i].pvid;
3266 + mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3273 +mt7530_get_port_link(struct switch_dev *dev, int port,
3274 + struct switch_port_link *link)
3276 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3279 + if (port < 0 || port >= MT7530_NUM_PORTS)
3282 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3284 + link->link = pmsr & 1;
3285 + link->duplex = (pmsr >> 1) & 1;
3286 + speed = (pmsr >> 2) & 3;
3290 + link->speed = SWITCH_PORT_SPEED_10;
3293 + link->speed = SWITCH_PORT_SPEED_100;
3296 + case 3: /* forced gige speed can be 2 or 3 */
3297 + link->speed = SWITCH_PORT_SPEED_1000;
3300 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3307 +static const struct switch_attr mt7530_global[] = {
3309 + .type = SWITCH_TYPE_INT,
3310 + .name = "enable_vlan",
3311 + .description = "VLAN mode (1:enabled)",
3313 + .id = MT7530_ATTR_ENABLE_VLAN,
3314 + .get = mt7530_get_vlan_enable,
3315 + .set = mt7530_set_vlan_enable,
3319 +static const struct switch_attr mt7530_port[] = {
3322 +static const struct switch_attr mt7530_vlan[] = {
3324 + .type = SWITCH_TYPE_INT,
3326 + .description = "VLAN ID (0-4094)",
3327 + .set = mt7530_set_vid,
3328 + .get = mt7530_get_vid,
3333 +static const struct switch_dev_ops mt7530_ops = {
3335 + .attr = mt7530_global,
3336 + .n_attr = ARRAY_SIZE(mt7530_global),
3339 + .attr = mt7530_port,
3340 + .n_attr = ARRAY_SIZE(mt7530_port),
3343 + .attr = mt7530_vlan,
3344 + .n_attr = ARRAY_SIZE(mt7530_vlan),
3346 + .get_vlan_ports = mt7530_get_vlan_ports,
3347 + .set_vlan_ports = mt7530_set_vlan_ports,
3348 + .get_port_pvid = mt7530_get_port_pvid,
3349 + .set_port_pvid = mt7530_set_port_pvid,
3350 + .get_port_link = mt7530_get_port_link,
3351 + .apply_config = mt7530_apply_config,
3352 + .reset_switch = mt7530_reset_switch,
3356 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
3358 + struct switch_dev *swdev;
3359 + struct mt7530_priv *mt7530;
3360 + struct mt7530_mapping *map;
3363 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
3366 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3370 + mt7530->base = base;
3371 + mt7530->bus = bus;
3372 + mt7530->global_vlan_enable = 1;
3374 + swdev = &mt7530->swdev;
3375 + swdev->name = "mt7530";
3376 + swdev->alias = "mt7530";
3377 + swdev->cpu_port = MT7530_CPU_PORT;
3378 + swdev->ports = MT7530_NUM_PORTS;
3379 + swdev->vlans = MT7530_NUM_VLANS;
3380 + swdev->ops = &mt7530_ops;
3382 + ret = register_switch(swdev, NULL);
3384 + dev_err(dev, "failed to register mt7530\n");
3388 + dev_info(dev, "loaded mt7530 driver\n");
3390 + map = mt7530_find_mapping(dev->of_node);
3392 + mt7530_apply_mapping(mt7530, map);
3393 + mt7530_apply_config(swdev);
3398 +++ b/drivers/net/ethernet/ralink/mt7530.h
3401 + * This program is free software; you can redistribute it and/or
3402 + * modify it under the terms of the GNU General Public License
3403 + * as published by the Free Software Foundation; either version 2
3404 + * of the License, or (at your option) any later version.
3406 + * This program is distributed in the hope that it will be useful,
3407 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3408 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3409 + * GNU General Public License for more details.
3411 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3414 +#ifndef _MT7530_H__
3415 +#define _MT7530_H__
3417 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);
3421 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
3424 + * This program is free software; you can redistribute it and/or modify
3425 + * it under the terms of the GNU General Public License as published by
3426 + * the Free Software Foundation; version 2 of the License
3428 + * This program is distributed in the hope that it will be useful,
3429 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3430 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3431 + * GNU General Public License for more details.
3433 + * You should have received a copy of the GNU General Public License
3434 + * along with this program; if not, write to the Free Software
3435 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3437 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3440 +#include <linux/module.h>
3441 +#include <linux/kernel.h>
3442 +#include <linux/types.h>
3443 +#include <linux/dma-mapping.h>
3444 +#include <linux/init.h>
3445 +#include <linux/skbuff.h>
3446 +#include <linux/etherdevice.h>
3447 +#include <linux/ethtool.h>
3448 +#include <linux/platform_device.h>
3449 +#include <linux/of_device.h>
3450 +#include <linux/clk.h>
3451 +#include <linux/of_net.h>
3452 +#include <linux/of_mdio.h>
3453 +#include <linux/if_vlan.h>
3454 +#include <linux/reset.h>
3456 +#include <asm/mach-ralink/ralink_regs.h>
3458 +#include "ralink_soc_eth.h"
3459 +#include "esw_rt3052.h"
3462 +#define TX_TIMEOUT (2 * HZ)
3463 +#define MAX_RX_LENGTH 1536
3464 +#define DMA_DUMMY_DESC 0xffffffff
3466 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3467 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3468 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3469 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3470 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3471 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3472 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3473 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3474 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3475 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3476 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3477 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3480 +static const u32 *fe_reg_table = fe_reg_table_default;
3482 +static void __iomem *fe_base = 0;
3484 +void fe_w32(u32 val, unsigned reg)
3486 + __raw_writel(val, fe_base + reg);
3489 +u32 fe_r32(unsigned reg)
3491 + return __raw_readl(fe_base + reg);
3494 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
3496 + fe_w32(val, fe_reg_table[reg]);
3499 +static inline u32 fe_reg_r32(enum fe_reg reg)
3501 + return fe_r32(fe_reg_table[reg]);
3504 +static inline void fe_int_disable(u32 mask)
3506 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3507 + FE_REG_FE_INT_ENABLE);
3509 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3512 +static inline void fe_int_enable(u32 mask)
3514 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3515 + FE_REG_FE_INT_ENABLE);
3517 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3520 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3522 + unsigned long flags;
3524 + spin_lock_irqsave(&priv->page_lock, flags);
3525 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3526 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3527 + FE_GDMA1_MAC_ADRL);
3528 + spin_unlock_irqrestore(&priv->page_lock, flags);
3531 +static int fe_set_mac_address(struct net_device *dev, void *p)
3533 + int ret = eth_mac_addr(dev, p);
3536 + struct fe_priv *priv = netdev_priv(dev);
3538 + if (priv->soc->set_mac)
3539 + priv->soc->set_mac(priv, dev->dev_addr);
3541 + fe_hw_set_macaddr(priv, p);
3547 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
3549 + struct sk_buff *skb;
3551 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
3555 + skb_reserve(skb, NET_IP_ALIGN);
3560 +static int fe_alloc_rx(struct fe_priv *priv)
3562 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3565 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3566 + &priv->rx_phys, GFP_ATOMIC);
3567 + if (!priv->rx_dma)
3570 + memset(priv->rx_dma, 0, size);
3572 + for (i = 0; i < NUM_DMA_DESC; i++) {
3573 + priv->rx_skb[i] = fe_alloc_skb(priv);
3574 + if (!priv->rx_skb[i])
3578 + for (i = 0; i < NUM_DMA_DESC; i++) {
3579 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3580 + priv->rx_skb[i]->data,
3583 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3585 + if (priv->soc->rx_dma)
3586 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3588 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3592 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3593 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3594 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3595 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3600 +static int fe_alloc_tx(struct fe_priv *priv)
3602 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3605 + priv->tx_free_idx = 0;
3607 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3608 + &priv->tx_phys, GFP_ATOMIC);
3609 + if (!priv->tx_dma)
3612 + memset(priv->tx_dma, 0, size);
3614 + for (i = 0; i < NUM_DMA_DESC; i++) {
3615 + if (priv->soc->tx_dma) {
3616 + priv->soc->tx_dma(priv, i, NULL);
3620 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3621 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3624 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3625 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3626 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3627 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3632 +static void fe_free_dma(struct fe_priv *priv)
3636 + for (i = 0; i < NUM_DMA_DESC; i++) {
3637 + if (priv->rx_skb[i]) {
3638 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3639 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3640 + dev_kfree_skb_any(priv->rx_skb[i]);
3641 + priv->rx_skb[i] = NULL;
3644 + if (priv->tx_skb[i]) {
3645 + dev_kfree_skb_any(priv->tx_skb[i]);
3646 + priv->tx_skb[i] = NULL;
3650 + if (priv->rx_dma) {
3651 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3652 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3656 + if (priv->tx_dma) {
3657 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3658 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3662 + netdev_reset_queue(priv->netdev);
3665 +static void fe_start_tso(struct sk_buff *skb, struct net_device *dev, unsigned int nr_frags, int idx)
3667 + struct fe_priv *priv = netdev_priv(dev);
3668 + struct skb_frag_struct *frag;
3671 + for (i = 0; i < nr_frags; i++) {
3672 + dma_addr_t mapped_addr;
3674 + frag = &skb_shinfo(skb)->frags[i];
3675 + mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE);
3677 + idx = (idx + 1) % NUM_DMA_DESC;
3678 + priv->tx_dma[idx].txd1 = mapped_addr;
3679 + if (i == nr_frags - 1)
3680 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(frag->size);
3682 + priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(frag->size);
3684 + priv->tx_dma[idx].txd3 = mapped_addr;
3685 + if (i == nr_frags - 1)
3686 + priv->tx_dma[idx].txd2 |= TX_DMA_LS1 | TX_DMA_PLEN1(frag->size);
3688 + priv->tx_dma[idx].txd2 |= TX_DMA_PLEN1(frag->size);
3693 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3695 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3696 + struct fe_priv *priv = netdev_priv(dev);
3697 + dma_addr_t mapped_addr;
3698 + u32 tx_next, tx, tx_num = 1;
3701 + if (priv->soc->min_pkt_len) {
3702 + if (skb->len < priv->soc->min_pkt_len) {
3703 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3705 + "fe_eth: skb_padto failed\n");
3709 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3713 + dev->trans_start = jiffies;
3714 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3715 + skb->len, DMA_TO_DEVICE);
3717 + spin_lock(&priv->page_lock);
3719 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3720 + if (priv->soc->tso && nr_frags)
3721 + tx_num += nr_frags >> 1;
3722 + tx_next = (tx + tx_num) % NUM_DMA_DESC;
3723 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3724 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3725 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3727 + spin_unlock(&priv->page_lock);
3728 + dev->stats.tx_dropped++;
3731 + return NETDEV_TX_OK;
3734 + if (priv->soc->tso) {
3737 + priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = skb;
3739 + priv->tx_skb[(tx + t - 1) % NUM_DMA_DESC] = (struct sk_buff *) DMA_DUMMY_DESC;
3741 + priv->tx_skb[tx] = skb;
3743 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3746 + priv->tx_dma[tx].txd4 &= ~0x80;
3747 + if (priv->soc->tx_dma)
3748 + priv->soc->tx_dma(priv, tx, skb);
3750 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3752 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3753 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3755 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3757 + if (priv->soc->tso)
3758 + fe_start_tso(skb, dev, nr_frags, tx);
3760 + if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
3761 + struct iphdr *iph = NULL;
3762 + struct tcphdr *th = NULL;
3763 + struct ipv6hdr *ip6h = NULL;
3765 + ip6h = (struct ipv6hdr *) skb_network_header(skb);
3766 + iph = (struct iphdr *) skb_network_header(skb);
3767 + if ((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
3768 + th = (struct tcphdr *)skb_transport_header(skb);
3769 + priv->tx_dma[tx].txd4 |= BIT(28);
3770 + th->check = htons(skb_shinfo(skb)->gso_size);
3771 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3772 + } else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
3773 + th = (struct tcphdr *)skb_transport_header(skb);
3774 + priv->tx_dma[tx].txd4 |= BIT(28);
3775 + th->check = htons(skb_shinfo(skb)->gso_size);
3776 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
3780 + for (i = 0; i < tx_num; i++)
3781 + dma_cache_sync(NULL, &priv->tx_dma[tx + i], sizeof(struct fe_tx_dma), DMA_TO_DEVICE);
3783 + dev->stats.tx_packets++;
3784 + dev->stats.tx_bytes += skb->len;
3787 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3788 + netdev_sent_queue(dev, skb->len);
3790 + spin_unlock(&priv->page_lock);
3792 + return NETDEV_TX_OK;
3795 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3797 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3798 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3802 + while ((rx < budget) && !complete) {
3803 + idx = (idx + 1) % NUM_DMA_DESC;
3805 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3806 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3809 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3810 + dma_addr_t dma_addr;
3812 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3813 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3815 + skb_put(priv->rx_skb[idx], pktlen);
3816 + priv->rx_skb[idx]->dev = priv->netdev;
3817 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3818 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3819 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3821 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3822 + priv->netdev->stats.rx_packets++;
3823 + priv->netdev->stats.rx_bytes += pktlen;
3825 +#ifdef CONFIG_INET_LRO
3826 + if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3827 + lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3830 + netif_receive_skb(priv->rx_skb[idx]);
3832 + priv->rx_skb[idx] = new_skb;
3834 + dma_addr = dma_map_single(&priv->netdev->dev,
3838 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3841 + priv->netdev->stats.rx_dropped++;
3844 + if (priv->soc->rx_dma)
3845 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3847 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3848 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3856 +#ifdef CONFIG_INET_LRO
3857 + if (priv->soc->get_skb_header)
3858 + lro_flush_all(&priv->lro_mgr);
3861 + napi_complete(&priv->rx_napi);
3862 + fe_int_enable(priv->soc->rx_dly_int);
3868 +static void fe_tx_housekeeping(unsigned long ptr)
3870 + struct net_device *dev = (struct net_device*)ptr;
3871 + struct fe_priv *priv = netdev_priv(dev);
3872 + unsigned int bytes_compl = 0;
3873 + unsigned int pkts_compl = 0;
3875 + spin_lock(&priv->page_lock);
3877 + struct fe_tx_dma *txd;
3879 + txd = &priv->tx_dma[priv->tx_free_idx];
3881 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3884 + if (priv->tx_skb[priv->tx_free_idx] != (struct sk_buff *) DMA_DUMMY_DESC) {
3885 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3886 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3889 + priv->tx_skb[priv->tx_free_idx] = NULL;
3890 + priv->tx_free_idx++;
3891 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3892 + priv->tx_free_idx = 0;
3895 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3896 + spin_unlock(&priv->page_lock);
3898 + fe_int_enable(priv->soc->tx_dly_int);
3901 +static void fe_tx_timeout(struct net_device *dev)
3903 + struct fe_priv *priv = netdev_priv(dev);
3905 + tasklet_schedule(&priv->tx_tasklet);
3906 + priv->netdev->stats.tx_errors++;
3907 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3908 + netif_wake_queue(dev);
3911 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3913 + struct fe_priv *priv = netdev_priv(dev);
3914 + unsigned int status;
3915 + unsigned int mask;
3917 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3918 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3920 + if (!(status & mask))
3923 + if (status & priv->soc->rx_dly_int) {
3924 + fe_int_disable(priv->soc->rx_dly_int);
3925 + napi_schedule(&priv->rx_napi);
3928 + if (status & priv->soc->tx_dly_int) {
3929 + fe_int_disable(priv->soc->tx_dly_int);
3930 + tasklet_schedule(&priv->tx_tasklet);
3933 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3935 + return IRQ_HANDLED;
3938 +static int fe_hw_init(struct net_device *dev)
3940 + struct fe_priv *priv = netdev_priv(dev);
3943 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3944 + dev_name(priv->device), dev);
3948 + err = fe_alloc_rx(priv);
3950 + err = fe_alloc_tx(priv);
3954 + if (priv->soc->set_mac)
3955 + priv->soc->set_mac(priv, dev->dev_addr);
3957 + fe_hw_set_macaddr(priv, dev->dev_addr);
3959 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3961 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3963 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3965 + if (priv->soc->fwd_config) {
3966 + priv->soc->fwd_config(priv);
3968 + unsigned long sysclk = priv->sysclk;
3971 + netdev_err(dev, "unable to get clock\n");
3975 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3976 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3978 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3979 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3982 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3983 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3984 + FE_GDMA1_FWD_CFG);
3985 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3987 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3990 + fe_w32(1, FE_FE_RST_GL);
3991 + fe_w32(0, FE_FE_RST_GL);
3996 +static int fe_open(struct net_device *dev)
3998 + struct fe_priv *priv = netdev_priv(dev);
3999 + unsigned long flags;
4002 + spin_lock_irqsave(&priv->page_lock, flags);
4003 + napi_enable(&priv->rx_napi);
4005 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4006 + val |= priv->soc->pdma_glo_cfg;
4007 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4009 + spin_unlock_irqrestore(&priv->page_lock, flags);
4012 + priv->phy->start(priv);
4014 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4015 + netif_carrier_on(dev);
4017 + netif_start_queue(dev);
4018 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4023 +static int fe_stop(struct net_device *dev)
4025 + struct fe_priv *priv = netdev_priv(dev);
4026 + unsigned long flags;
4028 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4030 + netif_stop_queue(dev);
4033 + priv->phy->stop(priv);
4035 + spin_lock_irqsave(&priv->page_lock, flags);
4036 + napi_disable(&priv->rx_napi);
4038 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4039 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4040 + FE_REG_PDMA_GLO_CFG);
4041 + spin_unlock_irqrestore(&priv->page_lock, flags);
4046 +static int __init fe_init(struct net_device *dev)
4048 + struct fe_priv *priv = netdev_priv(dev);
4049 + struct device_node *port;
4052 + BUG_ON(!priv->soc->reset_fe);
4053 + priv->soc->reset_fe();
4055 + if (priv->soc->switch_init)
4056 + priv->soc->switch_init(priv);
4058 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4059 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4061 + err = fe_mdio_init(priv);
4066 + err = priv->phy->connect(priv);
4068 + goto err_mdio_cleanup;
4071 + if (priv->soc->port_init)
4072 + for_each_child_of_node(priv->device->of_node, port)
4073 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4074 + priv->soc->port_init(priv, port);
4076 + err = fe_hw_init(dev);
4078 + goto err_phy_disconnect;
4080 + if (priv->soc->switch_config)
4081 + priv->soc->switch_config(priv);
4085 +err_phy_disconnect:
4087 + priv->phy->disconnect(priv);
4089 + fe_mdio_cleanup(priv);
4094 +static void fe_uninit(struct net_device *dev)
4096 + struct fe_priv *priv = netdev_priv(dev);
4098 + tasklet_kill(&priv->tx_tasklet);
4101 + priv->phy->disconnect(priv);
4102 + fe_mdio_cleanup(priv);
4104 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4105 + free_irq(dev->irq, dev);
4107 + fe_free_dma(priv);
4110 +static const struct net_device_ops fe_netdev_ops = {
4111 + .ndo_init = fe_init,
4112 + .ndo_uninit = fe_uninit,
4113 + .ndo_open = fe_open,
4114 + .ndo_stop = fe_stop,
4115 + .ndo_start_xmit = fe_start_xmit,
4116 + .ndo_tx_timeout = fe_tx_timeout,
4117 + .ndo_set_mac_address = fe_set_mac_address,
4118 + .ndo_change_mtu = eth_change_mtu,
4119 + .ndo_validate_addr = eth_validate_addr,
4122 +static int fe_probe(struct platform_device *pdev)
4124 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4125 + const struct of_device_id *match;
4126 + struct fe_soc_data *soc = NULL;
4127 + struct net_device *netdev;
4128 + struct fe_priv *priv;
4129 + struct clk *sysclk;
4132 + device_reset(&pdev->dev);
4134 + match = of_match_device(of_fe_match, &pdev->dev);
4135 + soc = (struct fe_soc_data *) match->data;
4137 + if (soc->init_data)
4138 + soc->init_data(soc);
4139 + if (soc->reg_table)
4140 + fe_reg_table = soc->reg_table;
4142 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
4146 + netdev = alloc_etherdev(sizeof(struct fe_priv));
4148 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
4152 + strcpy(netdev->name, "eth%d");
4153 + netdev->netdev_ops = &fe_netdev_ops;
4154 + netdev->base_addr = (unsigned long) fe_base;
4155 + netdev->watchdog_timeo = TX_TIMEOUT;
4156 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
4158 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4159 + netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4162 + dev_info(&pdev->dev, "Enabling TSO\n");
4163 + netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
4165 + netdev->hw_features = netdev->features;
4167 + netdev->irq = platform_get_irq(pdev, 0);
4168 + if (netdev->irq < 0) {
4169 + dev_err(&pdev->dev, "no IRQ resource found\n");
4174 + priv = netdev_priv(netdev);
4175 + memset(priv, 0, sizeof(struct fe_priv));
4176 + spin_lock_init(&priv->page_lock);
4178 + sysclk = devm_clk_get(&pdev->dev, NULL);
4179 + if (!IS_ERR(sysclk))
4180 + priv->sysclk = clk_get_rate(sysclk);
4182 + priv->netdev = netdev;
4183 + priv->device = &pdev->dev;
4186 + err = register_netdev(netdev);
4188 + dev_err(&pdev->dev, "error bringing up device\n");
4192 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
4194 +#ifdef CONFIG_INET_LRO
4195 + if (priv->soc->get_skb_header) {
4196 + priv->lro_mgr.dev = netdev;
4197 + memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
4198 + priv->lro_mgr.features = LRO_F_NAPI;
4199 + priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
4200 + priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
4201 + priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
4202 + priv->lro_mgr.max_aggr = 64;
4203 + priv->lro_mgr.frag_align_pad = 0;
4204 + priv->lro_mgr.lro_arr = priv->lro_arr;
4205 + priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
4209 + platform_set_drvdata(pdev, netdev);
4211 + netdev_info(netdev, "done loading\n");
4216 +static int fe_remove(struct platform_device *pdev)
4218 + struct net_device *dev = platform_get_drvdata(pdev);
4219 + struct fe_priv *priv = netdev_priv(dev);
4221 + netif_stop_queue(dev);
4222 + netif_napi_del(&priv->rx_napi);
4224 + unregister_netdev(dev);
4230 +static struct platform_driver fe_driver = {
4231 + .probe = fe_probe,
4232 + .remove = fe_remove,
4234 + .name = "ralink_soc_eth",
4235 + .owner = THIS_MODULE,
4236 + .of_match_table = of_fe_match,
4240 +static int __init init_rtfe(void)
4244 + ret = rtesw_init();
4248 + ret = platform_driver_register(&fe_driver);
4255 +static void __exit exit_rtfe(void)
4257 + platform_driver_unregister(&fe_driver);
4261 +module_init(init_rtfe);
4262 +module_exit(exit_rtfe);
4264 +MODULE_LICENSE("GPL");
4265 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4266 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4268 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
4271 + * This program is free software; you can redistribute it and/or modify
4272 + * it under the terms of the GNU General Public License as published by
4273 + * the Free Software Foundation; version 2 of the License
4275 + * This program is distributed in the hope that it will be useful,
4276 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4277 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4278 + * GNU General Public License for more details.
4280 + * You should have received a copy of the GNU General Public License
4281 + * along with this program; if not, write to the Free Software
4282 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4284 + * based on Ralink SDK3.3
4285 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4291 +#include <linux/mii.h>
4292 +#include <linux/interrupt.h>
4293 +#include <linux/netdevice.h>
4294 +#include <linux/dma-mapping.h>
4295 +#include <linux/phy.h>
4296 +#include <linux/inet_lro.h>
4300 + FE_REG_PDMA_GLO_CFG = 0,
4301 + FE_REG_PDMA_RST_CFG,
4302 + FE_REG_DLY_INT_CFG,
4303 + FE_REG_TX_BASE_PTR0,
4304 + FE_REG_TX_MAX_CNT0,
4305 + FE_REG_TX_CTX_IDX0,
4306 + FE_REG_RX_BASE_PTR0,
4307 + FE_REG_RX_MAX_CNT0,
4308 + FE_REG_RX_CALC_IDX0,
4309 + FE_REG_FE_INT_ENABLE,
4310 + FE_REG_FE_INT_STATUS,
4311 + FE_REG_FE_DMA_VID_BASE,
4315 +#define NUM_DMA_DESC 0x100
4317 +#define FE_DELAY_EN_INT 0x80
4318 +#define FE_DELAY_MAX_INT 0x04
4319 +#define FE_DELAY_MAX_TOUT 0x04
4320 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4321 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4322 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
4324 +/* interrupt bits */
4325 +#define FE_CNT_PPE_AF BIT(31)
4326 +#define FE_CNT_GDM_AF BIT(29)
4327 +#define FE_PSE_P2_FC BIT(26)
4328 +#define FE_PSE_BUF_DROP BIT(24)
4329 +#define FE_GDM_OTHER_DROP BIT(23)
4330 +#define FE_PSE_P1_FC BIT(22)
4331 +#define FE_PSE_P0_FC BIT(21)
4332 +#define FE_PSE_FQ_EMPTY BIT(20)
4333 +#define FE_GE1_STA_CHG BIT(18)
4334 +#define FE_TX_COHERENT BIT(17)
4335 +#define FE_RX_COHERENT BIT(16)
4336 +#define FE_TX_DONE_INT3 BIT(11)
4337 +#define FE_TX_DONE_INT2 BIT(10)
4338 +#define FE_TX_DONE_INT1 BIT(9)
4339 +#define FE_TX_DONE_INT0 BIT(8)
4340 +#define FE_RX_DONE_INT0 BIT(2)
4341 +#define FE_TX_DLY_INT BIT(1)
4342 +#define FE_RX_DLY_INT BIT(0)
4344 +#define RT5350_RX_DLY_INT BIT(30)
4345 +#define RT5350_TX_DLY_INT BIT(28)
4348 +#define FE_FE_OFFSET 0x0000
4349 +#define FE_GDMA_OFFSET 0x0020
4350 +#define FE_PSE_OFFSET 0x0040
4351 +#define FE_GDMA2_OFFSET 0x0060
4352 +#define FE_CDMA_OFFSET 0x0080
4353 +#define FE_DMA_VID0 0x00a8
4354 +#define FE_PDMA_OFFSET 0x0100
4355 +#define FE_PPE_OFFSET 0x0200
4356 +#define FE_CMTABLE_OFFSET 0x0400
4357 +#define FE_POLICYTABLE_OFFSET 0x1000
4359 +#define RT5350_PDMA_OFFSET 0x0800
4360 +#define RT5350_SDM_OFFSET 0x0c00
4362 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
4363 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
4364 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
4365 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
4366 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
4367 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
4368 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
4369 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
4371 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
4372 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
4373 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
4374 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
4375 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
4377 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
4378 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
4379 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
4380 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
4381 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
4383 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
4384 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
4385 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
4386 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
4388 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
4389 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
4391 +#define MT7620A_GDMA_OFFSET 0x0600
4392 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
4393 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
4394 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
4395 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
4396 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
4398 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
4399 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
4400 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
4401 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
4402 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
4403 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
4404 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
4405 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
4406 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
4407 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
4408 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
4409 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
4410 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
4411 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
4412 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
4413 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
4414 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
4415 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
4416 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
4417 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
4418 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
4419 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
4420 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
4421 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
4422 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
4423 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
4424 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
4425 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
4426 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
4427 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
4429 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
4430 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
4431 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
4432 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
4433 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
4434 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
4435 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
4436 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
4437 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
4438 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
4439 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
4440 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
4441 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
4442 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
4443 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
4444 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
4445 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
4446 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
4447 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
4448 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
4449 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
4450 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
4451 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
4452 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
4453 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
4454 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
4455 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
4456 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
4458 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
4459 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
4460 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
4461 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
4462 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
4463 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
4464 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
4465 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
4466 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
4467 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
4469 +#define RT5350_SDM_ICS_EN BIT(16)
4470 +#define RT5350_SDM_TCS_EN BIT(17)
4471 +#define RT5350_SDM_UCS_EN BIT(18)
4474 +/* MDIO_CFG register bits */
4475 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
4476 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
4477 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
4478 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
4479 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
4480 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
4481 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
4482 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
4483 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
4484 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
4485 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
4486 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
4487 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
4488 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
4489 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
4490 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
4491 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
4492 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
4493 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
4494 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
4495 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
4496 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
4497 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
4498 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
4499 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
4501 +/* uni-cast port */
4502 +#define FE_GDM1_ICS_EN BIT(22)
4503 +#define FE_GDM1_TCS_EN BIT(21)
4504 +#define FE_GDM1_UCS_EN BIT(20)
4505 +#define FE_GDM1_JMB_EN BIT(19)
4506 +#define FE_GDM1_STRPCRC BIT(16)
4507 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
4508 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
4509 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
4512 +#define FE_ICS_GEN_EN BIT(2)
4513 +#define FE_UCS_GEN_EN BIT(1)
4514 +#define FE_TCS_GEN_EN BIT(0)
4517 +#define FE_PST_DRX_IDX0 BIT(16)
4518 +#define FE_PST_DTX_IDX3 BIT(3)
4519 +#define FE_PST_DTX_IDX2 BIT(2)
4520 +#define FE_PST_DTX_IDX1 BIT(1)
4521 +#define FE_PST_DTX_IDX0 BIT(0)
4523 +#define FE_TX_WB_DDONE BIT(6)
4524 +#define FE_RX_DMA_BUSY BIT(3)
4525 +#define FE_TX_DMA_BUSY BIT(1)
4526 +#define FE_RX_DMA_EN BIT(2)
4527 +#define FE_TX_DMA_EN BIT(0)
4529 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
4530 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
4531 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
4533 +#define FE_US_CYC_CNT_MASK 0xff
4534 +#define FE_US_CYC_CNT_SHIFT 0x8
4535 +#define FE_US_CYC_CNT_DIVISOR 1000000
4537 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
4538 +#define RX_DMA_LSO BIT(30)
4539 +#define RX_DMA_DONE BIT(31)
4540 +#define RX_DMA_L4VALID BIT(30)
4543 + unsigned int rxd1;
4544 + unsigned int rxd2;
4545 + unsigned int rxd3;
4546 + unsigned int rxd4;
4547 +} __packed __aligned(4);
4549 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
4550 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
4551 +#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
4552 +#define TX_DMA_LS1 BIT(14)
4553 +#define TX_DMA_LSO BIT(30)
4554 +#define TX_DMA_DONE BIT(31)
4555 +#define TX_DMA_QN(_x) ((_x) << 16)
4556 +#define TX_DMA_PN(_x) ((_x) << 24)
4557 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
4558 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
4559 +#define TX_DMA_CHKSUM (0x7 << 29)
4562 + unsigned int txd1;
4563 + unsigned int txd2;
4564 + unsigned int txd3;
4565 + unsigned int txd4;
4566 +} __packed __aligned(4);
4571 + struct phy_device *phy[8];
4572 + struct device_node *phy_node[8];
4573 + const __be32 *phy_fixed[8];
4580 + int (*connect)(struct fe_priv *priv);
4581 + void (*disconnect)(struct fe_priv *priv);
4582 + void (*start)(struct fe_priv *priv);
4583 + void (*stop)(struct fe_priv *priv);
4588 + unsigned char mac[6];
4589 + const u32 *reg_table;
4591 + void (*init_data)(struct fe_soc_data *data);
4592 + void (*reset_fe)(void);
4593 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
4594 + void (*fwd_config)(struct fe_priv *priv);
4595 + void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
4596 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
4597 + int (*switch_init)(struct fe_priv *priv);
4598 + int (*switch_config)(struct fe_priv *priv);
4599 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
4600 + int (*has_carrier)(struct fe_priv *priv);
4601 + int (*mdio_init)(struct fe_priv *priv);
4602 + void (*mdio_cleanup)(struct fe_priv *priv);
4603 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
4604 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
4605 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
4606 + int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
4620 + spinlock_t page_lock;
4622 + struct fe_soc_data *soc;
4623 + struct net_device *netdev;
4624 + struct device *device;
4625 + unsigned long sysclk;
4627 + struct fe_rx_dma *rx_dma;
4628 + struct napi_struct rx_napi;
4629 + struct sk_buff *rx_skb[NUM_DMA_DESC];
4630 + dma_addr_t rx_phys;
4632 + struct fe_tx_dma *tx_dma;
4633 + struct tasklet_struct tx_tasklet;
4634 + struct sk_buff *tx_skb[NUM_DMA_DESC];
4635 + dma_addr_t tx_phys;
4636 + unsigned int tx_free_idx;
4638 + struct fe_phy *phy;
4639 + struct mii_bus *mii_bus;
4640 + int mii_irq[PHY_MAX_ADDR];
4644 + struct net_lro_mgr lro_mgr;
4645 + struct net_lro_desc lro_arr[8];
4648 +extern const struct of_device_id of_fe_match[];
4650 +void fe_w32(u32 val, unsigned reg);
4651 +u32 fe_r32(unsigned reg);
4653 +#endif /* FE_ETH_H */
4655 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
4658 + * This program is free software; you can redistribute it and/or modify
4659 + * it under the terms of the GNU General Public License as published by
4660 + * the Free Software Foundation; version 2 of the License
4662 + * This program is distributed in the hope that it will be useful,
4663 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4664 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4665 + * GNU General Public License for more details.
4667 + * You should have received a copy of the GNU General Public License
4668 + * along with this program; if not, write to the Free Software
4669 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4671 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4674 +#include <linux/module.h>
4675 +#include <linux/platform_device.h>
4676 +#include <linux/if_vlan.h>
4678 +#include <asm/mach-ralink/ralink_regs.h>
4680 +#include <mt7620.h>
4681 +#include "ralink_soc_eth.h"
4682 +#include "gsw_mt7620a.h"
4684 +#define MT7620A_CDMA_CSG_CFG 0x400
4685 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
4686 +#define MT7620A_DMA_2B_OFFSET BIT(31)
4687 +#define MT7620A_RESET_FE BIT(21)
4688 +#define MT7620A_RESET_ESW BIT(23)
4689 +#define MT7620_L4_VALID BIT(23)
4691 +#define SYSC_REG_RESET_CTRL 0x34
4692 +#define MAX_RX_LENGTH 1536
4694 +#define CDMA_ICS_EN BIT(2)
4695 +#define CDMA_UCS_EN BIT(1)
4696 +#define CDMA_TCS_EN BIT(0)
4698 +#define GDMA_ICS_EN BIT(22)
4699 +#define GDMA_TCS_EN BIT(21)
4700 +#define GDMA_UCS_EN BIT(20)
4702 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4703 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4704 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4705 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4706 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4707 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4708 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4709 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4710 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4711 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4712 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4713 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4714 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4717 +static void mt7620_fe_reset(void)
4719 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4720 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4723 +static void mt7620_fwd_config(struct fe_priv *priv)
4727 + /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4728 + for (i = 0; i < 16; i += 2)
4729 + fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
4731 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4732 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4733 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4736 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
4738 + unsigned int nr_frags = 0;
4739 + unsigned int len = 0;
4742 + nr_frags = skb_shinfo(skb)->nr_frags;
4743 + len = skb->len - skb->data_len;
4747 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4748 + else if (!nr_frags)
4749 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4751 + priv->tx_dma[idx].txd2 = TX_DMA_PLEN0(len);
4753 + if(skb && vlan_tx_tag_present(skb))
4754 + priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
4756 + priv->tx_dma[idx].txd4 = 0;
4759 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4761 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4764 +#ifdef CONFIG_INET_LRO
4766 +mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
4767 + u64 *hdr_flags, void *_priv)
4769 + struct iphdr *iph = NULL;
4773 + * Make sure that this packet is Ethernet II, is not VLAN
4774 + * tagged, is IPv4, has a valid IP header, and is TCP.
4776 + if (skb->protocol == 0x0081)
4777 + vhdr_len = VLAN_HLEN;
4779 + iph = (struct iphdr *)(skb->data + vhdr_len);
4780 + if(iph->protocol != IPPROTO_TCP)
4784 + *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
4785 + *hdr_flags = LRO_IPV4 | LRO_TCP;
4791 +static void mt7620_init_data(struct fe_soc_data *data)
4793 + if (mt7620_get_eco() >= 5)
4797 +static struct fe_soc_data mt7620_data = {
4798 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4799 + .init_data = mt7620_init_data,
4800 + .reset_fe = mt7620_fe_reset,
4801 + .set_mac = mt7620_set_mac,
4802 + .fwd_config = mt7620_fwd_config,
4803 + .tx_dma = mt7620_tx_dma,
4804 + .rx_dma = mt7620_rx_dma,
4805 + .switch_init = mt7620_gsw_probe,
4806 + .switch_config = mt7620_gsw_config,
4807 + .port_init = mt7620_port_init,
4809 + .reg_table = rt5350_reg_table,
4810 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4811 + .rx_dly_int = RT5350_RX_DLY_INT,
4812 + .tx_dly_int = RT5350_TX_DLY_INT,
4813 + .checksum_bit = MT7620_L4_VALID,
4814 + .has_carrier = mt7620a_has_carrier,
4815 + .mdio_read = mt7620_mdio_read,
4816 + .mdio_write = mt7620_mdio_write,
4817 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4818 +#ifdef CONFIG_INET_LRO
4819 + .get_skb_header = mt7620_get_skb_header,
4823 +const struct of_device_id of_fe_match[] = {
4824 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4828 +MODULE_DEVICE_TABLE(of, of_fe_match);
4830 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4833 + * This program is free software; you can redistribute it and/or modify
4834 + * it under the terms of the GNU General Public License as published by
4835 + * the Free Software Foundation; version 2 of the License
4837 + * This program is distributed in the hope that it will be useful,
4838 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4839 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4840 + * GNU General Public License for more details.
4842 + * You should have received a copy of the GNU General Public License
4843 + * along with this program; if not, write to the Free Software
4844 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4846 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4849 +#include <linux/module.h>
4851 +#include <asm/mach-ralink/ralink_regs.h>
4853 +#include "ralink_soc_eth.h"
4854 +#include "mdio_rt2880.h"
4856 +#define SYSC_REG_RESET_CTRL 0x034
4857 +#define RT2880_RESET_FE BIT(18)
4859 +void rt2880_fe_reset(void)
4861 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4864 +struct fe_soc_data rt2880_data = {
4865 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4866 + .reset_fe = rt2880_fe_reset,
4867 + .min_pkt_len = 64,
4868 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4869 + .checksum_bit = RX_DMA_L4VALID,
4870 + .rx_dly_int = FE_RX_DLY_INT,
4871 + .tx_dly_int = FE_TX_DLY_INT,
4872 + .mdio_read = rt2880_mdio_read,
4873 + .mdio_write = rt2880_mdio_write,
4874 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4875 + .port_init = rt2880_port_init,
4878 +const struct of_device_id of_fe_match[] = {
4879 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4883 +MODULE_DEVICE_TABLE(of, of_fe_match);
4885 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4888 + * This program is free software; you can redistribute it and/or modify
4889 + * it under the terms of the GNU General Public License as published by
4890 + * the Free Software Foundation; version 2 of the License
4892 + * This program is distributed in the hope that it will be useful,
4893 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4894 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4895 + * GNU General Public License for more details.
4897 + * You should have received a copy of the GNU General Public License
4898 + * along with this program; if not, write to the Free Software
4899 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4901 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4904 +#include <linux/module.h>
4906 +#include <asm/mach-ralink/ralink_regs.h>
4908 +#include "ralink_soc_eth.h"
4910 +#define RT305X_RESET_FE BIT(21)
4911 +#define RT305X_RESET_ESW BIT(23)
4912 +#define SYSC_REG_RESET_CTRL 0x034
4914 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4915 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4916 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4917 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4918 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4919 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4920 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4921 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4922 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4923 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4924 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4925 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4926 + [FE_REG_FE_DMA_VID_BASE] = 0,
4929 +static void rt305x_fe_reset(void)
4931 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4932 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4935 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4937 + unsigned long flags;
4939 + spin_lock_irqsave(&priv->page_lock, flags);
4940 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4941 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4942 + RT5350_SDM_MAC_ADRL);
4943 + spin_unlock_irqrestore(&priv->page_lock, flags);
4946 +static void rt5350_fwd_config(struct fe_priv *priv)
4948 + unsigned long sysclk = priv->sysclk;
4951 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4952 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4954 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4955 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4959 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4960 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4964 +static void rt5350_fe_reset(void)
4966 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4967 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4970 +static struct fe_soc_data rt3050_data = {
4971 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4972 + .reset_fe = rt305x_fe_reset,
4973 + .min_pkt_len = 64,
4974 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4975 + .checksum_bit = RX_DMA_L4VALID,
4976 + .rx_dly_int = FE_RX_DLY_INT,
4977 + .tx_dly_int = FE_TX_DLY_INT,
4980 +static struct fe_soc_data rt5350_data = {
4981 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4982 + .reg_table = rt5350_reg_table,
4983 + .reset_fe = rt5350_fe_reset,
4984 + .set_mac = rt5350_set_mac,
4985 + .fwd_config = rt5350_fwd_config,
4986 + .min_pkt_len = 64,
4987 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4988 + .checksum_bit = RX_DMA_L4VALID,
4989 + .rx_dly_int = RT5350_RX_DLY_INT,
4990 + .tx_dly_int = RT5350_TX_DLY_INT,
4993 +const struct of_device_id of_fe_match[] = {
4994 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4995 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4999 +MODULE_DEVICE_TABLE(of, of_fe_match);
5001 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
5004 + * This program is free software; you can redistribute it and/or modify
5005 + * it under the terms of the GNU General Public License as published by
5006 + * the Free Software Foundation; version 2 of the License
5008 + * This program is distributed in the hope that it will be useful,
5009 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5010 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5011 + * GNU General Public License for more details.
5013 + * You should have received a copy of the GNU General Public License
5014 + * along with this program; if not, write to the Free Software
5015 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5017 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5020 +#include <linux/module.h>
5022 +#include <asm/mach-ralink/ralink_regs.h>
5024 +#include "ralink_soc_eth.h"
5025 +#include "mdio_rt2880.h"
5027 +#define RT3883_SYSC_REG_RSTCTRL 0x34
5028 +#define RT3883_RSTCTRL_FE BIT(21)
5030 +static void rt3883_fe_reset(void)
5034 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5035 + t |= RT3883_RSTCTRL_FE;
5036 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5038 + t &= ~RT3883_RSTCTRL_FE;
5039 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5042 +static struct fe_soc_data rt3883_data = {
5043 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5044 + .reset_fe = rt3883_fe_reset,
5045 + .min_pkt_len = 64,
5046 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
5047 + .rx_dly_int = FE_RX_DLY_INT,
5048 + .tx_dly_int = FE_TX_DLY_INT,
5049 + .checksum_bit = RX_DMA_L4VALID,
5050 + .mdio_read = rt2880_mdio_read,
5051 + .mdio_write = rt2880_mdio_write,
5052 + .mdio_adjust_link = rt2880_mdio_link_adjust,
5053 + .port_init = rt2880_port_init,
5056 +const struct of_device_id of_fe_match[] = {
5057 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5061 +MODULE_DEVICE_TABLE(of, of_fe_match);