1 From e410b0069ee7c318a5b556f39b8b16814330a208 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 24 Jan 2014 17:01:17 +0100
4 Subject: [PATCH 15/57] MIPS: ralink: cleanup early_printk
6 Add support for the new MT7621/8 SoC and kill ifdefs.
7 Cleanup some whitespace error while we are at it.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/ralink/early_printk.c | 45 ++++++++++++++++++++++++++-------------
12 1 file changed, 30 insertions(+), 15 deletions(-)
14 diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
15 index b46d041..255d695 100644
16 --- a/arch/mips/ralink/early_printk.c
17 +++ b/arch/mips/ralink/early_printk.c
19 #include <asm/addrspace.h>
21 #ifdef CONFIG_SOC_RT288X
22 -#define EARLY_UART_BASE 0x300c00
23 +#define EARLY_UART_BASE 0x300c00
24 +#define CHIPID_BASE 0x300004
25 +#elif defined(CONFIG_SOC_MT7621)
26 +#define EARLY_UART_BASE 0x1E000c00
27 +#define CHIPID_BASE 0x1E000004
29 -#define EARLY_UART_BASE 0x10000c00
30 +#define EARLY_UART_BASE 0x10000c00
31 +#define CHIPID_BASE 0x10000004
34 -#define UART_REG_RX 0x00
35 -#define UART_REG_TX 0x04
36 -#define UART_REG_IER 0x08
37 -#define UART_REG_IIR 0x0c
38 -#define UART_REG_FCR 0x10
39 -#define UART_REG_LCR 0x14
40 -#define UART_REG_MCR 0x18
41 -#define UART_REG_LSR 0x1c
42 +#define MT7628_CHIP_NAME1 0x20203832
44 +#define UART_REG_TX 0x04
45 +#define UART_REG_LSR 0x14
46 +#define UART_REG_LSR_RT2880 0x1c
48 static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE);
49 +static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE);
51 static inline void uart_w32(u32 val, unsigned reg)
53 @@ -38,11 +41,23 @@ static inline u32 uart_r32(unsigned reg)
54 return __raw_readl(uart_membase + reg);
57 +static inline int soc_is_mt7628(void)
59 + return IS_ENABLED(CONFIG_SOC_MT7620) &&
60 + (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1);
63 void prom_putchar(unsigned char ch)
65 - while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
67 - uart_w32(ch, UART_REG_TX);
68 - while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
70 + if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) {
71 + uart_w32(ch, UART_TX);
72 + while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
75 + while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)
77 + uart_w32(ch, UART_REG_TX);
78 + while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0)