1 From 50216a5b7b3cc269043e7123db4bea262e35364e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 2 Dec 2013 16:13:40 +0100
4 Subject: [PATCH 504/507] MIPS: ralink: add pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7621.c | 797 ++++++++++++++++++++++++++++++++++++++++++++
10 2 files changed, 798 insertions(+)
11 create mode 100644 arch/mips/pci/pci-mt7621.c
13 diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
14 index 719e455..80886fe 100644
15 --- a/arch/mips/pci/Makefile
16 +++ b/arch/mips/pci/Makefile
17 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
18 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
19 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
20 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
21 +obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
22 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
23 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
24 obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
25 diff --git a/arch/mips/pci/pci-mt7621.c b/arch/mips/pci/pci-mt7621.c
27 index 0000000..0b58fce
29 +++ b/arch/mips/pci/pci-mt7621.c
31 +/**************************************************************************
33 + * BRIEF MODULE DESCRIPTION
34 + * PCI init for Ralink RT2880 solution
36 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
38 + * This program is free software; you can redistribute it and/or modify it
39 + * under the terms of the GNU General Public License as published by the
40 + * Free Software Foundation; either version 2 of the License, or (at your
41 + * option) any later version.
43 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
45 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
46 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
47 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
48 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
49 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
50 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
52 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 + * You should have received a copy of the GNU General Public License along
55 + * with this program; if not, write to the Free Software Foundation, Inc.,
56 + * 675 Mass Ave, Cambridge, MA 02139, USA.
59 + **************************************************************************
60 + * May 2007 Bruce Chang
63 + * May 2009 Bruce Chang
64 + * support RT2880/RT3883 PCIe
66 + * May 2011 Bruce Chang
67 + * support RT6855/MT7620 PCIe
69 + **************************************************************************
72 +#include <linux/types.h>
73 +#include <linux/pci.h>
74 +#include <linux/kernel.h>
75 +#include <linux/slab.h>
76 +#include <linux/version.h>
79 +//#include <asm/mach-ralink/eureka_ep430.h>
80 +#include <linux/init.h>
81 +#include <linux/mod_devicetable.h>
82 +#include <linux/delay.h>
83 +//#include <asm/rt2880/surfboardint.h>
85 +#include <ralink_regs.h>
87 +extern void pcie_phy_init(void);
88 +extern void chk_phy_pll(void);
91 + * These functions and structures provide the BIOS scan and mapping of the PCI
95 +#define CONFIG_PCIE_PORT0
96 +#define CONFIG_PCIE_PORT1
97 +#define CONFIG_PCIE_PORT2
98 +#define RALINK_PCIE0_CLK_EN (1<<24)
99 +#define RALINK_PCIE1_CLK_EN (1<<25)
100 +#define RALINK_PCIE2_CLK_EN (1<<26)
102 +#define RALINK_PCI_CONFIG_ADDR 0x20
103 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
104 +#define SURFBOARDINT_PCIE0 12 /* PCIE0 */
105 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
106 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
107 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
108 +#define SURFBOARDINT_PCIE1 32 /* PCIE1 */
109 +#define SURFBOARDINT_PCIE2 33 /* PCIE2 */
110 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
111 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
112 +#define RALINK_PCIE0_RST (1<<24)
113 +#define RALINK_PCIE1_RST (1<<25)
114 +#define RALINK_PCIE2_RST (1<<26)
115 +#define RALINK_SYSCTL_BASE 0xBE000000
117 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
118 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
119 +#define RALINK_PCI_BASE 0xBE140000
121 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
122 +#define RT6855_PCIE0_OFFSET 0x2000
123 +#define RT6855_PCIE1_OFFSET 0x3000
124 +#define RT6855_PCIE2_OFFSET 0x4000
126 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
127 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
128 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
129 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
130 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
131 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
132 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
133 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
135 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
136 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
137 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
138 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
139 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
140 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
141 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
142 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
144 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
145 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
146 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
147 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
148 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
149 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
150 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
151 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
153 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
154 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
157 +#define MV_WRITE(ofs, data) \
158 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
159 +#define MV_READ(ofs, data) \
160 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
161 +#define MV_READ_DATA(ofs) \
162 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
164 +#define MV_WRITE_16(ofs, data) \
165 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
166 +#define MV_READ_16(ofs, data) \
167 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
169 +#define MV_WRITE_8(ofs, data) \
170 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
171 +#define MV_READ_8(ofs, data) \
172 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
176 +#define RALINK_PCI_MM_MAP_BASE 0x60000000
177 +#define RALINK_PCI_IO_MAP_BASE 0x1e160000
179 +#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
181 +#define ASSERT_SYSRST_PCIE(val) do { \
182 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
183 + RALINK_RSTCTRL |= val; \
185 + RALINK_RSTCTRL &= ~val; \
187 +#define DEASSERT_SYSRST_PCIE(val) do { \
188 + if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
189 + RALINK_RSTCTRL &= ~val; \
191 + RALINK_RSTCTRL |= val; \
193 +#define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
194 +#define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
195 +#define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
196 +#define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
197 +#define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
198 +#define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
199 +#define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
200 +#define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
201 +//RALINK_SYSCFG1 bit
202 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
203 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
204 +//RALINK_RSTCTRL bit
205 +#define RALINK_PCIE_RST (1<<23)
206 +#define RALINK_PCI_RST (1<<24)
207 +//RALINK_CLKCFG1 bit
208 +#define RALINK_PCI_CLK_EN (1<<19)
209 +#define RALINK_PCIE_CLK_EN (1<<21)
210 +//RALINK_GPIOMODE bit
211 +#define PCI_SLOTx2 (1<<11)
212 +#define PCI_SLOTx1 (2<<11)
214 +#define PDRV_SW_SET (1<<31)
215 +#define LC_CKDRVPD_ (1<<19)
217 +#define MEMORY_BASE 0x0
218 +int pcie_link_status = 0;
220 +void __inline__ read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val);
221 +void __inline__ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val);
223 +#define PCI_ACCESS_READ_1 0
224 +#define PCI_ACCESS_READ_2 1
225 +#define PCI_ACCESS_READ_4 2
226 +#define PCI_ACCESS_WRITE_1 3
227 +#define PCI_ACCESS_WRITE_2 4
228 +#define PCI_ACCESS_WRITE_4 5
230 +static int config_access(unsigned char access_type, struct pci_bus *bus,
231 + unsigned int devfn, unsigned int where, u32 * data)
233 + unsigned int slot = PCI_SLOT(devfn);
234 + u8 func = PCI_FUNC(devfn);
235 + uint32_t address_reg, data_reg;
236 + unsigned int address;
238 + address_reg = RALINK_PCI_CONFIG_ADDR;
239 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
241 + address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
242 + MV_WRITE(address_reg, address);
244 + switch(access_type) {
245 + case PCI_ACCESS_WRITE_1:
246 + MV_WRITE_8(data_reg+(where&0x3), *data);
248 + case PCI_ACCESS_WRITE_2:
249 + MV_WRITE_16(data_reg+(where&0x3), *data);
251 + case PCI_ACCESS_WRITE_4:
252 + MV_WRITE(data_reg, *data);
254 + case PCI_ACCESS_READ_1:
255 + MV_READ_8( data_reg+(where&0x3), data);
257 + case PCI_ACCESS_READ_2:
258 + MV_READ_16(data_reg+(where&0x3), data);
260 + case PCI_ACCESS_READ_4:
261 + MV_READ(data_reg, data);
264 + printk("no specify access type\n");
271 +read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
273 + return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
277 +read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
279 + return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
283 +read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
285 + return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
289 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
291 + if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
294 + return PCIBIOS_SUCCESSFUL;
298 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
300 + if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
303 + return PCIBIOS_SUCCESSFUL;
307 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
309 + if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
312 + return PCIBIOS_SUCCESSFUL;
317 +pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
321 + return read_config_byte(bus, devfn, where, (u8 *) val);
323 + return read_config_word(bus, devfn, where, (u16 *) val);
325 + return read_config_dword(bus, devfn, where, val);
330 +pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
334 + return write_config_byte(bus, devfn, where, (u8) val);
336 + return write_config_word(bus, devfn, where, (u16) val);
338 + return write_config_dword(bus, devfn, where, val);
342 +struct pci_ops rt2880_pci_ops= {
343 + .read = pci_config_read,
344 + .write = pci_config_write,
347 +static struct resource rt2880_res_pci_mem1 = {
348 + .name = "PCI MEM1",
349 + .start = RALINK_PCI_MM_MAP_BASE,
350 + .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
351 + .flags = IORESOURCE_MEM,
353 +static struct resource rt2880_res_pci_io1 = {
354 + .name = "PCI I/O1",
355 + .start = RALINK_PCI_IO_MAP_BASE,
356 + .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
357 + .flags = IORESOURCE_IO,
360 +struct pci_controller rt2880_controller = {
361 + .pci_ops = &rt2880_pci_ops,
362 + .mem_resource = &rt2880_res_pci_mem1,
363 + .io_resource = &rt2880_res_pci_io1,
364 + .mem_offset = 0x00000000UL,
365 + .io_offset = 0x00000000UL,
366 + .io_map_base = 0xa0000000,
370 +read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
372 + unsigned int address_reg, data_reg, address;
374 + address_reg = RALINK_PCI_CONFIG_ADDR;
375 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
376 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
377 + MV_WRITE(address_reg, address);
378 + MV_READ(data_reg, val);
383 +write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
385 + unsigned int address_reg, data_reg, address;
387 + address_reg = RALINK_PCI_CONFIG_ADDR;
388 + data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
389 + address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
390 + MV_WRITE(address_reg, address);
391 + MV_WRITE(data_reg, val);
397 +pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
403 + if ((dev->bus->number == 0) && (slot == 0)) {
404 + write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
405 + read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
406 + printk("BAR0 at slot 0 = %x\n", val);
407 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
408 + } else if((dev->bus->number == 0) && (slot == 0x1)) {
409 + write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
410 + read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
411 + printk("BAR0 at slot 1 = %x\n", val);
412 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
413 + } else if((dev->bus->number == 0) && (slot == 0x2)) {
414 + write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
415 + read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
416 + printk("BAR0 at slot 2 = %x\n", val);
417 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
418 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
419 + switch (pcie_link_status) {
422 + irq = RALINK_INT_PCIE1;
425 + irq = RALINK_INT_PCIE2;
428 + irq = RALINK_INT_PCIE0;
430 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
431 + } else if ((dev->bus->number == 2) && (slot == 0x0)) {
432 + switch (pcie_link_status) {
435 + irq = RALINK_INT_PCIE2;
438 + irq = RALINK_INT_PCIE1;
440 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
441 + } else if ((dev->bus->number == 2) && (slot == 0x1)) {
442 + switch (pcie_link_status) {
445 + irq = RALINK_INT_PCIE2;
448 + irq = RALINK_INT_PCIE1;
450 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
451 + } else if ((dev->bus->number ==3) && (slot == 0x0)) {
452 + irq = RALINK_INT_PCIE2;
453 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
454 + } else if ((dev->bus->number ==3) && (slot == 0x1)) {
455 + irq = RALINK_INT_PCIE2;
456 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
457 + } else if ((dev->bus->number ==3) && (slot == 0x2)) {
458 + irq = RALINK_INT_PCIE2;
459 + printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
461 + printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
465 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
466 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
467 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
468 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
469 + pci_write_config_word(dev, PCI_COMMAND, cmd);
470 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
475 +set_pcie_phy(u32 *addr, int start_b, int bits, int val)
477 +// printk("0x%p:", addr);
478 +// printk(" %x", *addr);
479 + *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
480 + *(unsigned int *)(addr) |= val << start_b;
481 +// printk(" -> %x\n", *addr);
485 +bypass_pipe_rst(void)
487 +#if defined (CONFIG_PCIE_PORT0)
489 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
490 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
492 +#if defined (CONFIG_PCIE_PORT1)
494 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
495 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
497 +#if defined (CONFIG_PCIE_PORT2)
499 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
500 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
505 +set_phy_for_ssc(void)
507 + unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
509 + reg = (reg >> 6) & 0x7;
510 +#if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
511 + /* Set PCIe Port0 & Port1 PHY to disable SSC */
512 + /* Debug Xtal Type */
513 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
514 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
515 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
516 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
517 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
518 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
519 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
520 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
521 + printk("***** Xtal 40MHz *****\n");
522 + } else { // 25MHz | 20MHz Xtal
523 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
525 + printk("***** Xtal 25MHz *****\n");
526 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
527 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
528 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
529 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
530 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
532 + printk("***** Xtal 20MHz *****\n");
535 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
536 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
537 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
538 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
539 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
540 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
541 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
542 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
543 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
544 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
546 + /* Enable PHY and disable force mode */
547 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
548 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
549 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
550 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
552 +#if defined (CONFIG_PCIE_PORT2)
553 + /* Set PCIe Port2 PHY to disable SSC */
554 + /* Debug Xtal Type */
555 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
556 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
557 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
558 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
559 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
560 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
561 + } else { // 25MHz | 20MHz Xtal
562 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
563 + if (reg >= 6) { // 25MHz Xtal
564 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
565 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
566 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
567 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
568 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
571 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
572 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
573 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
574 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
575 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
576 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
577 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
578 + if(reg <= 5 && reg >= 3) { // 40MHz Xtal
579 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
580 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
582 + /* Enable PHY and disable force mode */
583 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
584 + set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
588 +int init_rt2880pci(void)
590 + unsigned long val = 0;
591 + iomem_resource.start = 0;
592 + iomem_resource.end= ~0;
593 + ioport_resource.start= 0;
594 + ioport_resource.end = ~0;
596 +#if defined (CONFIG_PCIE_PORT0)
597 + val = RALINK_PCIE0_RST;
599 +#if defined (CONFIG_PCIE_PORT1)
600 + val |= RALINK_PCIE1_RST;
602 +#if defined (CONFIG_PCIE_PORT2)
603 + val |= RALINK_PCIE2_RST;
605 + DEASSERT_SYSRST_PCIE(val);
606 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
610 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
611 + printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
612 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
613 + *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
614 + *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
616 + *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
618 + *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
622 + *(unsigned int *)(0xbe000060) &= ~0x00000c00;
624 +#if defined (CONFIG_PCIE_PORT0)
625 + val = RALINK_PCIE0_RST;
627 +#if defined (CONFIG_PCIE_PORT1)
628 + val |= RALINK_PCIE1_RST;
630 +#if defined (CONFIG_PCIE_PORT2)
631 + val |= RALINK_PCIE2_RST;
633 + DEASSERT_SYSRST_PCIE(val);
634 + printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
635 +#if defined (CONFIG_PCIE_PORT0)
636 + read_config(0, 0, 0, 0x70c, &val);
639 + write_config(0, 0, 0, 0x70c, val);
641 +#if defined (CONFIG_PCIE_PORT1)
642 + read_config(0, 1, 0, 0x70c, &val);
645 + write_config(0, 1, 0, 0x70c, val);
647 +#if defined (CONFIG_PCIE_PORT2)
648 + read_config(0, 2, 0, 0x70c, &val);
651 + write_config(0, 2, 0, 0x70c, val);
654 +#if defined (CONFIG_PCIE_PORT0)
655 + read_config(0, 0, 0, 0x70c, &val);
656 + printk("Port 0 N_FTS = %x\n", (unsigned int)val);
658 +#if defined (CONFIG_PCIE_PORT1)
659 + read_config(0, 1, 0, 0x70c, &val);
660 + printk("Port 1 N_FTS = %x\n", (unsigned int)val);
662 +#if defined (CONFIG_PCIE_PORT2)
663 + read_config(0, 2, 0, 0x70c, &val);
664 + printk("Port 2 N_FTS = %x\n", (unsigned int)val);
667 + RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
668 + RALINK_SYSCFG1 &= ~(0x30);
669 + RALINK_SYSCFG1 |= (2<<4);
670 + RALINK_PCIE_CLK_GEN &= 0x7fffffff;
671 + RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
672 + RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
673 + RALINK_PCIE_CLK_GEN |= 0x80000000;
675 + RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
678 +#if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
679 + *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
682 + RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
688 +#if defined (CONFIG_PCIE_PORT0)
689 + if(( RALINK_PCI0_STATUS & 0x1) == 0)
691 + printk("PCIE0 no card, disable it(RST&CLK)\n");
692 + ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
693 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
694 + pcie_link_status &= ~(1<<0);
696 + pcie_link_status |= 1<<0;
697 + RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
700 +#if defined (CONFIG_PCIE_PORT1)
701 + if(( RALINK_PCI1_STATUS & 0x1) == 0)
703 + printk("PCIE1 no card, disable it(RST&CLK)\n");
704 + ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
705 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
706 + pcie_link_status &= ~(1<<1);
708 + pcie_link_status |= 1<<1;
709 + RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
712 +#if defined (CONFIG_PCIE_PORT2)
713 + if (( RALINK_PCI2_STATUS & 0x1) == 0) {
714 + printk("PCIE2 no card, disable it(RST&CLK)\n");
715 + ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
716 + RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
717 + pcie_link_status &= ~(1<<2);
719 + pcie_link_status |= 1<<2;
720 + RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
723 + if (pcie_link_status == 0)
727 +pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
737 + switch(pcie_link_status) {
739 + RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
740 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
741 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
744 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
745 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
746 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
747 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
750 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
751 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
752 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
753 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
756 + RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
757 + RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
758 + RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
759 + RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
762 + printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
763 + //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
766 + ioport_resource.start = rt2880_res_pci_io1.start;
767 + ioport_resource.end = rt2880_res_pci_io1.end;
770 + RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
771 + RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
773 +#if defined (CONFIG_PCIE_PORT0)
775 + if((pcie_link_status & 0x1) != 0) {
776 + RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
777 + RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
778 + RALINK_PCI0_CLASS = 0x06040001;
779 + printk("PCIE0 enabled\n");
782 +#if defined (CONFIG_PCIE_PORT1)
784 + if ((pcie_link_status & 0x2) != 0) {
785 + RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
786 + RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
787 + RALINK_PCI1_CLASS = 0x06040001;
788 + printk("PCIE1 enabled\n");
791 +#if defined (CONFIG_PCIE_PORT2)
793 + if ((pcie_link_status & 0x4) != 0) {
794 + RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
795 + RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
796 + RALINK_PCI2_CLASS = 0x06040001;
797 + printk("PCIE2 enabled\n");
802 + switch(pcie_link_status) {
804 + read_config(0, 2, 0, 0x4, &val);
805 + write_config(0, 2, 0, 0x4, val|0x4);
806 + // write_config(0, 1, 0, 0x4, val|0x7);
810 + read_config(0, 1, 0, 0x4, &val);
811 + write_config(0, 1, 0, 0x4, val|0x4);
812 + // write_config(0, 1, 0, 0x4, val|0x7);
814 + read_config(0, 0, 0, 0x4, &val);
815 + write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
816 + // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
818 + register_pci_controller(&rt2880_controller);
822 +arch_initcall(init_rt2880pci);
824 +int pcibios_plat_dev_init(struct pci_dev *dev)