1 From 99342a0481d49b6e1ade90fdb02f597cb75f103f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 2 Dec 2013 16:11:09 +0100
4 Subject: [PATCH 502/507] MIPS: ralink: add MT7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/include/asm/mach-ralink/mt7621.h | 39 +++++
9 arch/mips/ralink/Kconfig | 18 ++
10 arch/mips/ralink/Makefile | 7 +-
11 arch/mips/ralink/Platform | 5 +
12 arch/mips/ralink/irq-gic.c | 255 ++++++++++++++++++++++++++++
13 arch/mips/ralink/malta-amon.c | 81 +++++++++
14 arch/mips/ralink/mt7621.c | 186 ++++++++++++++++++++
15 7 files changed, 590 insertions(+), 1 deletion(-)
16 create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
17 create mode 100644 arch/mips/ralink/irq-gic.c
18 create mode 100644 arch/mips/ralink/malta-amon.c
19 create mode 100644 arch/mips/ralink/mt7621.c
22 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
25 + * This program is free software; you can redistribute it and/or modify it
26 + * under the terms of the GNU General Public License version 2 as published
27 + * by the Free Software Foundation.
29 + * Parts of this file are based on Ralink's 2.6.21 BSP
31 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
32 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
33 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
36 +#ifndef _MT7621_REGS_H_
37 +#define _MT7621_REGS_H_
39 +#define MT7621_SYSC_BASE 0x1E000000
41 +#define SYSC_REG_CHIP_NAME0 0x00
42 +#define SYSC_REG_CHIP_NAME1 0x04
43 +#define SYSC_REG_CHIP_REV 0x0c
44 +#define SYSC_REG_SYSTEM_CONFIG0 0x10
45 +#define SYSC_REG_SYSTEM_CONFIG1 0x14
47 +#define CHIP_REV_PKG_MASK 0x1
48 +#define CHIP_REV_PKG_SHIFT 16
49 +#define CHIP_REV_VER_MASK 0xf
50 +#define CHIP_REV_VER_SHIFT 8
51 +#define CHIP_REV_ECO_MASK 0xf
53 +#define MT7621_DRAM_BASE 0x0
54 +#define MT7621_DDR2_SIZE_MIN 32
55 +#define MT7621_DDR2_SIZE_MAX 256
57 +#define MT7621_CHIP_NAME0 0x3637544D
58 +#define MT7621_CHIP_NAME1 0x20203132
60 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
63 --- a/arch/mips/ralink/Kconfig
64 +++ b/arch/mips/ralink/Kconfig
71 + depends on !SOC_MT7621
74 bool "Systick Clockevent source"
75 depends on SOC_RT305X || SOC_MT7620
76 @@ -35,6 +40,15 @@ choice
77 select USB_ARCH_HAS_EHCI
82 + select MIPS_CPU_SCACHE
83 + select SYS_SUPPORTS_MULTITHREADING
84 + select SYS_SUPPORTS_SMP
85 + select SYS_SUPPORTS_MIPS_CMP
92 @@ -62,6 +76,10 @@ choice
93 bool "MT7620A eval kit"
96 + config DTB_MT7621_EVAL
97 + bool "MT7621 eval kit"
98 + depends on SOC_MT7621
103 --- a/arch/mips/ralink/Makefile
104 +++ b/arch/mips/ralink/Makefile
106 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
107 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
109 -obj-y := prom.o of.o reset.o clk.o irq.o timer.o
110 +obj-y := prom.o of.o reset.o clk.o timer.o
112 +obj-$(CONFIG_IRQ_INTC) += irq.o
113 +obj-$(CONFIG_IRQ_GIC) += irq-gic.o
114 +obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
116 obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
118 @@ -16,6 +20,7 @@ obj-$(CONFIG_SOC_RT288X) += rt288x.o
119 obj-$(CONFIG_SOC_RT305X) += rt305x.o
120 obj-$(CONFIG_SOC_RT3883) += rt3883.o
121 obj-$(CONFIG_SOC_MT7620) += mt7620.o
122 +obj-$(CONFIG_SOC_MT7621) += mt7621.o
124 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
126 --- a/arch/mips/ralink/Platform
127 +++ b/arch/mips/ralink/Platform
128 @@ -26,3 +26,10 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
131 load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
132 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
137 +load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
138 +cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
140 +++ b/arch/mips/ralink/irq-gic.c
142 +#include <linux/init.h>
143 +#include <linux/sched.h>
144 +#include <linux/slab.h>
145 +#include <linux/interrupt.h>
146 +#include <linux/kernel_stat.h>
147 +#include <linux/hardirq.h>
148 +#include <linux/preempt.h>
149 +#include <linux/irqdomain.h>
150 +#include <linux/of_platform.h>
151 +#include <linux/of_address.h>
152 +#include <linux/of_irq.h>
154 +#include <asm/irq_cpu.h>
155 +#include <asm/mipsregs.h>
157 +#include <asm/irq.h>
158 +#include <asm/setup.h>
160 +#include <asm/gic.h>
161 +#include <asm/gcmpregs.h>
163 +#include <asm/mach-ralink/mt7621.h>
165 +static unsigned long _gcmp_base;
166 +static int gic_resched_int_base = 56;
167 +static int gic_call_int_base = 60;
168 +static struct irq_chip *irq_gic;
170 +#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
171 +#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
173 +static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
174 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //0
175 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
177 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //FE
178 + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //PCIE0
180 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
181 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
182 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
183 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //10
184 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
185 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
186 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
189 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
190 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
191 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
192 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
193 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //20
194 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
195 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
197 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
198 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //25
199 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
200 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
201 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
202 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
203 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },//30
204 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
207 +static struct gic_intr_map ipi_intr_map[8] = {
208 + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
209 + { 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
210 + { 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
211 + { 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
212 + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
213 + { 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
214 + { 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
215 + { 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
219 +ipi_resched_interrupt(int irq, void *dev_id)
223 + return IRQ_HANDLED;
227 +ipi_call_interrupt(int irq, void *dev_id)
229 + smp_call_function_interrupt();
231 + return IRQ_HANDLED;
234 +static struct irqaction irq_resched = {
235 + .handler = ipi_resched_interrupt,
236 + .flags = IRQF_DISABLED|IRQF_PERCPU,
237 + .name = "ipi resched"
240 +static struct irqaction irq_call = {
241 + .handler = ipi_call_interrupt,
242 + .flags = IRQF_DISABLED|IRQF_PERCPU,
247 +gic_irq_ack(struct irq_data *d)
249 + int irq = (d->irq - gic_irq_base);
251 + GIC_CLR_INTR_MASK(irq);
253 + if (gic_irq_flags[irq] & GIC_TRIG_EDGE)
254 + GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
258 +gic_finish_irq(struct irq_data *d)
260 + GIC_SET_INTR_MASK(d->irq - gic_irq_base);
264 +gic_platform_init(int irqs, struct irq_chip *irq_controller)
266 + irq_gic = irq_controller;
270 +vi_gic_irqdispatch(void)
272 + int irq = gic_get_int();
275 + do_IRQ(MIPS_GIC_IRQ_BASE + irq);
279 +vi_timer_irqdispatch(void)
281 + do_IRQ(cp0_compare_irq);
285 +plat_ipi_call_int_xlate(unsigned int cpu)
287 + return GIC_CALL_INT(cpu);
291 +plat_ipi_resched_int_xlate(unsigned int cpu)
293 + return GIC_RESCHED_INT(cpu);
297 +plat_irq_dispatch(void)
299 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
301 + if (pending & CAUSEF_IP7)
302 + do_IRQ(cp0_compare_irq);
303 + else if (pending & (CAUSEF_IP4 | CAUSEF_IP3))
304 + vi_gic_irqdispatch();
306 + spurious_interrupt();
309 +unsigned int __cpuinit
310 +get_c0_compare_int(void)
312 + return CP0_LEGACY_COMPARE_IRQ;
316 +gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
318 + irq_set_chip_and_handler(irq, irq_gic, handle_percpu_irq);
323 +static const struct irq_domain_ops irq_domain_ops = {
324 + .xlate = irq_domain_xlate_onecell,
329 +of_gic_init(struct device_node *node,
330 + struct device_node *parent)
332 + struct irq_domain *domain;
333 + struct resource gcmp = { 0 }, gic = { 0 };
334 + unsigned int gic_rev;
337 + if (of_address_to_resource(node, 0, &gic))
338 + panic("Failed to get gic memory range");
339 + if (request_mem_region(gic.start, resource_size(&gic),
341 + panic("Failed to request gic memory");
342 + if (of_address_to_resource(node, 2, &gcmp))
343 + panic("Failed to get gic memory range");
344 + if (request_mem_region(gcmp.start, resource_size(&gcmp),
346 + panic("Failed to request gcmp memory");
348 + _gcmp_base = (unsigned long) ioremap_nocache(gcmp.start, resource_size(&gcmp));
350 + panic("Failed to remap gcmp memory\n");
352 + if ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) != gcmp.start)
353 + panic("Failed to find gcmp core\n");
355 + /* tell the gcmp where to find the gic */
356 + GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
358 + if (cpu_has_vint) {
359 + set_vi_handler(3, vi_gic_irqdispatch);
360 + set_vi_handler(4, vi_gic_irqdispatch);
361 + set_vi_handler(7, vi_timer_irqdispatch);
364 + memcpy(&gic_intr_map[gic_resched_int_base], ipi_intr_map, sizeof(ipi_intr_map));
365 + gic_init(gic.start, resource_size(&gic), gic_intr_map,
366 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
368 + GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
369 + pr_info("gic: revision %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);
371 + domain = irq_domain_add_legacy(node, GIC_NUM_INTRS, MIPS_GIC_IRQ_BASE,
372 + 0, &irq_domain_ops, NULL);
374 + panic("Failed to add irqdomain");
376 + for (i = 0; i < NR_CPUS; i++) {
377 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
378 + setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
381 + change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
386 +static struct of_device_id __initdata of_irq_ids[] = {
387 + { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
388 + { .compatible = "ralink,mt7621-gic", .data = of_gic_init },
395 + of_irq_init(of_irq_ids);
398 +++ b/arch/mips/ralink/malta-amon.c
401 + * Copyright (C) 2007 MIPS Technologies, Inc.
402 + * All rights reserved.
404 + * This program is free software; you can distribute it and/or modify it
405 + * under the terms of the GNU General Public License (Version 2) as
406 + * published by the Free Software Foundation.
408 + * This program is distributed in the hope it will be useful, but WITHOUT
409 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
410 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
411 + * for more details.
413 + * You should have received a copy of the GNU General Public License along
414 + * with this program; if not, write to the Free Software Foundation, Inc.,
415 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
417 + * Arbitrary Monitor interface
420 +#include <linux/kernel.h>
421 +#include <linux/init.h>
422 +#include <linux/smp.h>
424 +#include <asm/addrspace.h>
425 +#include <asm/mips-boards/launch.h>
426 +#include <asm/mipsmtregs.h>
428 +int amon_cpu_avail(int cpu)
430 + struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
432 + if (cpu < 0 || cpu >= NCPULAUNCH) {
433 + pr_debug("avail: cpu%d is out of range\n", cpu);
438 + if (!(launch->flags & LAUNCH_FREADY)) {
439 + pr_debug("avail: cpu%d is not ready\n", cpu);
442 + if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
443 + pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
450 +void amon_cpu_start(int cpu,
451 + unsigned long pc, unsigned long sp,
452 + unsigned long gp, unsigned long a0)
454 + volatile struct cpulaunch *launch =
455 + (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
457 + if (!amon_cpu_avail(cpu))
459 + if (cpu == smp_processor_id()) {
460 + pr_debug("launch: I am cpu%d!\n", cpu);
465 + pr_debug("launch: starting cpu%d\n", cpu);
472 + smp_wmb(); /* Target must see parameters before go */
473 + launch->flags |= LAUNCH_FGO;
474 + smp_wmb(); /* Target must see go before we poll */
476 + while ((launch->flags & LAUNCH_FGONE) == 0)
478 + smp_rmb(); /* Target will be updating flags soon */
479 + pr_debug("launch: cpu%d gone!\n", cpu);
482 +++ b/arch/mips/ralink/mt7621.c
485 + * This program is free software; you can redistribute it and/or modify it
486 + * under the terms of the GNU General Public License version 2 as published
487 + * by the Free Software Foundation.
489 + * Parts of this file are based on Ralink's 2.6.21 BSP
491 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
492 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
493 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
496 +#include <linux/kernel.h>
497 +#include <linux/init.h>
498 +#include <linux/module.h>
499 +#include <asm/gcmpregs.h>
501 +#include <asm/mipsregs.h>
502 +#include <asm/mach-ralink/ralink_regs.h>
503 +#include <asm/mach-ralink/mt7621.h>
509 +#define SYSC_REG_SYSCFG 0x10
510 +#define SYSC_REG_CPLL_CLKCFG0 0x2c
511 +#define SYSC_REG_CUR_CLK_STS 0x44
512 +#define CPU_CLK_SEL (BIT(30) | BIT(31))
514 +#define MT7621_GPIO_MODE_UART1 1
515 +#define MT7621_GPIO_MODE_I2C 2
516 +#define MT7621_GPIO_MODE_UART2 3
517 +#define MT7621_GPIO_MODE_UART3 5
518 +#define MT7621_GPIO_MODE_JTAG 7
519 +#define MT7621_GPIO_MODE_WDT_MASK 0x3
520 +#define MT7621_GPIO_MODE_WDT_SHIFT 8
521 +#define MT7621_GPIO_MODE_WDT_GPIO 1
522 +#define MT7621_GPIO_MODE_PCIE_RST 0
523 +#define MT7621_GPIO_MODE_PCIE_REF 2
524 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3
525 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10
526 +#define MT7621_GPIO_MODE_PCIE_GPIO 1
527 +#define MT7621_GPIO_MODE_MDIO 12
528 +#define MT7621_GPIO_MODE_RGMII1 14
529 +#define MT7621_GPIO_MODE_RGMII2 15
530 +#define MT7621_GPIO_MODE_SPI_MASK 0x3
531 +#define MT7621_GPIO_MODE_SPI_SHIFT 16
532 +#define MT7621_GPIO_MODE_SPI_GPIO 1
533 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
534 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
535 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1
537 +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
538 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
539 +static struct rt2880_pmx_func uart3_grp[] = { FUNC("uart3", 0, 5, 4) };
540 +static struct rt2880_pmx_func uart2_grp[] = { FUNC("uart2", 0, 9, 4) };
541 +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
542 +static struct rt2880_pmx_func wdt_grp[] = {
543 + FUNC("wdt rst", 0, 18, 1),
544 + FUNC("wdt refclk", 2, 18, 1),
546 +static struct rt2880_pmx_func pcie_rst_grp[] = {
547 + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
548 + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
550 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
551 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
552 +static struct rt2880_pmx_func spi_grp[] = {
553 + FUNC("spi", 0, 34, 7),
554 + FUNC("nand", 2, 34, 8),
556 +static struct rt2880_pmx_func sdhci_grp[] = {
557 + FUNC("sdhci", 0, 41, 8),
558 + FUNC("nand", 2, 41, 8),
560 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
562 +static struct rt2880_pmx_group mt7621_pinmux_data[] = {
563 + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
564 + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
565 + GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
566 + GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
567 + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
568 + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
569 + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
570 + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
571 + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
572 + GRP("mdio", mdio_grp, 1, MT7621_GPIO_MODE_MDIO),
573 + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
574 + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
575 + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
576 + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
577 + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
578 + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
582 +void __init ralink_clk_init(void)
587 + u32 clk_sts, syscfg;
588 + u8 clk_sel = 0, xtal_mode;
591 + if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
596 + clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
597 + cpu_fdiv = ((clk_sts >> 8) & 0x1F);
598 + cpu_ffrac = (clk_sts & 0x1F);
599 + cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
600 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
604 + fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
605 + syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
606 + xtal_mode = (syscfg >> 6) & 0x7;
607 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
608 + if(xtal_mode >= 6) { //25Mhz Xtal
609 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
610 + cpu_clk = 25 * fbdiv * 1000 * 1000;
611 + } else if(xtal_mode >=3) { //40Mhz Xtal
612 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
613 + cpu_clk = 40 * fbdiv * 1000 * 1000;
614 + } else { // 20Mhz Xtal
615 + printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
616 + cpu_clk = 20 * fbdiv * 1000 * 1000;
620 + cpu_clk = 880000000;
621 + ralink_clk_add("cpu", cpu_clk);
622 + ralink_clk_add("1e000b00.spi", 50000000);
623 + ralink_clk_add("1e000c00.uartlite", 50000000);
626 +void __init ralink_of_remap(void)
628 + rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
629 + rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
631 + if (!rt_sysc_membase || !rt_memc_membase)
632 + panic("Failed to remap core resources");
635 +void prom_soc_init(struct ralink_soc_info *soc_info)
637 + void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
638 + unsigned char *name = NULL;
643 + n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
644 + n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
646 + if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
648 + soc_info->compatible = "mtk,mt7621-soc";
650 + panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
653 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
655 + snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
656 + "Mediatek %s ver:%u eco:%u",
658 + (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
659 + (rev & CHIP_REV_ECO_MASK));
661 + soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
662 + soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
663 + soc_info->mem_base = MT7621_DRAM_BASE;
665 + rt2880_pinmux_data = mt7621_pinmux_data;
667 + if (register_cmp_smp_ops())
668 + panic("failed to register_vsmp_smp_ops()");