1 From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
6 Add support for Ralink FE and ESW.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 20 files changed, 4606 insertions(+)
31 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32 create mode 100644 drivers/net/ethernet/ralink/Kconfig
33 create mode 100644 drivers/net/ethernet/ralink/Makefile
34 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38 create mode 100644 drivers/net/ethernet/ralink/mdio.c
39 create mode 100644 drivers/net/ethernet/ralink/mdio.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
50 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
53 + * Ralink RT305x SoC platform device registration
55 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
57 + * This program is free software; you can redistribute it and/or modify it
58 + * under the terms of the GNU General Public License version 2 as published
59 + * by the Free Software Foundation.
62 +#ifndef _RT305X_ESW_PLATFORM_H
63 +#define _RT305X_ESW_PLATFORM_H
66 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
67 + RT305X_ESW_VLAN_CONFIG_LLLLW,
68 + RT305X_ESW_VLAN_CONFIG_WLLLL,
71 +struct rt305x_esw_platform_data
74 + u32 reg_initval_fct2;
75 + u32 reg_initval_fpa2;
78 +#endif /* _RT305X_ESW_PLATFORM_H */
79 --- a/arch/mips/ralink/rt305x.c
80 +++ b/arch/mips/ralink/rt305x.c
81 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
84 ralink_clk_add("cpu", cpu_rate);
85 + ralink_clk_add("sys", sys_rate);
86 ralink_clk_add("10000b00.spi", sys_rate);
87 ralink_clk_add("10000100.timer", wdt_rate);
88 ralink_clk_add("10000120.watchdog", wdt_rate);
89 --- a/drivers/net/ethernet/Kconfig
90 +++ b/drivers/net/ethernet/Kconfig
91 @@ -135,6 +135,7 @@ config ETHOC
92 source "drivers/net/ethernet/packetengines/Kconfig"
93 source "drivers/net/ethernet/pasemi/Kconfig"
94 source "drivers/net/ethernet/qlogic/Kconfig"
95 +source "drivers/net/ethernet/ralink/Kconfig"
96 source "drivers/net/ethernet/realtek/Kconfig"
97 source "drivers/net/ethernet/renesas/Kconfig"
98 source "drivers/net/ethernet/rdc/Kconfig"
99 --- a/drivers/net/ethernet/Makefile
100 +++ b/drivers/net/ethernet/Makefile
101 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
102 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
103 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
104 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
105 +obj-$(CONFIG_NET_RALINK) += ralink/
106 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
107 obj-$(CONFIG_SH_ETH) += renesas/
108 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
110 +++ b/drivers/net/ethernet/ralink/Kconfig
113 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
116 + This driver supports the ethernet mac inside the ralink wisocs
120 +config NET_RALINK_MDIO
121 + def_bool NET_RALINK
122 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
125 +config NET_RALINK_MDIO_RT2880
126 + def_bool NET_RALINK
127 + depends on (SOC_RT288X || SOC_RT3883)
128 + select NET_RALINK_MDIO
130 +config NET_RALINK_ESW_RT3052
131 + def_bool NET_RALINK
132 + depends on SOC_RT305X
136 +config NET_RALINK_GSW_MT7620
137 + def_bool NET_RALINK
138 + depends on SOC_MT7620
140 + select NET_RALINK_MDIO
145 +++ b/drivers/net/ethernet/ralink/Makefile
148 +# Makefile for the Ralink SoCs built-in ethernet macs
151 +ralink-eth-y += ralink_soc_eth.o
153 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
154 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
156 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
157 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
159 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
160 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
161 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
162 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
164 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
166 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
169 + * This program is free software; you can redistribute it and/or modify
170 + * it under the terms of the GNU General Public License as published by
171 + * the Free Software Foundation; version 2 of the License
173 + * This program is distributed in the hope that it will be useful,
174 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
175 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
176 + * GNU General Public License for more details.
178 + * You should have received a copy of the GNU General Public License
179 + * along with this program; if not, write to the Free Software
180 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
182 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
185 +#include <linux/module.h>
186 +#include <linux/kernel.h>
187 +#include <linux/types.h>
188 +#include <linux/dma-mapping.h>
189 +#include <linux/init.h>
190 +#include <linux/skbuff.h>
191 +#include <linux/etherdevice.h>
192 +#include <linux/ethtool.h>
193 +#include <linux/platform_device.h>
194 +#include <linux/of_device.h>
195 +#include <linux/clk.h>
196 +#include <linux/of_net.h>
197 +#include <linux/of_mdio.h>
199 +#include <asm/mach-ralink/ralink_regs.h>
201 +#include "ralink_soc_eth.h"
203 +#include <linux/ioport.h>
204 +#include <linux/switch.h>
205 +#include <linux/mii.h>
207 +#include <ralink_regs.h>
208 +#include <asm/mach-ralink/rt305x.h>
209 +#include <asm/mach-ralink/rt305x_esw_platform.h>
212 + * HW limitations for this switch:
213 + * - No large frame support (PKT_MAX_LEN at most 1536)
214 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
215 + * though this might be possible using the undocumented PPE.
218 +#define RT305X_ESW_REG_ISR 0x00
219 +#define RT305X_ESW_REG_IMR 0x04
220 +#define RT305X_ESW_REG_FCT0 0x08
221 +#define RT305X_ESW_REG_PFC1 0x14
222 +#define RT305X_ESW_REG_ATS 0x24
223 +#define RT305X_ESW_REG_ATS0 0x28
224 +#define RT305X_ESW_REG_ATS1 0x2c
225 +#define RT305X_ESW_REG_ATS2 0x30
226 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
227 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
228 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
229 +#define RT305X_ESW_REG_POA 0x80
230 +#define RT305X_ESW_REG_FPA 0x84
231 +#define RT305X_ESW_REG_SOCPC 0x8c
232 +#define RT305X_ESW_REG_POC0 0x90
233 +#define RT305X_ESW_REG_POC1 0x94
234 +#define RT305X_ESW_REG_POC2 0x98
235 +#define RT305X_ESW_REG_SGC 0x9c
236 +#define RT305X_ESW_REG_STRT 0xa0
237 +#define RT305X_ESW_REG_PCR0 0xc0
238 +#define RT305X_ESW_REG_PCR1 0xc4
239 +#define RT305X_ESW_REG_FPA2 0xc8
240 +#define RT305X_ESW_REG_FCT2 0xcc
241 +#define RT305X_ESW_REG_SGC2 0xe4
242 +#define RT305X_ESW_REG_P0LED 0xa4
243 +#define RT305X_ESW_REG_P1LED 0xa8
244 +#define RT305X_ESW_REG_P2LED 0xac
245 +#define RT305X_ESW_REG_P3LED 0xb0
246 +#define RT305X_ESW_REG_P4LED 0xb4
247 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
248 +#define RT305X_ESW_REG_P1PC 0xec
249 +#define RT305X_ESW_REG_P2PC 0xf0
250 +#define RT305X_ESW_REG_P3PC 0xf4
251 +#define RT305X_ESW_REG_P4PC 0xf8
252 +#define RT305X_ESW_REG_P5PC 0xfc
254 +#define RT305X_ESW_LED_LINK 0
255 +#define RT305X_ESW_LED_100M 1
256 +#define RT305X_ESW_LED_DUPLEX 2
257 +#define RT305X_ESW_LED_ACTIVITY 3
258 +#define RT305X_ESW_LED_COLLISION 4
259 +#define RT305X_ESW_LED_LINKACT 5
260 +#define RT305X_ESW_LED_DUPLCOLL 6
261 +#define RT305X_ESW_LED_10MACT 7
262 +#define RT305X_ESW_LED_100MACT 8
263 +/* Additional led states not in datasheet: */
264 +#define RT305X_ESW_LED_BLINK 10
265 +#define RT305X_ESW_LED_ON 12
267 +#define RT305X_ESW_LINK_S 25
268 +#define RT305X_ESW_DUPLEX_S 9
269 +#define RT305X_ESW_SPD_S 0
271 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
272 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
273 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
275 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
277 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
278 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
280 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
281 +#define RT305X_ESW_PVIDC_PVID_S 12
283 +#define RT305X_ESW_VLANI_VID_M 0xfff
284 +#define RT305X_ESW_VLANI_VID_S 12
286 +#define RT305X_ESW_VMSC_MSC_M 0xff
287 +#define RT305X_ESW_VMSC_MSC_S 8
289 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
290 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
291 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
292 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
294 +#define RT305X_ESW_POC0_EN_BP_S 0
295 +#define RT305X_ESW_POC0_EN_FC_S 8
296 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
297 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
298 +#define RT305X_ESW_POC0_DIS_PORT_S 23
300 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
301 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
302 +#define RT305X_ESW_POC2_ENAGING_S 8
303 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
305 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
306 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
307 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
308 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
310 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
311 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
312 +#define RT305X_ESW_PFC1_EN_TOS_S 24
314 +#define RT305X_ESW_VLAN_NONE 0xfff
316 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
317 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
319 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
320 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
322 +#define RT305X_ESW_POA_LINK_MASK 0x1f
323 +#define RT305X_ESW_POA_LINK_SHIFT 25
325 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
326 +#define RT305X_ESW_PORT0 0
327 +#define RT305X_ESW_PORT1 1
328 +#define RT305X_ESW_PORT2 2
329 +#define RT305X_ESW_PORT3 3
330 +#define RT305X_ESW_PORT4 4
331 +#define RT305X_ESW_PORT5 5
332 +#define RT305X_ESW_PORT6 6
334 +#define RT305X_ESW_PORTS_NONE 0
336 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
337 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
338 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
340 +#define RT305X_ESW_PORTS_INTERNAL \
341 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
342 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
343 + BIT(RT305X_ESW_PORT4))
345 +#define RT305X_ESW_PORTS_NOCPU \
346 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
348 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
350 +#define RT305X_ESW_PORTS_ALL \
351 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
353 +#define RT305X_ESW_NUM_VLANS 16
354 +#define RT305X_ESW_NUM_VIDS 4096
355 +#define RT305X_ESW_NUM_PORTS 7
356 +#define RT305X_ESW_NUM_LANWAN 6
357 +#define RT305X_ESW_NUM_LEDS 5
359 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
360 +#define RT5350_EWS_REG_LED_POLARITY 0x168
361 +#define RT5350_RESET_EPHY BIT(24)
362 +#define SYSC_REG_RESET_CTRL 0x34
365 + /* Global attributes. */
366 + RT305X_ESW_ATTR_ENABLE_VLAN,
367 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
368 + RT305X_ESW_ATTR_BC_STATUS,
369 + RT305X_ESW_ATTR_LED_FREQ,
370 + /* Port attributes. */
371 + RT305X_ESW_ATTR_PORT_DISABLE,
372 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
373 + RT305X_ESW_ATTR_PORT_UNTAG,
374 + RT305X_ESW_ATTR_PORT_LED,
375 + RT305X_ESW_ATTR_PORT_LAN,
376 + RT305X_ESW_ATTR_PORT_RECV_BAD,
377 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
378 + RT5350_ESW_ATTR_PORT_TR_BAD,
379 + RT5350_ESW_ATTR_PORT_TR_GOOD,
396 + struct device *dev;
397 + void __iomem *base;
399 + const struct rt305x_esw_platform_data *pdata;
400 + /* Protects against concurrent register rmw operations. */
401 + spinlock_t reg_rw_lock;
403 + unsigned char port_map;
404 + unsigned int reg_initval_fct2;
405 + unsigned int reg_initval_fpa2;
406 + unsigned int reg_led_polarity;
409 + struct switch_dev swdev;
410 + bool global_vlan_enable;
411 + bool alt_vlan_disable;
412 + int bc_storm_protect;
414 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
415 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
419 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
421 + __raw_writel(val, esw->base + reg);
424 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
426 + return __raw_readl(esw->base + reg);
429 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
434 + t = __raw_readl(esw->base + reg) & ~mask;
435 + __raw_writel(t | val, esw->base + reg);
438 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
441 + unsigned long flags;
443 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
444 + esw_rmw_raw(esw, reg, mask, val);
445 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
448 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
451 + unsigned long t_start = jiffies;
455 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
456 + RT305X_ESW_PCR1_WT_DONE))
458 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
464 + write_data &= 0xffff;
466 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
467 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
468 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
469 + RT305X_ESW_REG_PCR0);
473 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
474 + RT305X_ESW_PCR1_WT_DONE)
477 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
484 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
488 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
493 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
494 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
495 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
500 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
504 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
506 + RT305X_ESW_REG_VLANI(vlan / 2),
507 + RT305X_ESW_VLANI_VID_M << s,
508 + (vid & RT305X_ESW_VLANI_VID_M) << s);
511 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
515 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
516 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
517 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
520 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
524 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
526 + RT305X_ESW_REG_PVIDC(port / 2),
527 + RT305X_ESW_PVIDC_PVID_M << s,
528 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
531 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
535 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
536 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
537 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
542 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
546 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
548 + RT305X_ESW_REG_VMSC(vlan / 4),
549 + RT305X_ESW_VMSC_MSC_M << s,
550 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
553 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
556 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
557 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
558 + RT305X_ESW_POC0_DIS_PORT_M;
561 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
564 + unsigned enable_mask;
568 + old_mask = esw_get_port_disable(esw);
569 + changed = old_mask ^ disable_mask;
570 + enable_mask = old_mask & disable_mask;
572 + /* enable before writing to MII */
573 + esw_rmw(esw, RT305X_ESW_REG_POC0,
574 + (RT305X_ESW_POC0_DIS_PORT_M <<
575 + RT305X_ESW_POC0_DIS_PORT_S),
576 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
578 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
579 + if (!(changed & (1 << i)))
581 + if (disable_mask & (1 << i)) {
583 + rt305x_mii_write(esw, i, MII_BMCR,
587 + rt305x_mii_write(esw, i, MII_BMCR,
595 + /* disable after writing to MII */
596 + esw_rmw(esw, RT305X_ESW_REG_POC0,
597 + (RT305X_ESW_POC0_DIS_PORT_M <<
598 + RT305X_ESW_POC0_DIS_PORT_S),
599 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
602 +static void esw_set_gsc(struct rt305x_esw *esw)
604 + esw_rmw(esw, RT305X_ESW_REG_SGC,
605 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
606 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
607 + esw_rmw(esw, RT305X_ESW_REG_SGC,
608 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
609 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
612 +static int esw_apply_config(struct switch_dev *dev);
614 +static void esw_hw_init(struct rt305x_esw *esw)
617 + u8 port_disable = 0;
618 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
620 + /* vodoo from original driver */
621 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
622 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
623 + /* Port priority 1 for all ports, vlan enabled. */
624 + esw_w32(esw, 0x00005555 |
625 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
626 + RT305X_ESW_REG_PFC1);
628 + /* Enable Back Pressure, and Flow Control */
630 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
631 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
632 + RT305X_ESW_REG_POC0);
634 + /* Enable Aging, and VLAN TAG removal */
636 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
637 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
638 + RT305X_ESW_REG_POC2);
640 + if (esw->reg_initval_fct2)
641 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
643 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
646 + * 300s aging timer, max packet len 1536, broadcast storm prevention
647 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
648 + * pressure jam, GMII disable was_transmit, back pressure disabled,
649 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
652 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
654 + /* Setup SoC Port control register */
656 + (RT305X_ESW_SOCPC_CRC_PADDING |
657 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
658 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
659 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
660 + RT305X_ESW_REG_SOCPC);
662 + if (esw->reg_initval_fpa2)
663 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
665 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
666 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
668 + /* Force Link/Activity on ports */
669 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
670 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
671 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
672 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
673 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
675 + /* Copy disabled port configuration from bootloader setup */
676 + port_disable = esw_get_port_disable(esw);
677 + for (i = 0; i < 6; i++)
678 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
680 + if (soc_is_rt3352()) {
682 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
683 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
684 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
686 + rt305x_mii_write(esw, 0, 31, 0x8000);
687 + for (i = 0; i < 5; i++) {
688 + if (esw->ports[i].disable) {
689 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
691 + rt305x_mii_write(esw, i, MII_BMCR,
696 + /* TX10 waveform coefficient LSB=0 disable PHY */
697 + rt305x_mii_write(esw, i, 26, 0x1601);
698 + /* TX100/TX10 AD/DA current bias */
699 + rt305x_mii_write(esw, i, 29, 0x7016);
700 + /* TX100 slew rate control */
701 + rt305x_mii_write(esw, i, 30, 0x0038);
704 + /* select global register */
705 + rt305x_mii_write(esw, 0, 31, 0x0);
706 + /* enlarge agcsel threshold 3 and threshold 2 */
707 + rt305x_mii_write(esw, 0, 1, 0x4a40);
708 + /* enlarge agcsel threshold 5 and threshold 4 */
709 + rt305x_mii_write(esw, 0, 2, 0x6254);
710 + /* enlarge agcsel threshold */
711 + rt305x_mii_write(esw, 0, 3, 0xa17f);
712 + rt305x_mii_write(esw, 0,12, 0x7eaa);
713 + /* longer TP_IDL tail length */
714 + rt305x_mii_write(esw, 0, 14, 0x65);
715 + /* increased squelch pulse count threshold. */
716 + rt305x_mii_write(esw, 0, 16, 0x0684);
717 + /* set TX10 signal amplitude threshold to minimum */
718 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
719 + /* set squelch amplitude to higher threshold */
720 + rt305x_mii_write(esw, 0, 18, 0x40ba);
721 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
722 + rt305x_mii_write(esw, 0, 22, 0x253f);
723 + /* set PLL/Receive bias current are calibrated */
724 + rt305x_mii_write(esw, 0, 27, 0x2fda);
725 + /* change PLL/Receive bias current to internal(RT3350) */
726 + rt305x_mii_write(esw, 0, 28, 0xc410);
727 + /* change PLL bias current to internal(RT3052_MP3) */
728 + rt305x_mii_write(esw, 0, 29, 0x598b);
729 + /* select local register */
730 + rt305x_mii_write(esw, 0, 31, 0x8000);
731 + } else if (soc_is_rt5350()) {
733 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
734 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
735 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
737 + /* set the led polarity */
738 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
740 + /* local registers */
741 + rt305x_mii_write(esw, 0, 31, 0x8000);
742 + for (i = 0; i < 5; i++) {
743 + if (esw->ports[i].disable) {
744 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
746 + rt305x_mii_write(esw, i, MII_BMCR,
751 + /* TX10 waveform coefficient LSB=0 disable PHY */
752 + rt305x_mii_write(esw, i, 26, 0x1601);
753 + /* TX100/TX10 AD/DA current bias */
754 + rt305x_mii_write(esw, i, 29, 0x7015);
755 + /* TX100 slew rate control */
756 + rt305x_mii_write(esw, i, 30, 0x0038);
759 + /* global registers */
760 + rt305x_mii_write(esw, 0, 31, 0x0);
761 + /* enlarge agcsel threshold 3 and threshold 2 */
762 + rt305x_mii_write(esw, 0, 1, 0x4a40);
763 + /* enlarge agcsel threshold 5 and threshold 4 */
764 + rt305x_mii_write(esw, 0, 2, 0x6254);
765 + /* enlarge agcsel threshold 6 */
766 + rt305x_mii_write(esw, 0, 3, 0xa17f);
767 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
768 + /* longer TP_IDL tail length */
769 + rt305x_mii_write(esw, 0, 14, 0x65);
770 + /* increased squelch pulse count threshold. */
771 + rt305x_mii_write(esw, 0, 16, 0x0684);
772 + /* set TX10 signal amplitude threshold to minimum */
773 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
774 + /* set squelch amplitude to higher threshold */
775 + rt305x_mii_write(esw, 0, 18, 0x40ba);
776 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
777 + rt305x_mii_write(esw, 0, 22, 0x253f);
778 + /* set PLL/Receive bias current are calibrated */
779 + rt305x_mii_write(esw, 0, 27, 0x2fda);
780 + /* change PLL/Receive bias current to internal(RT3350) */
781 + rt305x_mii_write(esw, 0, 28, 0xc410);
782 + /* change PLL bias current to internal(RT3052_MP3) */
783 + rt305x_mii_write(esw, 0, 29, 0x598b);
784 + /* select local register */
785 + rt305x_mii_write(esw, 0, 31, 0x8000);
787 + rt305x_mii_write(esw, 0, 31, 0x8000);
788 + for (i = 0; i < 5; i++) {
789 + if (esw->ports[i].disable) {
790 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
792 + rt305x_mii_write(esw, i, MII_BMCR,
797 + /* TX10 waveform coefficient */
798 + rt305x_mii_write(esw, i, 26, 0x1601);
799 + /* TX100/TX10 AD/DA current bias */
800 + rt305x_mii_write(esw, i, 29, 0x7058);
801 + /* TX100 slew rate control */
802 + rt305x_mii_write(esw, i, 30, 0x0018);
806 + /* select global register */
807 + rt305x_mii_write(esw, 0, 31, 0x0);
808 + /* tune TP_IDL tail and head waveform */
809 + rt305x_mii_write(esw, 0, 22, 0x052f);
810 + /* set TX10 signal amplitude threshold to minimum */
811 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
812 + /* set squelch amplitude to higher threshold */
813 + rt305x_mii_write(esw, 0, 18, 0x40ba);
814 + /* longer TP_IDL tail length */
815 + rt305x_mii_write(esw, 0, 14, 0x65);
816 + /* select local register */
817 + rt305x_mii_write(esw, 0, 31, 0x8000);
821 + port_map = esw->port_map;
823 + port_map = RT305X_ESW_PMAP_LLLLLL;
826 + * Unused HW feature, but still nice to be consistent here...
827 + * This is also exported to userspace ('lan' attribute) so it's
828 + * conveniently usable to decide which ports go into the wan vlan by
831 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
832 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
833 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
835 + /* make the switch leds blink */
836 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
837 + esw->ports[i].led = 0x05;
839 + /* Apply the empty config. */
840 + esw_apply_config(&esw->swdev);
842 + /* Only unmask the port change interrupt */
843 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
846 +static irqreturn_t esw_interrupt(int irq, void *_esw)
848 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
851 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
852 + if (status & RT305X_ESW_PORT_ST_CHG) {
853 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
854 + link >>= RT305X_ESW_POA_LINK_SHIFT;
855 + link &= RT305X_ESW_POA_LINK_MASK;
856 + dev_info(esw->dev, "link changed 0x%02X\n", link);
858 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
860 + return IRQ_HANDLED;
863 +static int esw_apply_config(struct switch_dev *dev)
865 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
872 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
874 + if (esw->global_vlan_enable) {
875 + vid = esw->vlans[i].vid;
876 + vmsc = esw->vlans[i].ports;
878 + vid = RT305X_ESW_VLAN_NONE;
879 + vmsc = RT305X_ESW_PORTS_NONE;
881 + esw_set_vlan_id(esw, i, vid);
882 + esw_set_vmsc(esw, i, vmsc);
885 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
887 + disable |= esw->ports[i].disable << i;
888 + if (esw->global_vlan_enable) {
889 + doubletag |= esw->ports[i].doubletag << i;
891 + untag |= esw->ports[i].untag << i;
892 + pvid = esw->ports[i].pvid;
894 + int x = esw->alt_vlan_disable ? 0 : 1;
895 + doubletag |= x << i;
900 + esw_set_pvid(esw, i, pvid);
901 + if (i < RT305X_ESW_NUM_LEDS)
902 + esw_w32(esw, esw->ports[i].led,
903 + RT305X_ESW_REG_P0LED + 4*i);
907 + esw_set_port_disable(esw, disable);
908 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
909 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
910 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
911 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
912 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
913 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
914 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
915 + esw_rmw(esw, RT305X_ESW_REG_POC2,
916 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
917 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
919 + if (!esw->global_vlan_enable) {
921 + * Still need to put all ports into vlan 0 or they'll be
923 + * NOTE: vlan 0 is special, no vlan tag is prepended
925 + esw_set_vlan_id(esw, 0, 0);
926 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
932 +static int esw_reset_switch(struct switch_dev *dev)
934 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
936 + esw->global_vlan_enable = 0;
937 + memset(esw->ports, 0, sizeof(esw->ports));
938 + memset(esw->vlans, 0, sizeof(esw->vlans));
944 +static int esw_get_vlan_enable(struct switch_dev *dev,
945 + const struct switch_attr *attr,
946 + struct switch_val *val)
948 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
950 + val->value.i = esw->global_vlan_enable;
955 +static int esw_set_vlan_enable(struct switch_dev *dev,
956 + const struct switch_attr *attr,
957 + struct switch_val *val)
959 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
961 + esw->global_vlan_enable = val->value.i != 0;
966 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
967 + const struct switch_attr *attr,
968 + struct switch_val *val)
970 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
972 + val->value.i = esw->alt_vlan_disable;
977 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
978 + const struct switch_attr *attr,
979 + struct switch_val *val)
981 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
983 + esw->alt_vlan_disable = val->value.i != 0;
989 +rt305x_esw_set_bc_status(struct switch_dev *dev,
990 + const struct switch_attr *attr,
991 + struct switch_val *val)
993 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
995 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1001 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1002 + const struct switch_attr *attr,
1003 + struct switch_val *val)
1005 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1007 + val->value.i = esw->bc_storm_protect;
1013 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1014 + const struct switch_attr *attr,
1015 + struct switch_val *val)
1017 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1019 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1025 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1026 + const struct switch_attr *attr,
1027 + struct switch_val *val)
1029 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1031 + val->value.i = esw->led_frequency;
1036 +static int esw_get_port_link(struct switch_dev *dev,
1038 + struct switch_port_link *link)
1040 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1043 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1046 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1048 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1049 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1050 + if (port < RT305X_ESW_NUM_LEDS) {
1051 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1053 + if (port == RT305X_ESW_NUM_PORTS - 1)
1055 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1059 + link->speed = SWITCH_PORT_SPEED_10;
1062 + link->speed = SWITCH_PORT_SPEED_100;
1065 + case 3: /* forced gige speed can be 2 or 3 */
1066 + link->speed = SWITCH_PORT_SPEED_1000;
1069 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1076 +static int esw_get_port_bool(struct switch_dev *dev,
1077 + const struct switch_attr *attr,
1078 + struct switch_val *val)
1080 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1081 + int idx = val->port_vlan;
1082 + u32 x, reg, shift;
1084 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1087 + switch (attr->id) {
1088 + case RT305X_ESW_ATTR_PORT_DISABLE:
1089 + reg = RT305X_ESW_REG_POC0;
1090 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1092 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1093 + reg = RT305X_ESW_REG_SGC2;
1094 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1096 + case RT305X_ESW_ATTR_PORT_UNTAG:
1097 + reg = RT305X_ESW_REG_POC2;
1098 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1100 + case RT305X_ESW_ATTR_PORT_LAN:
1101 + reg = RT305X_ESW_REG_SGC2;
1102 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1103 + if (idx >= RT305X_ESW_NUM_LANWAN)
1110 + x = esw_r32(esw, reg);
1111 + val->value.i = (x >> (idx + shift)) & 1;
1116 +static int esw_set_port_bool(struct switch_dev *dev,
1117 + const struct switch_attr *attr,
1118 + struct switch_val *val)
1120 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1121 + int idx = val->port_vlan;
1123 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1124 + val->value.i < 0 || val->value.i > 1)
1127 + switch (attr->id) {
1128 + case RT305X_ESW_ATTR_PORT_DISABLE:
1129 + esw->ports[idx].disable = val->value.i;
1131 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1132 + esw->ports[idx].doubletag = val->value.i;
1134 + case RT305X_ESW_ATTR_PORT_UNTAG:
1135 + esw->ports[idx].untag = val->value.i;
1144 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1145 + const struct switch_attr *attr,
1146 + struct switch_val *val)
1148 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1149 + int idx = val->port_vlan;
1150 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1153 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1155 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1156 + val->value.i = (reg >> shift) & 0xffff;
1162 +esw_get_port_tr_badgood(struct switch_dev *dev,
1163 + const struct switch_attr *attr,
1164 + struct switch_val *val)
1166 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1168 + int idx = val->port_vlan;
1169 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1172 + if (!soc_is_rt5350())
1175 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1178 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1179 + val->value.i = (reg >> shift) & 0xffff;
1184 +static int esw_get_port_led(struct switch_dev *dev,
1185 + const struct switch_attr *attr,
1186 + struct switch_val *val)
1188 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1189 + int idx = val->port_vlan;
1191 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1192 + idx >= RT305X_ESW_NUM_LEDS)
1195 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1200 +static int esw_set_port_led(struct switch_dev *dev,
1201 + const struct switch_attr *attr,
1202 + struct switch_val *val)
1204 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1205 + int idx = val->port_vlan;
1207 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1210 + esw->ports[idx].led = val->value.i;
1215 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1217 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1219 + if (port >= RT305X_ESW_NUM_PORTS)
1222 + *val = esw_get_pvid(esw, port);
1227 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1229 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1231 + if (port >= RT305X_ESW_NUM_PORTS)
1234 + esw->ports[port].pvid = val;
1239 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1241 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1243 + int vlan_idx = -1;
1248 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1252 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1253 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1254 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1260 + if (vlan_idx == -1)
1263 + vmsc = esw_get_vmsc(esw, vlan_idx);
1264 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1266 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1267 + struct switch_port *p;
1268 + int port_mask = 1 << i;
1270 + if (!(vmsc & port_mask))
1273 + p = &val->value.ports[val->len++];
1275 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1278 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1284 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1286 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1288 + int vlan_idx = -1;
1291 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1292 + val->len > RT305X_ESW_NUM_PORTS)
1295 + /* one of the already defined vlans? */
1296 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1297 + if (esw->vlans[i].vid == val->port_vlan &&
1298 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1304 + /* select a free slot */
1305 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1306 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1310 + /* bail if all slots are in use */
1311 + if (vlan_idx == -1)
1314 + ports = RT305X_ESW_PORTS_NONE;
1315 + for (i = 0; i < val->len; i++) {
1316 + struct switch_port *p = &val->value.ports[i];
1317 + int port_mask = 1 << p->id;
1318 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1320 + if (p->id >= RT305X_ESW_NUM_PORTS)
1323 + ports |= port_mask;
1324 + esw->ports[p->id].untag = untagged;
1326 + esw->vlans[vlan_idx].ports = ports;
1327 + if (ports == RT305X_ESW_PORTS_NONE)
1328 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1330 + esw->vlans[vlan_idx].vid = val->port_vlan;
1335 +static const struct switch_attr esw_global[] = {
1337 + .type = SWITCH_TYPE_INT,
1338 + .name = "enable_vlan",
1339 + .description = "VLAN mode (1:enabled)",
1341 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1342 + .get = esw_get_vlan_enable,
1343 + .set = esw_set_vlan_enable,
1346 + .type = SWITCH_TYPE_INT,
1347 + .name = "alternate_vlan_disable",
1348 + .description = "Use en_vlan instead of doubletag to disable"
1351 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1352 + .get = esw_get_alt_vlan_disable,
1353 + .set = esw_set_alt_vlan_disable,
1356 + .type = SWITCH_TYPE_INT,
1357 + .name = "bc_storm_protect",
1358 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1360 + .id = RT305X_ESW_ATTR_BC_STATUS,
1361 + .get = rt305x_esw_get_bc_status,
1362 + .set = rt305x_esw_set_bc_status,
1365 + .type = SWITCH_TYPE_INT,
1366 + .name = "led_frequency",
1367 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1369 + .id = RT305X_ESW_ATTR_LED_FREQ,
1370 + .get = rt305x_esw_get_led_freq,
1371 + .set = rt305x_esw_set_led_freq,
1375 +static const struct switch_attr esw_port[] = {
1377 + .type = SWITCH_TYPE_INT,
1378 + .name = "disable",
1379 + .description = "Port state (1:disabled)",
1381 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1382 + .get = esw_get_port_bool,
1383 + .set = esw_set_port_bool,
1386 + .type = SWITCH_TYPE_INT,
1387 + .name = "doubletag",
1388 + .description = "Double tagging for incoming vlan packets "
1391 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1392 + .get = esw_get_port_bool,
1393 + .set = esw_set_port_bool,
1396 + .type = SWITCH_TYPE_INT,
1398 + .description = "Untag (1:strip outgoing vlan tag)",
1400 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1401 + .get = esw_get_port_bool,
1402 + .set = esw_set_port_bool,
1405 + .type = SWITCH_TYPE_INT,
1407 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1408 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1409 + " 8:100mact, 10:blink, 11:off, 12:on)",
1411 + .id = RT305X_ESW_ATTR_PORT_LED,
1412 + .get = esw_get_port_led,
1413 + .set = esw_set_port_led,
1416 + .type = SWITCH_TYPE_INT,
1418 + .description = "HW port group (0:wan, 1:lan)",
1420 + .id = RT305X_ESW_ATTR_PORT_LAN,
1421 + .get = esw_get_port_bool,
1424 + .type = SWITCH_TYPE_INT,
1425 + .name = "recv_bad",
1426 + .description = "Receive bad packet counter",
1427 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1428 + .get = esw_get_port_recv_badgood,
1431 + .type = SWITCH_TYPE_INT,
1432 + .name = "recv_good",
1433 + .description = "Receive good packet counter",
1434 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1435 + .get = esw_get_port_recv_badgood,
1438 + .type = SWITCH_TYPE_INT,
1441 + .description = "Transmit bad packet counter. rt5350 only",
1442 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1443 + .get = esw_get_port_tr_badgood,
1446 + .type = SWITCH_TYPE_INT,
1447 + .name = "tr_good",
1449 + .description = "Transmit good packet counter. rt5350 only",
1450 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1451 + .get = esw_get_port_tr_badgood,
1455 +static const struct switch_attr esw_vlan[] = {
1458 +static const struct switch_dev_ops esw_ops = {
1460 + .attr = esw_global,
1461 + .n_attr = ARRAY_SIZE(esw_global),
1465 + .n_attr = ARRAY_SIZE(esw_port),
1469 + .n_attr = ARRAY_SIZE(esw_vlan),
1471 + .get_vlan_ports = esw_get_vlan_ports,
1472 + .set_vlan_ports = esw_set_vlan_ports,
1473 + .get_port_pvid = esw_get_port_pvid,
1474 + .set_port_pvid = esw_set_port_pvid,
1475 + .get_port_link = esw_get_port_link,
1476 + .apply_config = esw_apply_config,
1477 + .reset_switch = esw_reset_switch,
1480 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1481 + /* All ports are LAN ports. */
1482 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1483 + .reg_initval_fct2 = 0x00d6500c,
1485 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1486 + * turbo mii off, rgmi 3.3v off
1488 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1490 + .reg_initval_fpa2 = 0x3f502b28,
1493 +static const struct of_device_id ralink_esw_match[] = {
1494 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1497 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1499 +static int esw_probe(struct platform_device *pdev)
1501 + struct device_node *np = pdev->dev.of_node;
1502 + const struct rt305x_esw_platform_data *pdata;
1503 + const __be32 *port_map, *reg_init;
1504 + struct rt305x_esw *esw;
1505 + struct switch_dev *swdev;
1506 + struct resource *res, *irq;
1509 + pdata = pdev->dev.platform_data;
1511 + const struct of_device_id *match;
1512 + match = of_match_device(ralink_esw_match, &pdev->dev);
1514 + pdata = (struct rt305x_esw_platform_data *) match->data;
1519 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521 + dev_err(&pdev->dev, "no memory resource found\n");
1525 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1527 + dev_err(&pdev->dev, "no irq resource found\n");
1531 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1533 + dev_err(&pdev->dev, "no memory for private data\n");
1537 + esw->dev = &pdev->dev;
1538 + esw->irq = irq->start;
1539 + esw->base = ioremap(res->start, resource_size(res));
1541 + dev_err(&pdev->dev, "ioremap failed\n");
1546 + port_map = of_get_property(np, "ralink,portmap", NULL);
1548 + esw->port_map = be32_to_cpu(*port_map);
1550 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1552 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1554 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1556 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1558 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1560 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1562 + swdev = &esw->swdev;
1563 + swdev->of_node = pdev->dev.of_node;
1564 + swdev->name = "rt305x-esw";
1565 + swdev->alias = "rt305x";
1566 + swdev->cpu_port = RT305X_ESW_PORT6;
1567 + swdev->ports = RT305X_ESW_NUM_PORTS;
1568 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1569 + swdev->ops = &esw_ops;
1571 + err = register_switch(swdev, NULL);
1573 + dev_err(&pdev->dev, "register_switch failed\n");
1577 + platform_set_drvdata(pdev, esw);
1579 + esw->pdata = pdata;
1580 + spin_lock_init(&esw->reg_rw_lock);
1584 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1585 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1586 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1591 + iounmap(esw->base);
1597 +static int esw_remove(struct platform_device *pdev)
1599 + struct rt305x_esw *esw;
1601 + esw = platform_get_drvdata(pdev);
1603 + unregister_switch(&esw->swdev);
1604 + platform_set_drvdata(pdev, NULL);
1605 + iounmap(esw->base);
1612 +static struct platform_driver esw_driver = {
1613 + .probe = esw_probe,
1614 + .remove = esw_remove,
1616 + .name = "rt305x-esw",
1617 + .owner = THIS_MODULE,
1618 + .of_match_table = ralink_esw_match,
1622 +int __init rtesw_init(void)
1624 + return platform_driver_register(&esw_driver);
1627 +void rtesw_exit(void)
1629 + platform_driver_unregister(&esw_driver);
1632 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1635 + * This program is free software; you can redistribute it and/or modify
1636 + * it under the terms of the GNU General Public License as published by
1637 + * the Free Software Foundation; version 2 of the License
1639 + * This program is distributed in the hope that it will be useful,
1640 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1641 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1642 + * GNU General Public License for more details.
1644 + * You should have received a copy of the GNU General Public License
1645 + * along with this program; if not, write to the Free Software
1646 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1648 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1651 +#ifndef _RALINK_ESW_RT3052_H__
1652 +#define _RALINK_ESW_RT3052_H__
1654 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1656 +int __init rtesw_init(void);
1657 +void rtesw_exit(void);
1661 +static inline int __init rtesw_init(void) { return 0; }
1662 +static inline void rtesw_exit(void) { }
1667 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1670 + * This program is free software; you can redistribute it and/or modify
1671 + * it under the terms of the GNU General Public License as published by
1672 + * the Free Software Foundation; version 2 of the License
1674 + * This program is distributed in the hope that it will be useful,
1675 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1676 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1677 + * GNU General Public License for more details.
1679 + * You should have received a copy of the GNU General Public License
1680 + * along with this program; if not, write to the Free Software
1681 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1683 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1686 +#include <linux/module.h>
1687 +#include <linux/kernel.h>
1688 +#include <linux/types.h>
1689 +#include <linux/dma-mapping.h>
1690 +#include <linux/init.h>
1691 +#include <linux/skbuff.h>
1692 +#include <linux/etherdevice.h>
1693 +#include <linux/ethtool.h>
1694 +#include <linux/platform_device.h>
1695 +#include <linux/of_device.h>
1696 +#include <linux/clk.h>
1697 +#include <linux/of_net.h>
1698 +#include <linux/of_mdio.h>
1699 +#include <linux/of_irq.h>
1700 +#include <linux/of_address.h>
1701 +#include <linux/switch.h>
1703 +#include <asm/mach-ralink/ralink_regs.h>
1705 +#include "ralink_soc_eth.h"
1707 +#include <linux/ioport.h>
1708 +#include <linux/switch.h>
1709 +#include <linux/mii.h>
1711 +#include <ralink_regs.h>
1712 +#include <asm/mach-ralink/mt7620.h>
1714 +#include "ralink_soc_eth.h"
1715 +#include "gsw_mt7620a.h"
1716 +#include "mt7530.h"
1719 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1721 +#define MT7620A_GSW_REG_PIAC 0x7004
1723 +#define GSW_NUM_VLANS 16
1724 +#define GSW_NUM_VIDS 4096
1725 +#define GSW_NUM_PORTS 7
1726 +#define GSW_PORT6 6
1728 +#define GSW_MDIO_ACCESS BIT(31)
1729 +#define GSW_MDIO_READ BIT(19)
1730 +#define GSW_MDIO_WRITE BIT(18)
1731 +#define GSW_MDIO_START BIT(16)
1732 +#define GSW_MDIO_ADDR_SHIFT 20
1733 +#define GSW_MDIO_REG_SHIFT 25
1735 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1736 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1737 +#define GSW_REG_SMACCR0 0x3fE4
1738 +#define GSW_REG_SMACCR1 0x3fE8
1739 +#define GSW_REG_CKGCR 0x3ff0
1741 +#define GSW_REG_IMR 0x7008
1742 +#define GSW_REG_ISR 0x700c
1744 +#define SYSC_REG_CFG1 0x14
1746 +#define PORT_IRQ_ST_CHG 0x7f
1748 +#define SYSCFG1 0x14
1750 +#define ESW_PHY_POLLING 0x7000
1752 +#define PMCR_IPG BIT(18)
1753 +#define PMCR_MAC_MODE BIT(16)
1754 +#define PMCR_FORCE BIT(15)
1755 +#define PMCR_TX_EN BIT(14)
1756 +#define PMCR_RX_EN BIT(13)
1757 +#define PMCR_BACKOFF BIT(9)
1758 +#define PMCR_BACKPRES BIT(8)
1759 +#define PMCR_RX_FC BIT(5)
1760 +#define PMCR_TX_FC BIT(4)
1761 +#define PMCR_SPEED(_x) (_x << 2)
1762 +#define PMCR_DUPLEX BIT(1)
1763 +#define PMCR_LINK BIT(0)
1765 +#define PHY_AN_EN BIT(31)
1766 +#define PHY_PRE_EN BIT(30)
1767 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1770 + /* Global attributes. */
1771 + GSW_ATTR_ENABLE_VLAN,
1772 + /* Port attributes. */
1773 + GSW_ATTR_PORT_UNTAG,
1781 +struct mt7620_gsw {
1782 + struct device *dev;
1783 + void __iomem *base;
1786 + long unsigned int autopoll;
1789 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1791 + iowrite32(val, gsw->base + reg);
1794 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1796 + return ioread32(gsw->base + reg);
1799 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1801 + unsigned long t_start = jiffies;
1804 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1806 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1811 + printk(KERN_ERR "mdio: MDIO timeout\n");
1815 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1818 + if (mt7620_mii_busy_wait(gsw))
1821 + write_data &= 0xffff;
1823 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1824 + (phy_register << GSW_MDIO_REG_SHIFT) |
1825 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1826 + MT7620A_GSW_REG_PIAC);
1828 + if (mt7620_mii_busy_wait(gsw))
1834 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1838 + if (mt7620_mii_busy_wait(gsw))
1841 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1842 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1843 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1844 + MT7620A_GSW_REG_PIAC);
1846 + if (mt7620_mii_busy_wait(gsw))
1849 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1854 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1856 + struct fe_priv *priv = bus->priv;
1857 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1859 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1862 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1864 + struct fe_priv *priv = bus->priv;
1865 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1867 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1870 +static unsigned char *fe_speed_str(int speed)
1887 +int mt7620a_has_carrier(struct fe_priv *priv)
1889 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1892 + for (i = 0; i < GSW_PORT6; i++)
1893 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1898 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1903 + if (mt7620a_has_carrier(priv))
1904 + netif_carrier_on(priv->netdev);
1906 + netif_carrier_off(priv->netdev);
1909 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1911 + if (priv->link[port])
1912 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1913 + port, fe_speed_str(priv->phy->speed[port]),
1914 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1916 + netdev_info(priv->netdev, "port %d link down\n", port);
1917 + mt7620a_handle_carrier(priv);
1920 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1922 + struct fe_priv *priv = (struct fe_priv *) _priv;
1923 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1925 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1927 + status = gsw_r32(gsw, GSW_REG_ISR);
1928 + if (status & PORT_IRQ_ST_CHG)
1929 + for (i = 0; i <= max; i++) {
1930 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1931 + int link = status & 0x1;
1933 + if (link != priv->link[i]) {
1935 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1936 + i, fe_speed_str((status >> 2) & 3),
1937 + (status & 0x2) ? "Full" : "Half");
1939 + netdev_info(priv->netdev, "port %d link down\n", i);
1942 + priv->link[i] = link;
1944 + mt7620a_handle_carrier(priv);
1946 + gsw_w32(gsw, status, GSW_REG_ISR);
1948 + return IRQ_HANDLED;
1951 +static int mt7620_is_bga(void)
1953 + u32 bga = rt_sysc_r32(0x0c);
1955 + return (bga >> 16) & 1;
1958 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1961 + int lsb = -1, msb = 0;
1963 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1969 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1972 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1974 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1975 + const __be32 *_id = of_get_property(np, "reg", NULL);
1976 + int phy_mode, size, id;
1978 + u32 val, mask = 0;
1979 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1981 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
1983 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
1985 + pr_err("%s: invalid port id\n", np->name);
1989 + id = be32_to_cpu(*_id);
1994 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
1995 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
1996 + pr_err("%s: invalid fixed link property\n", np->name);
1997 + priv->phy->phy_fixed[id] = NULL;
2001 + phy_mode = of_get_phy_mode(np);
2002 + switch (phy_mode) {
2003 + case PHY_INTERFACE_MODE_RGMII:
2006 + case PHY_INTERFACE_MODE_MII:
2009 + case PHY_INTERFACE_MODE_RMII:
2013 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2017 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2018 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2021 + val = rt_sysc_r32(SYSCFG1);
2022 + val &= ~(3 << shift);
2023 + val |= mask << shift;
2024 + rt_sysc_w32(val, SYSCFG1);
2026 + if (priv->phy->phy_fixed[id]) {
2027 + const __be32 *link = priv->phy->phy_fixed[id];
2031 + priv->phy->speed[id] = be32_to_cpup(link++);
2032 + tx_fc = be32_to_cpup(link++);
2033 + rx_fc = be32_to_cpup(link++);
2034 + priv->phy->duplex[id] = be32_to_cpup(link++);
2035 + priv->link[id] = 1;
2037 + switch (priv->phy->speed[id]) {
2048 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2049 + priv->phy->phy_fixed[id] = 0;
2052 + val = PMCR_SPEED(val);
2053 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2054 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2056 + val |= PMCR_TX_FC;
2058 + val |= PMCR_RX_FC;
2059 + if (priv->phy->duplex[id])
2060 + val |= PMCR_DUPLEX;
2061 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2062 + dev_info(priv->device, "using fixed link parameters\n");
2066 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2067 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2068 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2070 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2071 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2072 + gsw->autopoll |= BIT(id);
2073 + gsw_auto_poll(gsw);
2078 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2080 + u32 is_BGA = mt7620_is_bga();
2082 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2083 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2085 + /*correct PHY setting L3.0 BGA*/
2086 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2088 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2090 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2092 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2094 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2095 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2096 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2097 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2098 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2099 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2101 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2102 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2104 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2106 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2107 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2108 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2109 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2110 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2111 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2113 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2114 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2115 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2116 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2117 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2118 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2120 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2121 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2123 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2124 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2125 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2126 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2127 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2129 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2130 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2131 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2132 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2133 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2134 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2135 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2136 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2137 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2139 + /* CPU Port6 Force Link 1G, FC ON */
2140 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2141 + /* Set Port6 CPU Port */
2142 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2144 + /* setup port 4 */
2145 + if (gsw->port4 == PORT4_EPHY) {
2146 + u32 val = rt_sysc_r32(SYSCFG1);
2148 + rt_sysc_w32(val, SYSCFG1);
2149 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2150 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2151 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2152 + pr_info("gsw: setting port4 to ephy mode\n");
2156 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2158 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2159 + unsigned long flags;
2161 + spin_lock_irqsave(&priv->page_lock, flags);
2162 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2163 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2165 + spin_unlock_irqrestore(&priv->page_lock, flags);
2168 +static struct of_device_id gsw_match[] = {
2169 + { .compatible = "ralink,mt7620a-gsw" },
2173 +int mt7620_gsw_config(struct fe_priv *priv)
2175 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2177 + /* is the mt7530 internal or external */
2178 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2179 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2181 + mt7530_probe(priv->device, gsw->base, NULL);
2186 +int mt7620_gsw_probe(struct fe_priv *priv)
2188 + struct mt7620_gsw *gsw;
2189 + struct device_node *np;
2190 + const char *port4 = NULL;
2192 + np = of_find_matching_node(NULL, gsw_match);
2194 + dev_err(priv->device, "no gsw node found\n");
2197 + np = of_node_get(np);
2199 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2201 + dev_err(priv->device, "no gsw memory for private data\n");
2205 + gsw->irq = irq_of_parse_and_map(np, 0);
2207 + dev_err(priv->device, "no gsw irq resource found\n");
2211 + gsw->base = of_iomap(np, 0);
2213 + dev_err(priv->device, "gsw ioremap failed\n");
2217 + gsw->dev = priv->device;
2218 + priv->soc->swpriv = gsw;
2220 + of_property_read_string(np, "ralink,port4", &port4);
2221 + if (port4 && !strcmp(port4, "ephy"))
2222 + gsw->port4 = PORT4_EPHY;
2223 + else if (port4 && !strcmp(port4, "gmac"))
2224 + gsw->port4 = PORT4_EXT;
2230 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2231 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2236 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2239 + * This program is free software; you can redistribute it and/or modify
2240 + * it under the terms of the GNU General Public License as published by
2241 + * the Free Software Foundation; version 2 of the License
2243 + * This program is distributed in the hope that it will be useful,
2244 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2245 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2246 + * GNU General Public License for more details.
2248 + * You should have received a copy of the GNU General Public License
2249 + * along with this program; if not, write to the Free Software
2250 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2252 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2255 +#ifndef _RALINK_GSW_MT7620_H__
2256 +#define _RALINK_GSW_MT7620_H__
2258 +extern int mt7620_gsw_config(struct fe_priv *priv);
2259 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2260 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2261 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2262 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2263 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2264 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2265 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2269 +++ b/drivers/net/ethernet/ralink/mdio.c
2272 + * This program is free software; you can redistribute it and/or modify
2273 + * it under the terms of the GNU General Public License as published by
2274 + * the Free Software Foundation; version 2 of the License
2276 + * This program is distributed in the hope that it will be useful,
2277 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2278 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2279 + * GNU General Public License for more details.
2281 + * You should have received a copy of the GNU General Public License
2282 + * along with this program; if not, write to the Free Software
2283 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2285 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2288 +#include <linux/module.h>
2289 +#include <linux/kernel.h>
2290 +#include <linux/types.h>
2291 +#include <linux/dma-mapping.h>
2292 +#include <linux/init.h>
2293 +#include <linux/skbuff.h>
2294 +#include <linux/etherdevice.h>
2295 +#include <linux/ethtool.h>
2296 +#include <linux/platform_device.h>
2297 +#include <linux/phy.h>
2298 +#include <linux/of_device.h>
2299 +#include <linux/clk.h>
2300 +#include <linux/of_net.h>
2301 +#include <linux/of_mdio.h>
2303 +#include "ralink_soc_eth.h"
2306 +static int fe_mdio_reset(struct mii_bus *bus)
2312 +static void fe_phy_link_adjust(struct net_device *dev)
2314 + struct fe_priv *priv = netdev_priv(dev);
2315 + unsigned long flags;
2318 + spin_lock_irqsave(&priv->phy->lock, flags);
2319 + for (i = 0; i < 8; i++) {
2320 + if (priv->phy->phy_node[i]) {
2321 + struct phy_device *phydev = priv->phy->phy[i];
2322 + int status_change = 0;
2325 + if (priv->phy->duplex[i] != phydev->duplex ||
2326 + priv->phy->speed[i] != phydev->speed)
2327 + status_change = 1;
2329 + if (phydev->link != priv->link[i])
2330 + status_change = 1;
2332 + switch (phydev->speed) {
2336 + priv->link[i] = phydev->link;
2337 + priv->phy->duplex[i] = phydev->duplex;
2338 + priv->phy->speed[i] = phydev->speed;
2340 + if (status_change && priv->soc->mdio_adjust_link)
2341 + priv->soc->mdio_adjust_link(priv, i);
2348 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2350 + const __be32 *_port = NULL;
2351 + struct phy_device *phydev;
2352 + int phy_mode, port;
2354 + _port = of_get_property(phy_node, "reg", NULL);
2356 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2357 + pr_err("%s: invalid port id\n", phy_node->name);
2360 + port = be32_to_cpu(*_port);
2361 + phy_mode = of_get_phy_mode(phy_node);
2362 + if (phy_mode < 0) {
2363 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2364 + priv->phy->phy_node[port] = NULL;
2368 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2370 + if (IS_ERR(phydev)) {
2371 + dev_err(priv->device, "could not connect to PHY\n");
2372 + priv->phy->phy_node[port] = NULL;
2373 + return PTR_ERR(phydev);
2376 + phydev->supported &= PHY_GBIT_FEATURES;
2377 + phydev->advertising = phydev->supported;
2378 + phydev->no_auto_carrier_off = 1;
2380 + dev_info(priv->device,
2381 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2382 + port, dev_name(&phydev->dev), phydev->phy_id,
2383 + phydev->drv->name);
2385 + priv->phy->phy[port] = phydev;
2386 + priv->link[port] = 0;
2391 +static int fe_phy_connect(struct fe_priv *priv)
2396 +static void fe_phy_disconnect(struct fe_priv *priv)
2398 + unsigned long flags;
2401 + for (i = 0; i < 8; i++)
2402 + if (priv->phy->phy_fixed[i]) {
2403 + spin_lock_irqsave(&priv->phy->lock, flags);
2404 + priv->link[i] = 0;
2405 + if (priv->soc->mdio_adjust_link)
2406 + priv->soc->mdio_adjust_link(priv, i);
2407 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2408 + } else if (priv->phy->phy[i]) {
2409 + phy_disconnect(priv->phy->phy[i]);
2413 +static void fe_phy_start(struct fe_priv *priv)
2415 + unsigned long flags;
2418 + for (i = 0; i < 8; i++) {
2419 + if (priv->phy->phy_fixed[i]) {
2420 + spin_lock_irqsave(&priv->phy->lock, flags);
2421 + priv->link[i] = 1;
2422 + if (priv->soc->mdio_adjust_link)
2423 + priv->soc->mdio_adjust_link(priv, i);
2424 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2425 + } else if (priv->phy->phy[i]) {
2426 + phy_start(priv->phy->phy[i]);
2431 +static void fe_phy_stop(struct fe_priv *priv)
2433 + unsigned long flags;
2436 + for (i = 0; i < 8; i++)
2437 + if (priv->phy->phy_fixed[i]) {
2438 + spin_lock_irqsave(&priv->phy->lock, flags);
2439 + priv->link[i] = 0;
2440 + if (priv->soc->mdio_adjust_link)
2441 + priv->soc->mdio_adjust_link(priv, i);
2442 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2443 + } else if (priv->phy->phy[i]) {
2444 + phy_stop(priv->phy->phy[i]);
2448 +static struct fe_phy phy_ralink = {
2449 + .connect = fe_phy_connect,
2450 + .disconnect = fe_phy_disconnect,
2451 + .start = fe_phy_start,
2452 + .stop = fe_phy_stop,
2455 +int fe_mdio_init(struct fe_priv *priv)
2457 + struct device_node *mii_np;
2460 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2463 + spin_lock_init(&phy_ralink.lock);
2464 + priv->phy = &phy_ralink;
2466 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2468 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2472 + if (!of_device_is_available(mii_np)) {
2474 + goto err_put_node;
2477 + priv->mii_bus = mdiobus_alloc();
2478 + if (priv->mii_bus == NULL) {
2480 + goto err_put_node;
2483 + priv->mii_bus->name = "mdio";
2484 + priv->mii_bus->read = priv->soc->mdio_read;
2485 + priv->mii_bus->write = priv->soc->mdio_write;
2486 + priv->mii_bus->reset = fe_mdio_reset;
2487 + priv->mii_bus->irq = priv->mii_irq;
2488 + priv->mii_bus->priv = priv;
2489 + priv->mii_bus->parent = priv->device;
2491 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2492 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2494 + goto err_free_bus;
2499 + kfree(priv->mii_bus);
2501 + of_node_put(mii_np);
2502 + priv->mii_bus = NULL;
2506 +void fe_mdio_cleanup(struct fe_priv *priv)
2508 + if (!priv->mii_bus)
2511 + mdiobus_unregister(priv->mii_bus);
2512 + of_node_put(priv->mii_bus->dev.of_node);
2513 + kfree(priv->mii_bus);
2516 +++ b/drivers/net/ethernet/ralink/mdio.h
2519 + * This program is free software; you can redistribute it and/or modify
2520 + * it under the terms of the GNU General Public License as published by
2521 + * the Free Software Foundation; version 2 of the License
2523 + * This program is distributed in the hope that it will be useful,
2524 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2525 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2526 + * GNU General Public License for more details.
2528 + * You should have received a copy of the GNU General Public License
2529 + * along with this program; if not, write to the Free Software
2530 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2532 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2535 +#ifndef _RALINK_MDIO_H__
2536 +#define _RALINK_MDIO_H__
2538 +#ifdef CONFIG_NET_RALINK_MDIO
2539 +extern int fe_mdio_init(struct fe_priv *priv);
2540 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2541 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2543 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2544 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2548 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
2551 + * This program is free software; you can redistribute it and/or modify
2552 + * it under the terms of the GNU General Public License as published by
2553 + * the Free Software Foundation; version 2 of the License
2555 + * This program is distributed in the hope that it will be useful,
2556 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2557 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2558 + * GNU General Public License for more details.
2560 + * You should have received a copy of the GNU General Public License
2561 + * along with this program; if not, write to the Free Software
2562 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2564 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2567 +#include <linux/module.h>
2568 +#include <linux/kernel.h>
2569 +#include <linux/types.h>
2570 +#include <linux/dma-mapping.h>
2571 +#include <linux/init.h>
2572 +#include <linux/skbuff.h>
2573 +#include <linux/etherdevice.h>
2574 +#include <linux/ethtool.h>
2575 +#include <linux/platform_device.h>
2576 +#include <linux/phy.h>
2577 +#include <linux/of_device.h>
2578 +#include <linux/clk.h>
2579 +#include <linux/of_net.h>
2580 +#include <linux/of_mdio.h>
2582 +#include "ralink_soc_eth.h"
2583 +#include "mdio_rt2880.h"
2586 +#define FE_MDIO_RETRY 1000
2588 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2590 + switch (priv->phy->speed[0]) {
2602 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2606 + if (!priv->link[0]) {
2607 + netif_carrier_off(priv->netdev);
2608 + netdev_info(priv->netdev, "link down\n");
2612 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2613 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2614 + FE_MDIO_CFG_GP1_FRC_EN;
2616 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2617 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2619 + if (priv->phy->tx_fc[0])
2620 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2622 + if (priv->phy->rx_fc[0])
2623 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2625 + switch (priv->phy->speed[0]) {
2627 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2630 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2633 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2639 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2641 + netif_carrier_on(priv->netdev);
2642 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2643 + rt2880_speed_str(priv),
2644 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2647 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2651 + retries = FE_MDIO_RETRY;
2655 + t = fe_r32(FE_MDIO_ACCESS);
2656 + if ((t & (0x1 << 31)) == 0)
2659 + if (retries-- == 0)
2665 + dev_err(priv->device, "MDIO operation timed out\n");
2666 + return -ETIMEDOUT;
2669 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2671 + struct fe_priv *priv = bus->priv;
2675 + err = rt2880_mdio_wait_ready(priv);
2679 + t = (phy_addr << 24) | (phy_reg << 16);
2680 + fe_w32(t, FE_MDIO_ACCESS);
2682 + fe_w32(t, FE_MDIO_ACCESS);
2684 + err = rt2880_mdio_wait_ready(priv);
2688 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2689 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2691 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2694 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2696 + struct fe_priv *priv = bus->priv;
2700 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2701 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2703 + err = rt2880_mdio_wait_ready(priv);
2707 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2708 + fe_w32(t, FE_MDIO_ACCESS);
2710 + fe_w32(t, FE_MDIO_ACCESS);
2712 + return rt2880_mdio_wait_ready(priv);
2715 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2717 + const __be32 *id = of_get_property(np, "reg", NULL);
2718 + const __be32 *link;
2722 + if (!id || (be32_to_cpu(*id) != 0)) {
2723 + pr_err("%s: invalid port id\n", np->name);
2727 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2728 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2729 + pr_err("%s: invalid fixed link property\n", np->name);
2730 + priv->phy->phy_fixed[0] = NULL;
2734 + phy_mode = of_get_phy_mode(np);
2735 + switch (phy_mode) {
2736 + case PHY_INTERFACE_MODE_RGMII:
2738 + case PHY_INTERFACE_MODE_MII:
2740 + case PHY_INTERFACE_MODE_RMII:
2743 + if (!priv->phy->phy_fixed[0])
2744 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2748 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2749 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2752 + if (priv->phy->phy_fixed[0]) {
2753 + link = priv->phy->phy_fixed[0];
2754 + priv->phy->speed[0] = be32_to_cpup(link++);
2755 + priv->phy->duplex[0] = be32_to_cpup(link++);
2756 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2757 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2759 + priv->link[0] = 1;
2760 + switch (priv->phy->speed[0]) {
2768 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2769 + priv->phy->phy_fixed[0] = 0;
2772 + dev_info(priv->device, "using fixed link parameters\n");
2773 + rt2880_mdio_link_adjust(priv, 0);
2776 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2777 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2783 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
2786 + * This program is free software; you can redistribute it and/or modify
2787 + * it under the terms of the GNU General Public License as published by
2788 + * the Free Software Foundation; version 2 of the License
2790 + * This program is distributed in the hope that it will be useful,
2791 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2792 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2793 + * GNU General Public License for more details.
2795 + * You should have received a copy of the GNU General Public License
2796 + * along with this program; if not, write to the Free Software
2797 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2799 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2802 +#ifndef _RALINK_MDIO_RT2880_H__
2803 +#define _RALINK_MDIO_RT2880_H__
2805 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2806 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2807 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2808 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2812 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
2815 + * This program is free software; you can redistribute it and/or modify
2816 + * it under the terms of the GNU General Public License as published by
2817 + * the Free Software Foundation; version 2 of the License
2819 + * This program is distributed in the hope that it will be useful,
2820 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2821 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2822 + * GNU General Public License for more details.
2824 + * You should have received a copy of the GNU General Public License
2825 + * along with this program; if not, write to the Free Software
2826 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2828 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2831 +#include <linux/module.h>
2832 +#include <linux/kernel.h>
2833 +#include <linux/types.h>
2834 +#include <linux/dma-mapping.h>
2835 +#include <linux/init.h>
2836 +#include <linux/skbuff.h>
2837 +#include <linux/etherdevice.h>
2838 +#include <linux/ethtool.h>
2839 +#include <linux/platform_device.h>
2840 +#include <linux/of_device.h>
2841 +#include <linux/clk.h>
2842 +#include <linux/of_net.h>
2843 +#include <linux/of_mdio.h>
2844 +#include <linux/if_vlan.h>
2845 +#include <linux/reset.h>
2847 +#include <asm/mach-ralink/ralink_regs.h>
2849 +#include "ralink_soc_eth.h"
2850 +#include "esw_rt3052.h"
2853 +#define TX_TIMEOUT (20 * HZ / 100)
2854 +#define MAX_RX_LENGTH 1536
2856 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
2857 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
2858 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
2859 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
2860 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
2861 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
2862 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
2863 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
2864 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
2865 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
2866 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
2867 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
2870 +static const u32 *fe_reg_table = fe_reg_table_default;
2872 +static void __iomem *fe_base = 0;
2874 +void fe_w32(u32 val, unsigned reg)
2876 + __raw_writel(val, fe_base + reg);
2879 +u32 fe_r32(unsigned reg)
2881 + return __raw_readl(fe_base + reg);
2884 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
2886 + fe_w32(val, fe_reg_table[reg]);
2889 +static inline u32 fe_reg_r32(enum fe_reg reg)
2891 + return fe_r32(fe_reg_table[reg]);
2894 +static inline void fe_int_disable(u32 mask)
2896 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
2897 + FE_REG_FE_INT_ENABLE);
2899 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2902 +static inline void fe_int_enable(u32 mask)
2904 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
2905 + FE_REG_FE_INT_ENABLE);
2907 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2910 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
2912 + unsigned long flags;
2914 + spin_lock_irqsave(&priv->page_lock, flags);
2915 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
2916 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2917 + FE_GDMA1_MAC_ADRL);
2918 + spin_unlock_irqrestore(&priv->page_lock, flags);
2921 +static int fe_set_mac_address(struct net_device *dev, void *p)
2923 + int ret = eth_mac_addr(dev, p);
2926 + struct fe_priv *priv = netdev_priv(dev);
2928 + if (priv->soc->set_mac)
2929 + priv->soc->set_mac(priv, dev->dev_addr);
2931 + fe_hw_set_macaddr(priv, p);
2937 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
2939 + struct sk_buff *skb;
2941 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2945 + skb_reserve(skb, NET_IP_ALIGN);
2950 +static int fe_alloc_rx(struct fe_priv *priv)
2952 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
2955 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2956 + &priv->rx_phys, GFP_ATOMIC);
2957 + if (!priv->rx_dma)
2960 + memset(priv->rx_dma, 0, size);
2962 + for (i = 0; i < NUM_DMA_DESC; i++) {
2963 + priv->rx_skb[i] = fe_alloc_skb(priv);
2964 + if (!priv->rx_skb[i])
2968 + for (i = 0; i < NUM_DMA_DESC; i++) {
2969 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
2970 + priv->rx_skb[i]->data,
2973 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
2975 + if (priv->soc->rx_dma)
2976 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
2978 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
2982 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
2983 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
2984 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
2985 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
2990 +static int fe_alloc_tx(struct fe_priv *priv)
2992 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
2995 + priv->tx_free_idx = 0;
2997 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2998 + &priv->tx_phys, GFP_ATOMIC);
2999 + if (!priv->tx_dma)
3002 + memset(priv->tx_dma, 0, size);
3004 + for (i = 0; i < NUM_DMA_DESC; i++) {
3005 + if (priv->soc->tx_dma) {
3006 + priv->soc->tx_dma(priv, i, NULL);
3010 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3011 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3014 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3015 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3016 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3017 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3022 +static void fe_free_dma(struct fe_priv *priv)
3026 + for (i = 0; i < NUM_DMA_DESC; i++) {
3027 + if (priv->rx_skb[i]) {
3028 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3029 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3030 + dev_kfree_skb_any(priv->rx_skb[i]);
3031 + priv->rx_skb[i] = NULL;
3034 + if (priv->tx_skb[i]) {
3035 + dev_kfree_skb_any(priv->tx_skb[i]);
3036 + priv->tx_skb[i] = NULL;
3040 + if (priv->rx_dma) {
3041 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3042 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3046 + if (priv->tx_dma) {
3047 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3048 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3052 + netdev_reset_queue(priv->netdev);
3055 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3057 + struct fe_priv *priv = netdev_priv(dev);
3058 + dma_addr_t mapped_addr;
3062 + if (priv->soc->min_pkt_len) {
3063 + if (skb->len < priv->soc->min_pkt_len) {
3064 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3066 + "fe_eth: skb_padto failed\n");
3070 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3074 + dev->trans_start = jiffies;
3075 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3076 + skb->len, DMA_TO_DEVICE);
3078 + spin_lock(&priv->page_lock);
3080 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3081 + tx_next = (tx + 1) % NUM_DMA_DESC;
3083 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3084 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3085 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3087 + spin_unlock(&priv->page_lock);
3088 + dev->stats.tx_dropped++;
3091 + return NETDEV_TX_OK;
3094 + priv->tx_skb[tx] = skb;
3095 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3098 + priv->tx_dma[tx].txd4 &= ~0x80;
3099 + if (priv->soc->tx_dma)
3100 + priv->soc->tx_dma(priv, tx, skb);
3102 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3104 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3105 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3107 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3109 + dev->stats.tx_packets++;
3110 + dev->stats.tx_bytes += skb->len;
3112 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3113 + netdev_sent_queue(dev, skb->len);
3115 + spin_unlock(&priv->page_lock);
3117 + return NETDEV_TX_OK;
3120 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3122 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3123 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3127 + while ((rx < budget) && !complete) {
3128 + idx = (idx + 1) % NUM_DMA_DESC;
3130 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3131 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3134 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3135 + dma_addr_t dma_addr;
3137 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3138 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3140 + skb_put(priv->rx_skb[idx], pktlen);
3141 + priv->rx_skb[idx]->dev = priv->netdev;
3142 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3143 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3144 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3146 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3147 + priv->netdev->stats.rx_packets++;
3148 + priv->netdev->stats.rx_bytes += pktlen;
3150 +#ifdef CONFIG_INET_LRO
3151 + if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3152 + lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3155 + netif_receive_skb(priv->rx_skb[idx]);
3157 + priv->rx_skb[idx] = new_skb;
3159 + dma_addr = dma_map_single(&priv->netdev->dev,
3163 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3166 + priv->netdev->stats.rx_dropped++;
3169 + if (priv->soc->rx_dma)
3170 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3172 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3173 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3181 +#ifdef CONFIG_INET_LRO
3182 + if (priv->soc->get_skb_header)
3183 + lro_flush_all(&priv->lro_mgr);
3186 + napi_complete(&priv->rx_napi);
3187 + fe_int_enable(priv->soc->rx_dly_int);
3193 +static void fe_tx_housekeeping(unsigned long ptr)
3195 + struct net_device *dev = (struct net_device*)ptr;
3196 + struct fe_priv *priv = netdev_priv(dev);
3197 + unsigned int bytes_compl = 0;
3198 + unsigned int pkts_compl = 0;
3200 + spin_lock(&priv->page_lock);
3202 + struct fe_tx_dma *txd;
3204 + txd = &priv->tx_dma[priv->tx_free_idx];
3206 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3209 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3212 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3213 + priv->tx_skb[priv->tx_free_idx] = NULL;
3214 + priv->tx_free_idx++;
3215 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3216 + priv->tx_free_idx = 0;
3219 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3220 + spin_unlock(&priv->page_lock);
3222 + fe_int_enable(priv->soc->tx_dly_int);
3225 +static void fe_tx_timeout(struct net_device *dev)
3227 + struct fe_priv *priv = netdev_priv(dev);
3229 + tasklet_schedule(&priv->tx_tasklet);
3230 + priv->netdev->stats.tx_errors++;
3231 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3232 + netif_wake_queue(dev);
3235 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3237 + struct fe_priv *priv = netdev_priv(dev);
3238 + unsigned int status;
3239 + unsigned int mask;
3241 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3242 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3244 + if (!(status & mask))
3247 + if (status & priv->soc->rx_dly_int) {
3248 + fe_int_disable(priv->soc->rx_dly_int);
3249 + napi_schedule(&priv->rx_napi);
3252 + if (status & priv->soc->tx_dly_int) {
3253 + fe_int_disable(priv->soc->tx_dly_int);
3254 + tasklet_schedule(&priv->tx_tasklet);
3257 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3259 + return IRQ_HANDLED;
3262 +static int fe_hw_init(struct net_device *dev)
3264 + struct fe_priv *priv = netdev_priv(dev);
3267 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3268 + dev_name(priv->device), dev);
3272 + err = fe_alloc_rx(priv);
3274 + err = fe_alloc_tx(priv);
3278 + if (priv->soc->set_mac)
3279 + priv->soc->set_mac(priv, dev->dev_addr);
3281 + fe_hw_set_macaddr(priv, dev->dev_addr);
3283 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3285 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3287 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3289 + if (priv->soc->fwd_config) {
3290 + priv->soc->fwd_config(priv);
3292 + unsigned long sysclk = priv->sysclk;
3295 + netdev_err(dev, "unable to get clock\n");
3299 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3300 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3302 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3303 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3306 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3307 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3308 + FE_GDMA1_FWD_CFG);
3309 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3311 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3314 + fe_w32(1, FE_FE_RST_GL);
3315 + fe_w32(0, FE_FE_RST_GL);
3320 +static int fe_open(struct net_device *dev)
3322 + struct fe_priv *priv = netdev_priv(dev);
3323 + unsigned long flags;
3326 + spin_lock_irqsave(&priv->page_lock, flags);
3327 + napi_enable(&priv->rx_napi);
3329 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3330 + val |= priv->soc->pdma_glo_cfg;
3331 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3333 + spin_unlock_irqrestore(&priv->page_lock, flags);
3336 + priv->phy->start(priv);
3338 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3339 + netif_carrier_on(dev);
3341 + netif_start_queue(dev);
3342 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3347 +static int fe_stop(struct net_device *dev)
3349 + struct fe_priv *priv = netdev_priv(dev);
3350 + unsigned long flags;
3352 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3354 + netif_stop_queue(dev);
3357 + priv->phy->stop(priv);
3359 + spin_lock_irqsave(&priv->page_lock, flags);
3360 + napi_disable(&priv->rx_napi);
3362 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3363 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3364 + FE_REG_PDMA_GLO_CFG);
3365 + spin_unlock_irqrestore(&priv->page_lock, flags);
3370 +static int __init fe_init(struct net_device *dev)
3372 + struct fe_priv *priv = netdev_priv(dev);
3373 + struct device_node *port;
3376 + BUG_ON(!priv->soc->reset_fe);
3377 + priv->soc->reset_fe();
3379 + if (priv->soc->switch_init)
3380 + priv->soc->switch_init(priv);
3382 + net_srandom(jiffies);
3383 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3384 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3386 + err = fe_mdio_init(priv);
3391 + err = priv->phy->connect(priv);
3393 + goto err_mdio_cleanup;
3396 + if (priv->soc->port_init)
3397 + for_each_child_of_node(priv->device->of_node, port)
3398 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
3399 + priv->soc->port_init(priv, port);
3401 + err = fe_hw_init(dev);
3403 + goto err_phy_disconnect;
3405 + if (priv->soc->switch_config)
3406 + priv->soc->switch_config(priv);
3410 +err_phy_disconnect:
3412 + priv->phy->disconnect(priv);
3414 + fe_mdio_cleanup(priv);
3419 +static void fe_uninit(struct net_device *dev)
3421 + struct fe_priv *priv = netdev_priv(dev);
3423 + tasklet_kill(&priv->tx_tasklet);
3426 + priv->phy->disconnect(priv);
3427 + fe_mdio_cleanup(priv);
3429 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3430 + free_irq(dev->irq, dev);
3432 + fe_free_dma(priv);
3435 +static const struct net_device_ops fe_netdev_ops = {
3436 + .ndo_init = fe_init,
3437 + .ndo_uninit = fe_uninit,
3438 + .ndo_open = fe_open,
3439 + .ndo_stop = fe_stop,
3440 + .ndo_start_xmit = fe_start_xmit,
3441 + .ndo_tx_timeout = fe_tx_timeout,
3442 + .ndo_set_mac_address = fe_set_mac_address,
3443 + .ndo_change_mtu = eth_change_mtu,
3444 + .ndo_validate_addr = eth_validate_addr,
3447 +static int fe_probe(struct platform_device *pdev)
3449 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3450 + const struct of_device_id *match;
3451 + struct fe_soc_data *soc = NULL;
3452 + struct net_device *netdev;
3453 + struct fe_priv *priv;
3454 + struct clk *sysclk;
3457 + device_reset(&pdev->dev);
3459 + match = of_match_device(of_fe_match, &pdev->dev);
3460 + soc = (struct fe_soc_data *) match->data;
3461 + if (soc->reg_table)
3462 + fe_reg_table = soc->reg_table;
3464 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3468 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3470 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3474 + strcpy(netdev->name, "eth%d");
3475 + netdev->netdev_ops = &fe_netdev_ops;
3476 + netdev->base_addr = (unsigned long) fe_base;
3477 + netdev->watchdog_timeo = TX_TIMEOUT;
3478 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3480 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3481 + netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
3483 + netdev->irq = platform_get_irq(pdev, 0);
3484 + if (netdev->irq < 0) {
3485 + dev_err(&pdev->dev, "no IRQ resource found\n");
3490 + priv = netdev_priv(netdev);
3491 + memset(priv, 0, sizeof(struct fe_priv));
3492 + spin_lock_init(&priv->page_lock);
3494 + sysclk = devm_clk_get(&pdev->dev, NULL);
3495 + if (!IS_ERR(sysclk))
3496 + priv->sysclk = clk_get_rate(sysclk);
3498 + priv->netdev = netdev;
3499 + priv->device = &pdev->dev;
3502 + err = register_netdev(netdev);
3504 + dev_err(&pdev->dev, "error bringing up device\n");
3508 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3510 +#ifdef CONFIG_INET_LRO
3511 + if (priv->soc->get_skb_header) {
3512 + priv->lro_mgr.dev = netdev;
3513 + memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
3514 + priv->lro_mgr.features = LRO_F_NAPI;
3515 + priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
3516 + priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
3517 + priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
3518 + priv->lro_mgr.max_aggr = 64;
3519 + priv->lro_mgr.frag_align_pad = 0;
3520 + priv->lro_mgr.lro_arr = priv->lro_arr;
3521 + priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
3525 + platform_set_drvdata(pdev, netdev);
3527 + netdev_info(netdev, "done loading\n");
3532 +static int fe_remove(struct platform_device *pdev)
3534 + struct net_device *dev = platform_get_drvdata(pdev);
3535 + struct fe_priv *priv = netdev_priv(dev);
3537 + netif_stop_queue(dev);
3538 + netif_napi_del(&priv->rx_napi);
3540 + unregister_netdev(dev);
3546 +static struct platform_driver fe_driver = {
3547 + .probe = fe_probe,
3548 + .remove = fe_remove,
3550 + .name = "ralink_soc_eth",
3551 + .owner = THIS_MODULE,
3552 + .of_match_table = of_fe_match,
3556 +static int __init init_rtfe(void)
3560 + ret = rtesw_init();
3564 + ret = platform_driver_register(&fe_driver);
3571 +static void __exit exit_rtfe(void)
3573 + platform_driver_unregister(&fe_driver);
3577 +module_init(init_rtfe);
3578 +module_exit(exit_rtfe);
3580 +MODULE_LICENSE("GPL");
3581 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3582 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
3584 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
3587 + * This program is free software; you can redistribute it and/or modify
3588 + * it under the terms of the GNU General Public License as published by
3589 + * the Free Software Foundation; version 2 of the License
3591 + * This program is distributed in the hope that it will be useful,
3592 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3593 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3594 + * GNU General Public License for more details.
3596 + * You should have received a copy of the GNU General Public License
3597 + * along with this program; if not, write to the Free Software
3598 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3600 + * based on Ralink SDK3.3
3601 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3607 +#include <linux/mii.h>
3608 +#include <linux/interrupt.h>
3609 +#include <linux/netdevice.h>
3610 +#include <linux/dma-mapping.h>
3611 +#include <linux/phy.h>
3612 +#include <linux/inet_lro.h>
3616 + FE_REG_PDMA_GLO_CFG = 0,
3617 + FE_REG_PDMA_RST_CFG,
3618 + FE_REG_DLY_INT_CFG,
3619 + FE_REG_TX_BASE_PTR0,
3620 + FE_REG_TX_MAX_CNT0,
3621 + FE_REG_TX_CTX_IDX0,
3622 + FE_REG_RX_BASE_PTR0,
3623 + FE_REG_RX_MAX_CNT0,
3624 + FE_REG_RX_CALC_IDX0,
3625 + FE_REG_FE_INT_ENABLE,
3626 + FE_REG_FE_INT_STATUS,
3627 + FE_REG_FE_DMA_VID_BASE,
3631 +#define NUM_DMA_DESC 0x100
3633 +#define FE_DELAY_EN_INT 0x80
3634 +#define FE_DELAY_MAX_INT 0x04
3635 +#define FE_DELAY_MAX_TOUT 0x04
3636 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
3637 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
3638 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
3640 +/* interrupt bits */
3641 +#define FE_CNT_PPE_AF BIT(31)
3642 +#define FE_CNT_GDM_AF BIT(29)
3643 +#define FE_PSE_P2_FC BIT(26)
3644 +#define FE_PSE_BUF_DROP BIT(24)
3645 +#define FE_GDM_OTHER_DROP BIT(23)
3646 +#define FE_PSE_P1_FC BIT(22)
3647 +#define FE_PSE_P0_FC BIT(21)
3648 +#define FE_PSE_FQ_EMPTY BIT(20)
3649 +#define FE_GE1_STA_CHG BIT(18)
3650 +#define FE_TX_COHERENT BIT(17)
3651 +#define FE_RX_COHERENT BIT(16)
3652 +#define FE_TX_DONE_INT3 BIT(11)
3653 +#define FE_TX_DONE_INT2 BIT(10)
3654 +#define FE_TX_DONE_INT1 BIT(9)
3655 +#define FE_TX_DONE_INT0 BIT(8)
3656 +#define FE_RX_DONE_INT0 BIT(2)
3657 +#define FE_TX_DLY_INT BIT(1)
3658 +#define FE_RX_DLY_INT BIT(0)
3660 +#define RT5350_RX_DLY_INT BIT(30)
3661 +#define RT5350_TX_DLY_INT BIT(28)
3664 +#define FE_FE_OFFSET 0x0000
3665 +#define FE_GDMA_OFFSET 0x0020
3666 +#define FE_PSE_OFFSET 0x0040
3667 +#define FE_GDMA2_OFFSET 0x0060
3668 +#define FE_CDMA_OFFSET 0x0080
3669 +#define FE_DMA_VID0 0x00a8
3670 +#define FE_PDMA_OFFSET 0x0100
3671 +#define FE_PPE_OFFSET 0x0200
3672 +#define FE_CMTABLE_OFFSET 0x0400
3673 +#define FE_POLICYTABLE_OFFSET 0x1000
3675 +#define RT5350_PDMA_OFFSET 0x0800
3676 +#define RT5350_SDM_OFFSET 0x0c00
3678 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
3679 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
3680 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
3681 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
3682 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
3683 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
3684 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
3685 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
3687 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
3688 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
3689 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
3690 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
3691 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
3693 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
3694 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
3695 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
3696 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
3697 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
3699 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
3700 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
3701 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
3702 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
3704 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
3705 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
3707 +#define MT7620A_GDMA_OFFSET 0x0600
3708 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
3709 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
3710 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
3711 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
3712 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
3714 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
3715 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
3716 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
3717 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
3718 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
3719 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
3720 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
3721 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
3722 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
3723 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
3724 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
3725 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
3726 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
3727 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
3728 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
3729 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
3730 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
3731 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
3732 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
3733 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
3734 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
3735 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
3736 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
3737 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
3738 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
3739 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
3740 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
3741 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
3742 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
3743 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
3745 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
3746 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
3747 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
3748 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
3749 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
3750 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
3751 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
3752 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
3753 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
3754 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
3755 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
3756 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
3757 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
3758 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
3759 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
3760 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
3761 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
3762 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
3763 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
3764 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
3765 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
3766 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
3767 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
3768 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
3769 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
3770 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
3771 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
3772 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
3774 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
3775 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
3776 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
3777 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
3778 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
3779 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
3780 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
3781 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
3782 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
3783 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
3785 +#define RT5350_SDM_ICS_EN BIT(16)
3786 +#define RT5350_SDM_TCS_EN BIT(17)
3787 +#define RT5350_SDM_UCS_EN BIT(18)
3790 +/* MDIO_CFG register bits */
3791 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
3792 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
3793 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
3794 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
3795 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
3796 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
3797 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
3798 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
3799 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
3800 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
3801 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
3802 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
3803 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
3804 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
3805 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
3806 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
3807 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
3808 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
3809 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
3810 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
3811 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
3812 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
3813 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
3814 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
3815 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
3817 +/* uni-cast port */
3818 +#define FE_GDM1_ICS_EN BIT(22)
3819 +#define FE_GDM1_TCS_EN BIT(21)
3820 +#define FE_GDM1_UCS_EN BIT(20)
3821 +#define FE_GDM1_JMB_EN BIT(19)
3822 +#define FE_GDM1_STRPCRC BIT(16)
3823 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
3824 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
3825 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
3828 +#define FE_ICS_GEN_EN BIT(2)
3829 +#define FE_UCS_GEN_EN BIT(1)
3830 +#define FE_TCS_GEN_EN BIT(0)
3833 +#define FE_PST_DRX_IDX0 BIT(16)
3834 +#define FE_PST_DTX_IDX3 BIT(3)
3835 +#define FE_PST_DTX_IDX2 BIT(2)
3836 +#define FE_PST_DTX_IDX1 BIT(1)
3837 +#define FE_PST_DTX_IDX0 BIT(0)
3839 +#define FE_TX_WB_DDONE BIT(6)
3840 +#define FE_RX_DMA_BUSY BIT(3)
3841 +#define FE_TX_DMA_BUSY BIT(1)
3842 +#define FE_RX_DMA_EN BIT(2)
3843 +#define FE_TX_DMA_EN BIT(0)
3845 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
3846 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
3847 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
3849 +#define FE_US_CYC_CNT_MASK 0xff
3850 +#define FE_US_CYC_CNT_SHIFT 0x8
3851 +#define FE_US_CYC_CNT_DIVISOR 1000000
3853 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
3854 +#define RX_DMA_LSO BIT(30)
3855 +#define RX_DMA_DONE BIT(31)
3856 +#define RX_DMA_L4VALID BIT(30)
3859 + unsigned int rxd1;
3860 + unsigned int rxd2;
3861 + unsigned int rxd3;
3862 + unsigned int rxd4;
3863 +} __packed __aligned(4);
3865 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
3866 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
3867 +#define TX_DMA_LSO BIT(30)
3868 +#define TX_DMA_DONE BIT(31)
3869 +#define TX_DMA_QN(_x) ((_x) << 16)
3870 +#define TX_DMA_PN(_x) ((_x) << 24)
3871 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
3872 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
3873 +#define TX_DMA_CHKSUM (0x7 << 29)
3876 + unsigned int txd1;
3877 + unsigned int txd2;
3878 + unsigned int txd3;
3879 + unsigned int txd4;
3880 +} __packed __aligned(4);
3885 + struct phy_device *phy[8];
3886 + struct device_node *phy_node[8];
3887 + const __be32 *phy_fixed[8];
3894 + int (*connect)(struct fe_priv *priv);
3895 + void (*disconnect)(struct fe_priv *priv);
3896 + void (*start)(struct fe_priv *priv);
3897 + void (*stop)(struct fe_priv *priv);
3902 + unsigned char mac[6];
3903 + const u32 *reg_table;
3905 + void (*reset_fe)(void);
3906 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
3907 + void (*fwd_config)(struct fe_priv *priv);
3908 + void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
3909 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
3910 + int (*switch_init)(struct fe_priv *priv);
3911 + int (*switch_config)(struct fe_priv *priv);
3912 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
3913 + int (*has_carrier)(struct fe_priv *priv);
3914 + int (*mdio_init)(struct fe_priv *priv);
3915 + void (*mdio_cleanup)(struct fe_priv *priv);
3916 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3917 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
3918 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
3919 + int (*get_skb_header)(struct sk_buff *skb, void **iphdr, void **tcph, u64 *hdr_flags, void *priv);
3932 + spinlock_t page_lock;
3934 + struct fe_soc_data *soc;
3935 + struct net_device *netdev;
3936 + struct device *device;
3937 + unsigned long sysclk;
3939 + struct fe_rx_dma *rx_dma;
3940 + struct napi_struct rx_napi;
3941 + struct sk_buff *rx_skb[NUM_DMA_DESC];
3942 + dma_addr_t rx_phys;
3944 + struct fe_tx_dma *tx_dma;
3945 + struct tasklet_struct tx_tasklet;
3946 + struct sk_buff *tx_skb[NUM_DMA_DESC];
3947 + dma_addr_t tx_phys;
3948 + unsigned int tx_free_idx;
3950 + struct fe_phy *phy;
3951 + struct mii_bus *mii_bus;
3952 + int mii_irq[PHY_MAX_ADDR];
3956 + struct net_lro_mgr lro_mgr;
3957 + struct net_lro_desc lro_arr[8];
3960 +extern const struct of_device_id of_fe_match[];
3962 +void fe_w32(u32 val, unsigned reg);
3963 +u32 fe_r32(unsigned reg);
3965 +#endif /* FE_ETH_H */
3967 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
3970 + * This program is free software; you can redistribute it and/or modify
3971 + * it under the terms of the GNU General Public License as published by
3972 + * the Free Software Foundation; version 2 of the License
3974 + * This program is distributed in the hope that it will be useful,
3975 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3976 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3977 + * GNU General Public License for more details.
3979 + * You should have received a copy of the GNU General Public License
3980 + * along with this program; if not, write to the Free Software
3981 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3983 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3986 +#include <linux/module.h>
3987 +#include <linux/platform_device.h>
3988 +#include <linux/if_vlan.h>
3990 +#include <asm/mach-ralink/ralink_regs.h>
3992 +#include "ralink_soc_eth.h"
3993 +#include "gsw_mt7620a.h"
3995 +#define MT7620A_CDMA_CSG_CFG 0x400
3996 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
3997 +#define MT7620A_DMA_2B_OFFSET BIT(31)
3998 +#define MT7620A_RESET_FE BIT(21)
3999 +#define MT7620A_RESET_ESW BIT(23)
4000 +#define MT7620_L4_VALID BIT(23)
4002 +#define SYSC_REG_RESET_CTRL 0x34
4003 +#define MAX_RX_LENGTH 1536
4005 +#define CDMA_ICS_EN BIT(2)
4006 +#define CDMA_UCS_EN BIT(1)
4007 +#define CDMA_TCS_EN BIT(0)
4009 +#define GDMA_ICS_EN BIT(22)
4010 +#define GDMA_TCS_EN BIT(21)
4011 +#define GDMA_UCS_EN BIT(20)
4013 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4014 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4015 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4016 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4017 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4018 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4019 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4020 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4021 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4022 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4023 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4024 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4025 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
4028 +static void mt7620_fe_reset(void)
4030 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
4031 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4034 +static void mt7620_fwd_config(struct fe_priv *priv)
4038 + /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4039 + for (i = 0; i < 16; i += 2)
4040 + fe_w32(((i + 1) << 16) + i, MT7620_DMA_VID + (i * 2));
4042 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4043 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4044 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4047 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
4050 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
4052 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4054 + if(skb && vlan_tx_tag_present(skb))
4055 + priv->tx_dma[idx].txd4 = 0x80 | (vlan_tx_tag_get(skb) >> 13) << 4 | (vlan_tx_tag_get(skb) & 0xF);
4057 + priv->tx_dma[idx].txd4 = 0;
4060 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4062 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4065 +#ifdef CONFIG_INET_LRO
4067 +mt7620_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
4068 + u64 *hdr_flags, void *_priv)
4070 + struct iphdr *iph = NULL;
4074 + * Make sure that this packet is Ethernet II, is not VLAN
4075 + * tagged, is IPv4, has a valid IP header, and is TCP.
4077 + if (skb->protocol == 0x0081)
4078 + vhdr_len = VLAN_HLEN;
4080 + iph = (struct iphdr *)(skb->data + vhdr_len);
4081 + if(iph->protocol != IPPROTO_TCP)
4085 + *tcph = skb->data + (iph->ihl << 2) + vhdr_len;
4086 + *hdr_flags = LRO_IPV4 | LRO_TCP;
4092 +static struct fe_soc_data mt7620_data = {
4093 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4094 + .reset_fe = mt7620_fe_reset,
4095 + .set_mac = mt7620_set_mac,
4096 + .fwd_config = mt7620_fwd_config,
4097 + .tx_dma = mt7620_tx_dma,
4098 + .rx_dma = mt7620_rx_dma,
4099 + .switch_init = mt7620_gsw_probe,
4100 + .switch_config = mt7620_gsw_config,
4101 + .port_init = mt7620_port_init,
4103 + .reg_table = rt5350_reg_table,
4104 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4105 + .rx_dly_int = RT5350_RX_DLY_INT,
4106 + .tx_dly_int = RT5350_TX_DLY_INT,
4107 + .checksum_bit = MT7620_L4_VALID,
4108 + .has_carrier = mt7620a_has_carrier,
4109 + .mdio_read = mt7620_mdio_read,
4110 + .mdio_write = mt7620_mdio_write,
4111 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4112 +#ifdef CONFIG_INET_LRO
4113 + .get_skb_header = mt7620_get_skb_header,
4117 +const struct of_device_id of_fe_match[] = {
4118 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4122 +MODULE_DEVICE_TABLE(of, of_fe_match);
4124 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4127 + * This program is free software; you can redistribute it and/or modify
4128 + * it under the terms of the GNU General Public License as published by
4129 + * the Free Software Foundation; version 2 of the License
4131 + * This program is distributed in the hope that it will be useful,
4132 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4133 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4134 + * GNU General Public License for more details.
4136 + * You should have received a copy of the GNU General Public License
4137 + * along with this program; if not, write to the Free Software
4138 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4140 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4143 +#include <linux/module.h>
4145 +#include <asm/mach-ralink/ralink_regs.h>
4147 +#include "ralink_soc_eth.h"
4148 +#include "mdio_rt2880.h"
4150 +#define SYSC_REG_RESET_CTRL 0x034
4151 +#define RT2880_RESET_FE BIT(18)
4153 +void rt2880_fe_reset(void)
4155 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4158 +struct fe_soc_data rt2880_data = {
4159 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4160 + .reset_fe = rt2880_fe_reset,
4161 + .min_pkt_len = 64,
4162 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4163 + .checksum_bit = RX_DMA_L4VALID,
4164 + .rx_dly_int = FE_RX_DLY_INT,
4165 + .tx_dly_int = FE_TX_DLY_INT,
4166 + .mdio_read = rt2880_mdio_read,
4167 + .mdio_write = rt2880_mdio_write,
4168 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4171 +const struct of_device_id of_fe_match[] = {
4172 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4176 +MODULE_DEVICE_TABLE(of, of_fe_match);
4178 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4181 + * This program is free software; you can redistribute it and/or modify
4182 + * it under the terms of the GNU General Public License as published by
4183 + * the Free Software Foundation; version 2 of the License
4185 + * This program is distributed in the hope that it will be useful,
4186 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4187 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4188 + * GNU General Public License for more details.
4190 + * You should have received a copy of the GNU General Public License
4191 + * along with this program; if not, write to the Free Software
4192 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4194 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4197 +#include <linux/module.h>
4199 +#include <asm/mach-ralink/ralink_regs.h>
4201 +#include "ralink_soc_eth.h"
4203 +#define RT305X_RESET_FE BIT(21)
4204 +#define RT305X_RESET_ESW BIT(23)
4205 +#define SYSC_REG_RESET_CTRL 0x034
4207 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4208 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4209 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4210 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4211 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4212 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4213 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4214 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4215 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4216 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4217 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4218 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4219 + [FE_REG_FE_DMA_VID_BASE] = 0,
4222 +static void rt305x_fe_reset(void)
4224 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4225 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4228 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4230 + unsigned long flags;
4232 + spin_lock_irqsave(&priv->page_lock, flags);
4233 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4234 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4235 + RT5350_SDM_MAC_ADRL);
4236 + spin_unlock_irqrestore(&priv->page_lock, flags);
4239 +static void rt5350_fwd_config(struct fe_priv *priv)
4241 + unsigned long sysclk = priv->sysclk;
4244 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4245 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4247 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4248 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4252 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4253 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4257 +static void rt5350_fe_reset(void)
4259 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4260 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4263 +static struct fe_soc_data rt3050_data = {
4264 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4265 + .reset_fe = rt305x_fe_reset,
4266 + .min_pkt_len = 64,
4267 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4268 + .checksum_bit = RX_DMA_L4VALID,
4269 + .rx_dly_int = FE_RX_DLY_INT,
4270 + .tx_dly_int = FE_TX_DLY_INT,
4273 +static struct fe_soc_data rt5350_data = {
4274 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4275 + .reg_table = rt5350_reg_table,
4276 + .reset_fe = rt5350_fe_reset,
4277 + .set_mac = rt5350_set_mac,
4278 + .fwd_config = rt5350_fwd_config,
4279 + .min_pkt_len = 64,
4280 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4281 + .checksum_bit = RX_DMA_L4VALID,
4282 + .rx_dly_int = RT5350_RX_DLY_INT,
4283 + .tx_dly_int = RT5350_TX_DLY_INT,
4286 +const struct of_device_id of_fe_match[] = {
4287 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4288 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4292 +MODULE_DEVICE_TABLE(of, of_fe_match);
4294 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4297 + * This program is free software; you can redistribute it and/or modify
4298 + * it under the terms of the GNU General Public License as published by
4299 + * the Free Software Foundation; version 2 of the License
4301 + * This program is distributed in the hope that it will be useful,
4302 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4303 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4304 + * GNU General Public License for more details.
4306 + * You should have received a copy of the GNU General Public License
4307 + * along with this program; if not, write to the Free Software
4308 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4310 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4313 +#include <linux/module.h>
4315 +#include <asm/mach-ralink/ralink_regs.h>
4317 +#include "ralink_soc_eth.h"
4318 +#include "mdio_rt2880.h"
4320 +#define RT3883_SYSC_REG_RSTCTRL 0x34
4321 +#define RT3883_RSTCTRL_FE BIT(21)
4323 +static void rt3883_fe_reset(void)
4327 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4328 + t |= RT3883_RSTCTRL_FE;
4329 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4331 + t &= ~RT3883_RSTCTRL_FE;
4332 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4335 +static struct fe_soc_data rt3883_data = {
4336 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4337 + .reset_fe = rt3883_fe_reset,
4338 + .min_pkt_len = 64,
4339 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4340 + .rx_dly_int = FE_RX_DLY_INT,
4341 + .tx_dly_int = FE_TX_DLY_INT,
4342 + .checksum_bit = RX_DMA_L4VALID,
4343 + .mdio_read = rt2880_mdio_read,
4344 + .mdio_write = rt2880_mdio_write,
4345 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4346 + .port_init = rt2880_port_init,
4349 +const struct of_device_id of_fe_match[] = {
4350 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4354 +MODULE_DEVICE_TABLE(of, of_fe_match);
4357 +++ b/drivers/net/ethernet/ralink/mt7530.c
4360 + * This program is free software; you can redistribute it and/or
4361 + * modify it under the terms of the GNU General Public License
4362 + * as published by the Free Software Foundation; either version 2
4363 + * of the License, or (at your option) any later version.
4365 + * This program is distributed in the hope that it will be useful,
4366 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4367 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4368 + * GNU General Public License for more details.
4370 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4373 +#include <linux/if.h>
4374 +#include <linux/module.h>
4375 +#include <linux/init.h>
4376 +#include <linux/list.h>
4377 +#include <linux/if_ether.h>
4378 +#include <linux/skbuff.h>
4379 +#include <linux/netdevice.h>
4380 +#include <linux/netlink.h>
4381 +#include <linux/bitops.h>
4382 +#include <net/genetlink.h>
4383 +#include <linux/switch.h>
4384 +#include <linux/delay.h>
4385 +#include <linux/phy.h>
4386 +#include <linux/netdevice.h>
4387 +#include <linux/etherdevice.h>
4388 +#include <linux/lockdep.h>
4389 +#include <linux/workqueue.h>
4390 +#include <linux/of_device.h>
4392 +#include "mt7530.h"
4394 +#define MT7530_CPU_PORT 6
4395 +#define MT7530_NUM_PORTS 7
4396 +#define MT7530_NUM_VLANS 16
4397 +#define MT7530_NUM_VIDS 16
4399 +#define REG_ESW_VLAN_VTCR 0x90
4400 +#define REG_ESW_VLAN_VAWD1 0x94
4401 +#define REG_ESW_VLAN_VAWD2 0x98
4404 + /* Global attributes. */
4405 + MT7530_ATTR_ENABLE_VLAN,
4408 +struct mt7530_port {
4412 +struct mt7530_vlan {
4416 +struct mt7530_priv {
4417 + void __iomem *base;
4418 + struct mii_bus *bus;
4419 + struct switch_dev swdev;
4421 + bool global_vlan_enable;
4422 + struct mt7530_vlan vlans[MT7530_NUM_VLANS];
4423 + struct mt7530_port ports[MT7530_NUM_PORTS];
4426 +struct mt7530_mapping {
4430 +} mt7530_defaults[] = {
4433 + .pvids = { 1, 1, 1, 1, 2, 1 },
4434 + .vlans = { 0, 0x6f, 0x50 },
4437 + .pvids = { 2, 1, 1, 1, 1, 1 },
4438 + .vlans = { 0, 0x7e, 0x41 },
4442 +struct mt7530_mapping*
4443 +mt7530_find_mapping(struct device_node *np)
4448 + if (of_property_read_string(np, "ralink,port-map", &map))
4451 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
4452 + if (!strcmp(map, mt7530_defaults[i].name))
4453 + return &mt7530_defaults[i];
4459 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
4463 + mt7530->global_vlan_enable = 1;
4465 + for (i = 0; i < 6; i++)
4466 + mt7530->ports[i].pvid = map->pvids[i];
4467 + for (i = 0; i < 8; i++)
4468 + mt7530->vlans[i].ports = map->vlans[i];
4472 +mt7530_reset_switch(struct switch_dev *dev)
4474 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4476 + memset(priv->ports, 0, sizeof(priv->ports));
4477 + memset(priv->vlans, 0, sizeof(priv->vlans));
4483 +mt7530_get_vlan_enable(struct switch_dev *dev,
4484 + const struct switch_attr *attr,
4485 + struct switch_val *val)
4487 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4489 + val->value.i = priv->global_vlan_enable;
4495 +mt7530_set_vlan_enable(struct switch_dev *dev,
4496 + const struct switch_attr *attr,
4497 + struct switch_val *val)
4499 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4501 + priv->global_vlan_enable = val->value.i != 0;
4507 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
4512 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4513 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
4514 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
4516 + return (high << 16) | (low & 0xffff);
4519 + return ioread32(priv->base + reg);
4523 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
4526 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4527 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
4528 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
4532 + iowrite32(val, priv->base + reg);
4536 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
4540 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
4542 + for (i = 0; i < 20; i++) {
4543 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
4545 + if ((val & BIT(31)) == 0)
4551 + printk("mt7530: vtcr timeout\n");
4555 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
4557 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4559 + if (port >= MT7530_NUM_PORTS)
4562 + *val = mt7530_r32(priv, 0x2014 + (0x100 * port));
4569 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
4571 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4573 + if (port >= MT7530_NUM_PORTS)
4576 + priv->ports[port].pvid = pvid;
4582 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4584 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4590 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS)
4593 + mt7530_vtcr(priv, 0, val->port_vlan);
4594 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
4598 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
4599 + struct switch_port *p;
4600 + if (!(member & BIT(i)))
4603 + p = &val->value.ports[val->len++];
4612 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4614 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4618 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS ||
4619 + val->len > MT7530_NUM_PORTS)
4622 + for (i = 0; i < val->len; i++) {
4623 + struct switch_port *p = &val->value.ports[i];
4625 + if (p->id >= MT7530_NUM_PORTS)
4628 + ports |= BIT(p->id);
4630 + priv->vlans[val->port_vlan].ports = ports;
4636 +mt7530_apply_config(struct switch_dev *dev)
4638 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4641 + if (!priv->global_vlan_enable) {
4642 + mt7530_w32(priv, 0x2004, 0xff000);
4643 + mt7530_w32(priv, 0x2104, 0xff000);
4644 + mt7530_w32(priv, 0x2204, 0xff000);
4645 + mt7530_w32(priv, 0x2304, 0xff000);
4646 + mt7530_w32(priv, 0x2404, 0xff000);
4647 + mt7530_w32(priv, 0x2504, 0xff000);
4648 + mt7530_w32(priv, 0x2604, 0xff000);
4649 + mt7530_w32(priv, 0x2010, 0x810000c);
4650 + mt7530_w32(priv, 0x2110, 0x810000c);
4651 + mt7530_w32(priv, 0x2210, 0x810000c);
4652 + mt7530_w32(priv, 0x2310, 0x810000c);
4653 + mt7530_w32(priv, 0x2410, 0x810000c);
4654 + mt7530_w32(priv, 0x2510, 0x810000c);
4655 + mt7530_w32(priv, 0x2610, 0x810000c);
4659 + // LAN/WAN ports as security mode
4660 + mt7530_w32(priv, 0x2004, 0xff0003);
4661 + mt7530_w32(priv, 0x2104, 0xff0003);
4662 + mt7530_w32(priv, 0x2204, 0xff0003);
4663 + mt7530_w32(priv, 0x2304, 0xff0003);
4664 + mt7530_w32(priv, 0x2404, 0xff0003);
4665 + mt7530_w32(priv, 0x2504, 0xff0003);
4666 + // LAN/WAN ports as transparent port
4667 + mt7530_w32(priv, 0x2010, 0x810000c0);
4668 + mt7530_w32(priv, 0x2110, 0x810000c0);
4669 + mt7530_w32(priv, 0x2210, 0x810000c0);
4670 + mt7530_w32(priv, 0x2310, 0x810000c0);
4671 + mt7530_w32(priv, 0x2410, 0x810000c0);
4672 + mt7530_w32(priv, 0x2510, 0x810000c0);
4674 + // set CPU/P7 port as user port
4675 + mt7530_w32(priv, 0x2610, 0x81000000);
4676 + mt7530_w32(priv, 0x2710, 0x81000000);
4678 + mt7530_w32(priv, 0x2604, 0x20ff0003);
4679 + mt7530_w32(priv, 0x2704, 0x20ff0003);
4680 + mt7530_w32(priv, 0x2610, 0x81000000);
4682 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
4683 + u8 ports = priv->vlans[i].ports;
4684 + u32 val = mt7530_r32(priv, 0x100 + 4 * (i / 2));
4693 + mt7530_w32(priv, 0x100 + 4 * (i / 2), val);
4696 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, BIT(30) | (ports << 16) | BIT(0));
4698 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
4700 + mt7530_vtcr(priv, 1, i);
4703 + for (i = 0; i < MT7530_NUM_PORTS; i++)
4704 + mt7530_w32(priv, 0x2014 + (0x100 * i), 0x10000 | priv->ports[i].pvid);
4710 +mt7530_get_port_link(struct switch_dev *dev, int port,
4711 + struct switch_port_link *link)
4713 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4716 + if (port < 0 || port >= MT7530_NUM_PORTS)
4719 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
4721 + link->link = pmsr & 1;
4722 + link->duplex = (pmsr >> 1) & 1;
4723 + speed = (pmsr >> 2) & 3;
4727 + link->speed = SWITCH_PORT_SPEED_10;
4730 + link->speed = SWITCH_PORT_SPEED_100;
4733 + case 3: /* forced gige speed can be 2 or 3 */
4734 + link->speed = SWITCH_PORT_SPEED_1000;
4737 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
4744 +static const struct switch_attr mt7530_global[] = {
4746 + .type = SWITCH_TYPE_INT,
4747 + .name = "enable_vlan",
4748 + .description = "VLAN mode (1:enabled)",
4750 + .id = MT7530_ATTR_ENABLE_VLAN,
4751 + .get = mt7530_get_vlan_enable,
4752 + .set = mt7530_set_vlan_enable,
4756 +static const struct switch_attr mt7530_port[] = {
4759 +static const struct switch_attr mt7530_vlan[] = {
4762 +static const struct switch_dev_ops mt7530_ops = {
4764 + .attr = mt7530_global,
4765 + .n_attr = ARRAY_SIZE(mt7530_global),
4768 + .attr = mt7530_port,
4769 + .n_attr = ARRAY_SIZE(mt7530_port),
4772 + .attr = mt7530_vlan,
4773 + .n_attr = ARRAY_SIZE(mt7530_vlan),
4775 + .get_vlan_ports = mt7530_get_vlan_ports,
4776 + .set_vlan_ports = mt7530_set_vlan_ports,
4777 + .get_port_pvid = mt7530_get_port_pvid,
4778 + .set_port_pvid = mt7530_set_port_pvid,
4779 + .get_port_link = mt7530_get_port_link,
4780 + .apply_config = mt7530_apply_config,
4781 + .reset_switch = mt7530_reset_switch,
4785 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
4787 + struct switch_dev *swdev;
4788 + struct mt7530_priv *mt7530;
4789 + struct mt7530_mapping *map;
4792 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
4795 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
4799 + mt7530->base = base;
4800 + mt7530->bus = bus;
4801 + mt7530->global_vlan_enable = 1;
4803 + swdev = &mt7530->swdev;
4804 + swdev->name = "mt7530";
4805 + swdev->alias = "mt7530";
4806 + swdev->cpu_port = MT7530_CPU_PORT;
4807 + swdev->ports = MT7530_NUM_PORTS;
4808 + swdev->vlans = MT7530_NUM_VLANS;
4809 + swdev->ops = &mt7530_ops;
4811 + ret = register_switch(swdev, NULL);
4813 + dev_err(dev, "failed to register mt7530\n");
4817 + dev_info(dev, "loaded mt7530 driver\n");
4819 + map = mt7530_find_mapping(dev->of_node);
4821 + mt7530_apply_mapping(mt7530, map);
4822 + mt7530_apply_config(swdev);
4827 +++ b/drivers/net/ethernet/ralink/mt7530.h
4830 + * This program is free software; you can redistribute it and/or
4831 + * modify it under the terms of the GNU General Public License
4832 + * as published by the Free Software Foundation; either version 2
4833 + * of the License, or (at your option) any later version.
4835 + * This program is distributed in the hope that it will be useful,
4836 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4837 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4838 + * GNU General Public License for more details.
4840 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4843 +#ifndef _MT7530_H__
4844 +#define _MT7530_H__
4846 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);