1 #ifndef __MTK_PHY_NEW_H
2 #define __MTK_PHY_NEW_H
4 //#define CONFIG_U3D_HAL_SUPPORT
6 /* include system library */
8 #include <linux/kernel.h>
9 #include <linux/slab.h>
10 #include <linux/delay.h>
12 /* Choose PHY R/W implementation */
13 //#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
14 #define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
16 /* Choose PHY version */
17 //Select your project by defining one of the followings
18 #define CONFIG_PROJECT_7621 //7621
19 #define CONFIG_PROJECT_PHY
21 /* BASE ADDRESS DEFINE, should define this on ASIC */
22 #define PHY_BASE 0xBE1D0000
23 #define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
24 #define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
25 #define U2_PHY_BASE (PHY_BASE+0x800)
26 #define U3_PHYD_BASE (PHY_BASE+0x900)
27 #define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
28 #define U3_PHYA_BASE (PHY_BASE+0xb00)
29 #define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
31 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
32 #define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
33 #define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
34 #define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
35 #define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
36 #define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
37 #define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
38 #define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
43 0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
44 0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
45 0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
46 0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
47 0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
48 0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
49 0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
54 typedef unsigned int PHY_UINT32;
55 typedef int PHY_INT32;
56 typedef unsigned short PHY_UINT16;
57 typedef short PHY_INT16;
58 typedef unsigned char PHY_UINT8;
59 typedef char PHY_INT8;
61 typedef PHY_UINT32 __bitwise PHY_LE32;
68 #define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
69 #define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
71 #define DRV_MDELAY mdelay
72 #define DRV_MSLEEP msleep
73 #define DRV_UDELAY udelay
74 #define DRV_USLEEP usleep
76 /* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
77 PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
78 PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
79 PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
80 PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
82 /* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
83 PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
84 PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
85 PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
86 PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
89 PHY_INT32 phy_version;
90 PHY_INT32 phyd_version_addr;
92 #ifdef CONFIG_PROJECT_PHY
93 struct u2phy_reg *u2phy_regs;
94 struct u3phya_reg *u3phya_regs;
95 struct u3phya_da_reg *u3phya_da_regs;
96 struct u3phyd_reg *u3phyd_regs;
97 struct u3phyd_bank2_reg *u3phyd_bank2_regs;
98 struct sifslv_chip_reg *sifslv_chip_regs;
99 struct sifslv_fm_feg *sifslv_fm_regs;
103 struct u3phy_operator {
104 PHY_INT32 (*init) (struct u3phy_info *info);
105 PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
106 PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
107 PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
108 PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
109 PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
110 PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
116 #define AUTOEXT extern
119 AUTOEXT struct u3phy_info *u3phy;
120 AUTOEXT struct u3phy_info *u3phy_p1;
121 AUTOEXT struct u3phy_operator *u3phy_ops;
123 /*********eye scan required*********/
125 #define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
126 #define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
134 struct strucScanRegion
144 struct strucTestCycle
147 PHY_INT8 bNumOfEyeCnt;
149 PHY_INT8 bNumOfIgnoreCnt;
152 #define ERRCNT_MAX 128
153 #define CYCLE_COUNT_MAX 15
155 /// the map resolution is 128 x 128 pts
161 PHY_INT32 u3phy_init(void);
163 AUTOEXT struct strucScanRegion _rEye1;
164 AUTOEXT struct strucScanRegion _rEye2;
165 AUTOEXT struct strucTestCycle _rTestCycle;
166 AUTOEXT PHY_UINT8 _bXcurr;
167 AUTOEXT PHY_UINT8 _bYcurr;
168 AUTOEXT enumScanDir _eScanDir;
169 AUTOEXT PHY_INT8 _fgXChged;
170 AUTOEXT PHY_INT8 _bPIResult;
171 /* use local variable instead to save memory use */
173 AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
174 AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
177 /***********************************/