2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
36 #include <asm/mach-ralink/ralink_regs.h>
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
41 #include "ralink_ethtool.h"
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
62 #define SYSC_REG_RSTCTRL 0x34
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
87 static const u16 *fe_reg_table = fe_reg_table_default;
91 void (*action)(struct fe_priv *);
94 static void __iomem *fe_base = 0;
96 void fe_w32(u32 val, unsigned reg)
98 __raw_writel(val, fe_base + reg);
101 u32 fe_r32(unsigned reg)
103 return __raw_readl(fe_base + reg);
106 void fe_reg_w32(u32 val, enum fe_reg reg)
108 fe_w32(val, fe_reg_table[reg]);
111 u32 fe_reg_r32(enum fe_reg reg)
113 return fe_r32(fe_reg_table[reg]);
116 void fe_reset(u32 reset_bits)
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
130 static inline void fe_int_disable(u32 mask)
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
138 static inline void fe_int_enable(u32 mask)
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
154 spin_unlock_irqrestore(&priv->page_lock, flags);
157 static int fe_set_mac_address(struct net_device *dev, void *p)
159 int ret = eth_mac_addr(dev, p);
162 struct fe_priv *priv = netdev_priv(dev);
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
167 fe_hw_set_macaddr(priv, p);
173 static inline int fe_max_frag_size(int mtu)
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
179 static inline int fe_max_buf_size(int frag_size)
181 return frag_size - NET_SKB_PAD - NET_IP_ALIGN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
193 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
195 dma_txd->txd1 = txd->txd1;
196 dma_txd->txd3 = txd->txd3;
197 dma_txd->txd4 = txd->txd4;
198 /* clean dma done flag last */
199 dma_txd->txd2 = txd->txd2;
202 static void fe_clean_rx(struct fe_priv *priv)
205 struct fe_rx_ring *ring = &priv->rx_ring;
208 for (i = 0; i < ring->rx_ring_size; i++)
209 if (ring->rx_data[i]) {
210 if (ring->rx_dma && ring->rx_dma[i].rxd1)
211 dma_unmap_single(&priv->netdev->dev,
212 ring->rx_dma[i].rxd1,
215 put_page(virt_to_head_page(ring->rx_data[i]));
218 kfree(ring->rx_data);
219 ring->rx_data = NULL;
223 dma_free_coherent(&priv->netdev->dev,
224 ring->rx_ring_size * sizeof(*ring->rx_dma),
231 static int fe_alloc_rx(struct fe_priv *priv)
233 struct net_device *netdev = priv->netdev;
234 struct fe_rx_ring *ring = &priv->rx_ring;
237 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
242 for (i = 0; i < ring->rx_ring_size; i++) {
243 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
244 if (!ring->rx_data[i])
248 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
249 ring->rx_ring_size * sizeof(*ring->rx_dma),
251 GFP_ATOMIC | __GFP_ZERO);
255 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
259 for (i = 0; i < ring->rx_ring_size; i++) {
260 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
261 ring->rx_data[i] + NET_SKB_PAD + pad,
264 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
266 ring->rx_dma[i].rxd1 = (unsigned int) dma_addr;
268 if (priv->flags & FE_FLAG_RX_SG_DMA)
269 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
271 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
273 ring->rx_calc_idx = ring->rx_ring_size - 1;
276 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
277 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
278 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
279 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
287 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
289 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
290 dma_unmap_single(dev,
291 dma_unmap_addr(tx_buf, dma_addr0),
292 dma_unmap_len(tx_buf, dma_len0),
294 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
296 dma_unmap_addr(tx_buf, dma_addr0),
297 dma_unmap_len(tx_buf, dma_len0),
300 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
302 dma_unmap_addr(tx_buf, dma_addr1),
303 dma_unmap_len(tx_buf, dma_len1),
307 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
308 dev_kfree_skb_any(tx_buf->skb);
313 static void fe_clean_tx(struct fe_priv *priv)
316 struct device *dev = &priv->netdev->dev;
317 struct fe_tx_ring *ring = &priv->tx_ring;
320 for (i = 0; i < ring->tx_ring_size; i++)
321 fe_txd_unmap(dev, &ring->tx_buf[i]);
327 dma_free_coherent(dev,
328 ring->tx_ring_size * sizeof(*ring->tx_dma),
334 netdev_reset_queue(priv->netdev);
337 static int fe_alloc_tx(struct fe_priv *priv)
340 struct fe_tx_ring *ring = &priv->tx_ring;
342 ring->tx_free_idx = 0;
343 ring->tx_next_idx = 0;
344 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
346 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
351 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
352 ring->tx_ring_size * sizeof(*ring->tx_dma),
354 GFP_ATOMIC | __GFP_ZERO);
358 for (i = 0; i < ring->tx_ring_size; i++) {
359 if (priv->soc->tx_dma) {
360 priv->soc->tx_dma(&ring->tx_dma[i]);
362 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
366 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
367 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
368 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
369 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
377 static int fe_init_dma(struct fe_priv *priv)
381 err = fe_alloc_tx(priv);
385 err = fe_alloc_rx(priv);
392 static void fe_free_dma(struct fe_priv *priv)
398 void fe_stats_update(struct fe_priv *priv)
400 struct fe_hw_stats *hwstats = priv->hw_stats;
401 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
404 u64_stats_update_begin(&hwstats->syncp);
406 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
407 hwstats->rx_bytes += fe_r32(base);
408 stats = fe_r32(base + 0x04);
410 hwstats->rx_bytes += (stats << 32);
411 hwstats->rx_packets += fe_r32(base + 0x08);
412 hwstats->rx_overflow += fe_r32(base + 0x10);
413 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
414 hwstats->rx_short_errors += fe_r32(base + 0x18);
415 hwstats->rx_long_errors += fe_r32(base + 0x1c);
416 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
417 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
418 hwstats->tx_skip += fe_r32(base + 0x28);
419 hwstats->tx_collisions += fe_r32(base + 0x2c);
420 hwstats->tx_bytes += fe_r32(base + 0x30);
421 stats = fe_r32(base + 0x34);
423 hwstats->tx_bytes += (stats << 32);
424 hwstats->tx_packets += fe_r32(base + 0x38);
426 hwstats->tx_bytes += fe_r32(base);
427 hwstats->tx_packets += fe_r32(base + 0x04);
428 hwstats->tx_skip += fe_r32(base + 0x08);
429 hwstats->tx_collisions += fe_r32(base + 0x0c);
430 hwstats->rx_bytes += fe_r32(base + 0x20);
431 hwstats->rx_packets += fe_r32(base + 0x24);
432 hwstats->rx_overflow += fe_r32(base + 0x28);
433 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
434 hwstats->rx_short_errors += fe_r32(base + 0x30);
435 hwstats->rx_long_errors += fe_r32(base + 0x34);
436 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
437 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
440 u64_stats_update_end(&hwstats->syncp);
443 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
444 struct rtnl_link_stats64 *storage)
446 struct fe_priv *priv = netdev_priv(dev);
447 struct fe_hw_stats *hwstats = priv->hw_stats;
448 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
452 netdev_stats_to_stats64(storage, &dev->stats);
456 if (netif_running(dev) && netif_device_present(dev)) {
457 if (spin_trylock(&hwstats->stats_lock)) {
458 fe_stats_update(priv);
459 spin_unlock(&hwstats->stats_lock);
464 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
465 storage->rx_packets = hwstats->rx_packets;
466 storage->tx_packets = hwstats->tx_packets;
467 storage->rx_bytes = hwstats->rx_bytes;
468 storage->tx_bytes = hwstats->tx_bytes;
469 storage->collisions = hwstats->tx_collisions;
470 storage->rx_length_errors = hwstats->rx_short_errors +
471 hwstats->rx_long_errors;
472 storage->rx_over_errors = hwstats->rx_overflow;
473 storage->rx_crc_errors = hwstats->rx_fcs_errors;
474 storage->rx_errors = hwstats->rx_checksum_errors;
475 storage->tx_aborted_errors = hwstats->tx_skip;
476 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
478 storage->tx_errors = priv->netdev->stats.tx_errors;
479 storage->rx_dropped = priv->netdev->stats.rx_dropped;
480 storage->tx_dropped = priv->netdev->stats.tx_dropped;
485 static int fe_vlan_rx_add_vid(struct net_device *dev,
486 __be16 proto, u16 vid)
488 struct fe_priv *priv = netdev_priv(dev);
489 u32 idx = (vid & 0xf);
492 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
493 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
496 if (test_bit(idx, &priv->vlan_map)) {
497 netdev_warn(dev, "disable tx vlan offload\n");
498 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
499 netdev_update_features(dev);
501 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
505 vlan_cfg |= (vid << 16);
507 vlan_cfg &= 0xffff0000;
510 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
512 set_bit(idx, &priv->vlan_map);
518 static int fe_vlan_rx_kill_vid(struct net_device *dev,
519 __be16 proto, u16 vid)
521 struct fe_priv *priv = netdev_priv(dev);
522 u32 idx = (vid & 0xf);
524 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
525 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
528 clear_bit(idx, &priv->vlan_map);
533 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
536 return (u32)(ring->tx_ring_size -
537 ((ring->tx_next_idx - ring->tx_free_idx) &
538 (ring->tx_ring_size - 1)));
541 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
542 int tx_num, struct fe_tx_ring *ring)
544 struct fe_priv *priv = netdev_priv(dev);
545 struct skb_frag_struct *frag;
546 struct fe_tx_dma txd, *ptxd;
547 struct fe_tx_buf *tx_buf;
548 dma_addr_t mapped_addr;
549 unsigned int nr_frags;
551 int i, j, k, frag_size, frag_map_size, offset;
553 tx_buf = &ring->tx_buf[ring->tx_next_idx];
554 memset(tx_buf, 0, sizeof(*tx_buf));
555 memset(&txd, 0, sizeof(txd));
556 nr_frags = skb_shinfo(skb)->nr_frags;
558 /* init tx descriptor */
559 if (priv->soc->tx_dma)
560 priv->soc->tx_dma(&txd);
562 txd.txd4 = TX_DMA_DESP4_DEF;
565 /* TX Checksum offload */
566 if (skb->ip_summed == CHECKSUM_PARTIAL)
567 txd.txd4 |= TX_DMA_CHKSUM;
569 /* VLAN header offload */
570 if (vlan_tx_tag_present(skb)) {
571 if (IS_ENABLED(CONFIG_SOC_MT7621))
572 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
574 txd.txd4 |= TX_DMA_INS_VLAN |
575 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
576 (vlan_tx_tag_get(skb) & 0xF);
579 /* TSO: fill MSS info in tcp checksum field */
580 if (skb_is_gso(skb)) {
581 if (skb_cow_head(skb, 0)) {
582 netif_warn(priv, tx_err, dev,
583 "GSO expand head fail.\n");
586 if (skb_shinfo(skb)->gso_type &
587 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
588 txd.txd4 |= TX_DMA_TSO;
589 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
593 mapped_addr = dma_map_single(&dev->dev, skb->data,
594 skb_headlen(skb), DMA_TO_DEVICE);
595 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
597 txd.txd1 = mapped_addr;
598 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
600 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
601 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
602 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
605 j = ring->tx_next_idx;
607 for (i = 0; i < nr_frags; i++) {
609 frag = &skb_shinfo(skb)->frags[i];
610 frag_size = skb_frag_size(frag);
612 while (frag_size > 0) {
613 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
614 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
615 frag_map_size, DMA_TO_DEVICE);
616 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
620 j = NEXT_TX_DESP_IDX(j);
621 txd.txd1 = mapped_addr;
622 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
625 tx_buf = &ring->tx_buf[j];
626 memset(tx_buf, 0, sizeof(*tx_buf));
628 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
629 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
630 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
632 txd.txd3 = mapped_addr;
633 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
635 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
636 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
637 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
638 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
640 if (!((i == (nr_frags -1)) &&
641 (frag_map_size == frag_size))) {
642 fe_set_txd(&txd, &ring->tx_dma[j]);
643 memset(&txd, 0, sizeof(txd));
646 frag_size -= frag_map_size;
647 offset += frag_map_size;
652 /* set last segment */
654 txd.txd2 |= TX_DMA_LS1;
656 txd.txd2 |= TX_DMA_LS0;
657 fe_set_txd(&txd, &ring->tx_dma[j]);
659 /* store skb to cleanup */
662 netdev_sent_queue(dev, skb->len);
663 skb_tx_timestamp(skb);
665 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
667 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
668 netif_stop_queue(dev);
670 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
671 netif_wake_queue(dev);
674 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
675 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
680 j = ring->tx_next_idx;
681 for (i = 0; i < tx_num; i++) {
682 ptxd = &ring->tx_dma[j];
683 tx_buf = &ring->tx_buf[j];
686 fe_txd_unmap(&dev->dev, tx_buf);
688 ptxd->txd2 = TX_DMA_DESP2_DEF;
689 j = NEXT_TX_DESP_IDX(j);
697 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
702 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
703 if ((priv->flags & FE_FLAG_PADDING_64B) &&
704 !(priv->flags & FE_FLAG_PADDING_BUG))
707 if (vlan_tx_tag_present(skb))
709 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
711 else if(!(priv->flags & FE_FLAG_PADDING_64B))
716 if (skb->len < len) {
717 if ((ret = skb_pad(skb, len - skb->len)) < 0)
720 skb_set_tail_pointer(skb, len);
727 static inline int fe_cal_txd_req(struct sk_buff *skb)
730 struct skb_frag_struct *frag;
733 if (skb_is_gso(skb)) {
734 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
735 frag = &skb_shinfo(skb)->frags[i];
736 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
739 nfrags += skb_shinfo(skb)->nr_frags;
742 return DIV_ROUND_UP(nfrags, 2);
745 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
747 struct fe_priv *priv = netdev_priv(dev);
748 struct fe_tx_ring *ring = &priv->tx_ring;
749 struct net_device_stats *stats = &dev->stats;
753 if (fe_skb_padto(skb, priv)) {
754 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
758 tx_num = fe_cal_txd_req(skb);
759 if (unlikely(fe_empty_txd(ring) <= tx_num))
761 netif_stop_queue(dev);
762 netif_err(priv, tx_queued,dev,
763 "Tx Ring full when queue awake!\n");
764 return NETDEV_TX_BUSY;
767 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
771 stats->tx_bytes += len;
777 static inline void fe_rx_vlan(struct sk_buff *skb)
782 if (!__vlan_get_tag(skb, &vlanid)) {
783 /* pop the vlan tag */
784 ehdr = (struct ethhdr *)skb->data;
785 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
786 skb_pull(skb, VLAN_HLEN);
787 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
791 static int fe_poll_rx(struct napi_struct *napi, int budget,
792 struct fe_priv *priv, u32 rx_intr)
794 struct net_device *netdev = priv->netdev;
795 struct net_device_stats *stats = &netdev->stats;
796 struct fe_soc_data *soc = priv->soc;
797 struct fe_rx_ring *ring = &priv->rx_ring;
798 int idx = ring->rx_calc_idx;
802 struct fe_rx_dma *rxd, trxd;
804 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
806 if (netdev->features & NETIF_F_RXCSUM)
807 checksum_bit = soc->checksum_bit;
811 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
816 while (done < budget) {
819 idx = NEXT_RX_DESP_IDX(idx);
820 rxd = &ring->rx_dma[idx];
821 data = ring->rx_data[idx];
823 fe_get_rxd(&trxd, rxd);
824 if (!(trxd.rxd2 & RX_DMA_DONE))
827 /* alloc new buffer */
828 new_data = netdev_alloc_frag(ring->frag_size);
829 if (unlikely(!new_data)) {
833 dma_addr = dma_map_single(&netdev->dev,
834 new_data + NET_SKB_PAD + pad,
837 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
838 put_page(virt_to_head_page(new_data));
843 skb = build_skb(data, ring->frag_size);
844 if (unlikely(!skb)) {
845 put_page(virt_to_head_page(new_data));
848 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
850 dma_unmap_single(&netdev->dev, trxd.rxd1,
851 ring->rx_buf_size, DMA_FROM_DEVICE);
852 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
854 skb_put(skb, pktlen);
855 if (trxd.rxd4 & checksum_bit) {
856 skb->ip_summed = CHECKSUM_UNNECESSARY;
858 skb_checksum_none_assert(skb);
862 skb->protocol = eth_type_trans(skb, netdev);
865 stats->rx_bytes += pktlen;
867 napi_gro_receive(napi, skb);
869 ring->rx_data[idx] = new_data;
870 rxd->rxd1 = (unsigned int) dma_addr;
873 if (priv->flags & FE_FLAG_RX_SG_DMA)
874 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
876 rxd->rxd2 = RX_DMA_LSO;
878 ring->rx_calc_idx = idx;
880 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
885 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
890 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
893 struct net_device *netdev = priv->netdev;
894 struct device *dev = &netdev->dev;
895 unsigned int bytes_compl = 0;
897 struct fe_tx_buf *tx_buf;
900 struct fe_tx_ring *ring = &priv->tx_ring;
902 idx = ring->tx_free_idx;
903 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
905 while ((idx != hwidx) && budget) {
906 tx_buf = &ring->tx_buf[idx];
912 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
913 bytes_compl += skb->len;
917 fe_txd_unmap(dev, tx_buf);
918 idx = NEXT_TX_DESP_IDX(idx);
920 ring->tx_free_idx = idx;
923 /* read hw index again make sure no new tx packet */
924 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
926 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
933 netdev_completed_queue(netdev, done, bytes_compl);
935 if (unlikely(netif_queue_stopped(netdev) &&
936 (fe_empty_txd(ring) > ring->tx_thresh)))
937 netif_wake_queue(netdev);
943 static int fe_poll(struct napi_struct *napi, int budget)
945 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
946 struct fe_hw_stats *hwstat = priv->hw_stats;
947 int tx_done, rx_done, tx_again;
948 u32 status, fe_status, status_reg, mask;
949 u32 tx_intr, rx_intr, status_intr;
951 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
952 tx_intr = priv->soc->tx_int;
953 rx_intr = priv->soc->rx_int;
954 status_intr = priv->soc->status_int;
955 tx_done = rx_done = tx_again = 0;
957 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
958 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
959 status_reg = FE_REG_FE_INT_STATUS2;
961 status_reg = FE_REG_FE_INT_STATUS;
963 if (status & tx_intr)
964 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
966 if (status & rx_intr)
967 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
969 if (unlikely(fe_status & status_intr)) {
970 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
971 fe_stats_update(priv);
972 spin_unlock(&hwstat->stats_lock);
974 fe_reg_w32(status_intr, status_reg);
977 if (unlikely(netif_msg_intr(priv))) {
978 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
979 netdev_info(priv->netdev,
980 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
981 tx_done, rx_done, status, mask);
984 if (!tx_again && (rx_done < budget)) {
985 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
986 if (status & (tx_intr | rx_intr ))
990 fe_int_enable(tx_intr | rx_intr);
997 static void fe_tx_timeout(struct net_device *dev)
999 struct fe_priv *priv = netdev_priv(dev);
1000 struct fe_tx_ring *ring = &priv->tx_ring;
1002 priv->netdev->stats.tx_errors++;
1003 netif_err(priv, tx_err, dev,
1004 "transmit timed out\n");
1005 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1006 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1007 netif_info(priv, drv, dev, "tx_ring=%d, " \
1008 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1009 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1010 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1011 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1012 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1016 netif_info(priv, drv, dev, "rx_ring=%d, " \
1017 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1018 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1019 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1020 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1021 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1024 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1025 schedule_work(&priv->pending_work);
1028 static irqreturn_t fe_handle_irq(int irq, void *dev)
1030 struct fe_priv *priv = netdev_priv(dev);
1031 u32 status, int_mask;
1033 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1035 if (unlikely(!status))
1038 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1039 if (likely(status & int_mask)) {
1040 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1041 fe_int_disable(int_mask);
1042 __napi_schedule(&priv->rx_napi);
1045 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1051 #ifdef CONFIG_NET_POLL_CONTROLLER
1052 static void fe_poll_controller(struct net_device *dev)
1054 struct fe_priv *priv = netdev_priv(dev);
1055 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1057 fe_int_disable(int_mask);
1058 fe_handle_irq(dev->irq, dev);
1059 fe_int_enable(int_mask);
1063 int fe_set_clock_cycle(struct fe_priv *priv)
1065 unsigned long sysclk = priv->sysclk;
1071 sysclk /= FE_US_CYC_CNT_DIVISOR;
1072 sysclk <<= FE_US_CYC_CNT_SHIFT;
1074 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1075 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1081 void fe_fwd_config(struct fe_priv *priv)
1085 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1087 /* disable jumbo frame */
1088 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1089 fwd_cfg &= ~FE_GDM1_JMB_EN;
1091 /* set unicast/multicast/broadcast frame to cpu */
1094 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1097 static void fe_rxcsum_config(bool enable)
1100 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1101 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1104 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1105 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1109 static void fe_txcsum_config(bool enable)
1112 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1113 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1116 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1117 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1121 void fe_csum_config(struct fe_priv *priv)
1123 struct net_device *dev = priv_netdev(priv);
1125 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1126 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1129 static int fe_hw_init(struct net_device *dev)
1131 struct fe_priv *priv = netdev_priv(dev);
1134 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1135 dev_name(priv->device), dev);
1139 if (priv->soc->set_mac)
1140 priv->soc->set_mac(priv, dev->dev_addr);
1142 fe_hw_set_macaddr(priv, dev->dev_addr);
1144 /* disable delay interrupt */
1145 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1147 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1149 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1150 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1151 for (i = 0; i < 16; i += 2)
1152 fe_w32(((i + 1) << 16) + i,
1153 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1156 BUG_ON(!priv->soc->fwd_config);
1157 if (priv->soc->fwd_config(priv))
1158 netdev_err(dev, "unable to get clock\n");
1160 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1161 fe_reg_w32(1, FE_REG_FE_RST_GL);
1162 fe_reg_w32(0, FE_REG_FE_RST_GL);
1168 static int fe_open(struct net_device *dev)
1170 struct fe_priv *priv = netdev_priv(dev);
1171 unsigned long flags;
1175 err = fe_init_dma(priv);
1179 spin_lock_irqsave(&priv->page_lock, flags);
1181 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1182 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1183 val |= FE_RX_2B_OFFSET;
1184 val |= priv->soc->pdma_glo_cfg;
1185 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1187 spin_unlock_irqrestore(&priv->page_lock, flags);
1190 priv->phy->start(priv);
1192 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1193 netif_carrier_on(dev);
1195 napi_enable(&priv->rx_napi);
1196 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1197 netif_start_queue(dev);
1206 static int fe_stop(struct net_device *dev)
1208 struct fe_priv *priv = netdev_priv(dev);
1209 unsigned long flags;
1212 netif_tx_disable(dev);
1213 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1214 napi_disable(&priv->rx_napi);
1217 priv->phy->stop(priv);
1219 spin_lock_irqsave(&priv->page_lock, flags);
1221 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1222 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1223 FE_REG_PDMA_GLO_CFG);
1224 spin_unlock_irqrestore(&priv->page_lock, flags);
1227 for (i = 0; i < 10; i++) {
1228 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1229 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1241 static int __init fe_init(struct net_device *dev)
1243 struct fe_priv *priv = netdev_priv(dev);
1244 struct device_node *port;
1247 BUG_ON(!priv->soc->reset_fe);
1248 priv->soc->reset_fe();
1250 if (priv->soc->switch_init)
1251 priv->soc->switch_init(priv);
1253 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1254 /*If the mac address is invalid, use random mac address */
1255 if (!is_valid_ether_addr(dev->dev_addr)) {
1256 random_ether_addr(dev->dev_addr);
1257 dev_err(priv->device, "generated random MAC address %pM\n",
1261 err = fe_mdio_init(priv);
1265 if (priv->soc->port_init)
1266 for_each_child_of_node(priv->device->of_node, port)
1267 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1268 priv->soc->port_init(priv, port);
1271 err = priv->phy->connect(priv);
1273 goto err_phy_disconnect;
1276 err = fe_hw_init(dev);
1278 goto err_phy_disconnect;
1280 if (priv->soc->switch_config)
1281 priv->soc->switch_config(priv);
1287 priv->phy->disconnect(priv);
1288 fe_mdio_cleanup(priv);
1293 static void fe_uninit(struct net_device *dev)
1295 struct fe_priv *priv = netdev_priv(dev);
1298 priv->phy->disconnect(priv);
1299 fe_mdio_cleanup(priv);
1301 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1302 free_irq(dev->irq, dev);
1305 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1307 struct fe_priv *priv = netdev_priv(dev);
1314 return phy_ethtool_ioctl(priv->phy_dev,
1315 (void *) ifr->ifr_data);
1319 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1327 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1329 struct fe_priv *priv = netdev_priv(dev);
1330 int frag_size, old_mtu;
1333 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1334 return eth_change_mtu(dev, new_mtu);
1336 frag_size = fe_max_frag_size(new_mtu);
1337 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1343 /* return early if the buffer sizes will not change */
1344 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1346 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1349 if (new_mtu <= ETH_DATA_LEN)
1350 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1352 priv->rx_ring.frag_size = PAGE_SIZE;
1353 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1355 if (!netif_running(dev))
1359 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1360 if (new_mtu <= ETH_DATA_LEN)
1361 fwd_cfg &= ~FE_GDM1_JMB_EN;
1363 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1364 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1365 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1367 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1369 return fe_open(dev);
1372 static const struct net_device_ops fe_netdev_ops = {
1373 .ndo_init = fe_init,
1374 .ndo_uninit = fe_uninit,
1375 .ndo_open = fe_open,
1376 .ndo_stop = fe_stop,
1377 .ndo_start_xmit = fe_start_xmit,
1378 .ndo_set_mac_address = fe_set_mac_address,
1379 .ndo_validate_addr = eth_validate_addr,
1380 .ndo_do_ioctl = fe_do_ioctl,
1381 .ndo_change_mtu = fe_change_mtu,
1382 .ndo_tx_timeout = fe_tx_timeout,
1383 .ndo_get_stats64 = fe_get_stats64,
1384 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1385 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1386 #ifdef CONFIG_NET_POLL_CONTROLLER
1387 .ndo_poll_controller = fe_poll_controller,
1391 static void fe_reset_pending(struct fe_priv *priv)
1393 struct net_device *dev = priv->netdev;
1406 netif_alert(priv, ifup, dev,
1407 "Driver up/down cycle failed, closing device.\n");
1412 static const struct fe_work_t fe_work[] = {
1413 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1416 static void fe_pending_work(struct work_struct *work)
1418 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1422 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1423 pending = test_and_clear_bit(fe_work[i].bitnr,
1424 priv->pending_flags);
1426 fe_work[i].action(priv);
1430 static int fe_probe(struct platform_device *pdev)
1432 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1433 const struct of_device_id *match;
1434 struct fe_soc_data *soc;
1435 struct net_device *netdev;
1436 struct fe_priv *priv;
1438 int err, napi_weight;
1440 device_reset(&pdev->dev);
1442 match = of_match_device(of_fe_match, &pdev->dev);
1443 soc = (struct fe_soc_data *) match->data;
1446 fe_reg_table = soc->reg_table;
1448 soc->reg_table = fe_reg_table;
1450 fe_base = devm_ioremap_resource(&pdev->dev, res);
1452 err = -EADDRNOTAVAIL;
1456 netdev = alloc_etherdev(sizeof(*priv));
1458 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1463 SET_NETDEV_DEV(netdev, &pdev->dev);
1464 netdev->netdev_ops = &fe_netdev_ops;
1465 netdev->base_addr = (unsigned long) fe_base;
1467 netdev->irq = platform_get_irq(pdev, 0);
1468 if (netdev->irq < 0) {
1469 dev_err(&pdev->dev, "no IRQ resource found\n");
1475 soc->init_data(soc, netdev);
1476 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1477 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1478 netdev->vlan_features = netdev->hw_features &
1479 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1480 netdev->features |= netdev->hw_features;
1482 /* fake rx vlan filter func. to support tx vlan offload func */
1483 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1484 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1486 priv = netdev_priv(netdev);
1487 spin_lock_init(&priv->page_lock);
1488 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1489 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1490 if (!priv->hw_stats) {
1494 spin_lock_init(&priv->hw_stats->stats_lock);
1497 sysclk = devm_clk_get(&pdev->dev, NULL);
1498 if (!IS_ERR(sysclk))
1499 priv->sysclk = clk_get_rate(sysclk);
1501 priv->netdev = netdev;
1502 priv->device = &pdev->dev;
1504 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1505 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1506 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1507 priv->tx_ring.tx_ring_size = priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1508 INIT_WORK(&priv->pending_work, fe_pending_work);
1511 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1513 priv->tx_ring.tx_ring_size *= 4;
1514 priv->rx_ring.rx_ring_size *= 4;
1516 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1517 fe_set_ethtool_ops(netdev);
1519 err = register_netdev(netdev);
1521 dev_err(&pdev->dev, "error bringing up device\n");
1525 platform_set_drvdata(pdev, netdev);
1527 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1528 netdev->base_addr, netdev->irq);
1533 free_netdev(netdev);
1535 devm_iounmap(&pdev->dev, fe_base);
1540 static int fe_remove(struct platform_device *pdev)
1542 struct net_device *dev = platform_get_drvdata(pdev);
1543 struct fe_priv *priv = netdev_priv(dev);
1545 netif_napi_del(&priv->rx_napi);
1547 kfree(priv->hw_stats);
1549 cancel_work_sync(&priv->pending_work);
1551 unregister_netdev(dev);
1553 platform_set_drvdata(pdev, NULL);
1558 static struct platform_driver fe_driver = {
1560 .remove = fe_remove,
1562 .name = "ralink_soc_eth",
1563 .owner = THIS_MODULE,
1564 .of_match_table = of_fe_match,
1568 static int __init init_rtfe(void)
1576 ret = platform_driver_register(&fe_driver);
1583 static void __exit exit_rtfe(void)
1585 platform_driver_unregister(&fe_driver);
1589 module_init(init_rtfe);
1590 module_exit(exit_rtfe);
1592 MODULE_LICENSE("GPL");
1593 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1594 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1595 MODULE_VERSION(FE_DRV_VERSION);