2 * Ralink RT305x SoC specific setup
4 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Ralink's 2.6.21 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
18 #include <asm/mipsregs.h>
20 #include <asm/mach-ralink/common.h>
21 #include <asm/mach-ralink/ramips_gpio.h>
22 #include <asm/mach-ralink/rt305x.h>
23 #include <asm/mach-ralink/rt305x_regs.h>
25 void __iomem * rt305x_sysc_base;
26 void __iomem * rt305x_memc_base;
27 enum rt305x_soc_type rt305x_soc;
29 void __init ramips_soc_prom_init(void)
31 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
32 const char *name = "unknown";
37 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
38 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
40 if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
41 unsigned long icache_sets;
43 icache_sets = (read_c0_config1() >> 22) & 7;
44 if (icache_sets == 1) {
45 rt305x_soc = RT305X_SOC_RT3050;
48 rt305x_soc = RT305X_SOC_RT3052;
51 } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
52 rt305x_soc = RT305X_SOC_RT3350;
54 } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
55 rt305x_soc = RT305X_SOC_RT3352;
58 panic("rt305x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
61 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
63 snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
64 "Ralink %s id:%u rev:%u",
66 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
67 (id & CHIP_ID_REV_MASK));
69 ramips_mem_base = RT305X_SDRAM_BASE;
70 ramips_mem_size_min = RT305X_MEM_SIZE_MIN;
71 ramips_mem_size_max = RT305X_MEM_SIZE_MAX;
74 static struct ramips_gpio_chip rt305x_gpio_chips[] = {
77 .label = "RT305X-GPIO0",
82 [RAMIPS_GPIO_REG_INT] = 0x00,
83 [RAMIPS_GPIO_REG_EDGE] = 0x04,
84 [RAMIPS_GPIO_REG_RENA] = 0x08,
85 [RAMIPS_GPIO_REG_FENA] = 0x0c,
86 [RAMIPS_GPIO_REG_DATA] = 0x20,
87 [RAMIPS_GPIO_REG_DIR] = 0x24,
88 [RAMIPS_GPIO_REG_POL] = 0x28,
89 [RAMIPS_GPIO_REG_SET] = 0x2c,
90 [RAMIPS_GPIO_REG_RESET] = 0x30,
91 [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
93 .map_base = RT305X_PIO_BASE,
94 .map_size = RT305X_PIO_SIZE,
98 .label = "RT305X-GPIO1",
103 [RAMIPS_GPIO_REG_INT] = 0x38,
104 [RAMIPS_GPIO_REG_EDGE] = 0x3c,
105 [RAMIPS_GPIO_REG_RENA] = 0x40,
106 [RAMIPS_GPIO_REG_FENA] = 0x44,
107 [RAMIPS_GPIO_REG_DATA] = 0x48,
108 [RAMIPS_GPIO_REG_DIR] = 0x4c,
109 [RAMIPS_GPIO_REG_POL] = 0x50,
110 [RAMIPS_GPIO_REG_SET] = 0x54,
111 [RAMIPS_GPIO_REG_RESET] = 0x58,
112 [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
114 .map_base = RT305X_PIO_BASE,
115 .map_size = RT305X_PIO_SIZE,
119 .label = "RT305X-GPIO2",
124 [RAMIPS_GPIO_REG_INT] = 0x60,
125 [RAMIPS_GPIO_REG_EDGE] = 0x64,
126 [RAMIPS_GPIO_REG_RENA] = 0x68,
127 [RAMIPS_GPIO_REG_FENA] = 0x6c,
128 [RAMIPS_GPIO_REG_DATA] = 0x70,
129 [RAMIPS_GPIO_REG_DIR] = 0x74,
130 [RAMIPS_GPIO_REG_POL] = 0x78,
131 [RAMIPS_GPIO_REG_SET] = 0x7c,
132 [RAMIPS_GPIO_REG_RESET] = 0x80,
133 [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
135 .map_base = RT305X_PIO_BASE,
136 .map_size = RT305X_PIO_SIZE,
140 static struct ramips_gpio_data rt305x_gpio_data = {
141 .chips = rt305x_gpio_chips,
142 .num_chips = ARRAY_SIZE(rt305x_gpio_chips),
145 static void rt305x_gpio_reserve(int first, int last)
147 for (; first <= last; first++)
148 gpio_request(first, "reserved");
151 void __init rt305x_gpio_init(u32 mode)
155 rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
157 ramips_gpio_init(&rt305x_gpio_data);
158 if ((mode & RT305X_GPIO_MODE_I2C) == 0)
159 rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
161 if ((mode & RT305X_GPIO_MODE_SPI) == 0)
162 rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
164 t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
165 t &= RT305X_GPIO_MODE_UART0_MASK;
167 case RT305X_GPIO_MODE_UARTF:
168 case RT305X_GPIO_MODE_PCM_UARTF:
169 case RT305X_GPIO_MODE_PCM_I2S:
170 case RT305X_GPIO_MODE_I2S_UARTF:
171 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
173 case RT305X_GPIO_MODE_PCM_GPIO:
174 rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
176 case RT305X_GPIO_MODE_GPIO_UARTF:
177 case RT305X_GPIO_MODE_GPIO_I2S:
178 rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
182 if ((mode & RT305X_GPIO_MODE_UART1) == 0)
183 rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
184 RT305X_GPIO_UART1_RXD);
186 if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
187 rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
189 if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
190 rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
191 RT305X_GPIO_MDIO_MDIO);
193 if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
194 rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
195 RT305X_GPIO_SDRAM_MD31);
197 if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
198 rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
199 RT305X_GPIO_GE0_RXCLK);