2 * Ralink SoC specific GPIO support
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
13 #include <linux/spinlock.h>
14 #include <linux/gpio.h>
16 #include <ralink_soc.h>
18 #define GPIO0_REG_INT 0x00
19 #define GPIO0_REG_EDGE 0x04
20 #define GPIO0_REG_RENA 0x08
21 #define GPIO0_REG_FENA 0x0c
22 #define GPIO0_REG_DATA 0x20
23 #define GPIO0_REG_DIR 0x24
24 #define GPIO0_REG_POL 0x28
25 #define GPIO0_REG_SET 0x2c
26 #define GPIO0_REG_RESET 0x30
27 #define GPIO0_REG_TOGGLE 0x34
29 #define GPIO1_REG_INT 0x38
30 #define GPIO1_REG_EDGE 0x3c
31 #define GPIO1_REG_RENA 0x40
32 #define GPIO1_REG_FENA 0x44
33 #define GPIO1_REG_DATA 0x48
34 #define GPIO1_REG_DIR 0x4c
35 #define GPIO1_REG_POL 0x50
36 #define GPIO1_REG_SET 0x54
37 #define GPIO1_REG_RESET 0x58
38 #define GPIO1_REG_TOGGLE 0x5c
40 #define GPIO2_REG_INT 0x60
41 #define GPIO2_REG_EDGE 0x64
42 #define GPIO2_REG_RENA 0x68
43 #define GPIO2_REG_FENA 0x6c
44 #define GPIO2_REG_DATA 0x70
45 #define GPIO2_REG_DIR 0x74
46 #define GPIO2_REG_POL 0x78
47 #define GPIO2_REG_SET 0x7c
48 #define GPIO2_REG_RESET 0x80
49 #define GPIO2_REG_TOGGLE 0x84
52 RAMIPS_GPIO_REG_INT, /* Interrupt status */
57 RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
58 RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
60 RAMIPS_GPIO_REG_RESET,
61 RAMIPS_GPIO_REG_TOGGLE,
65 struct ramips_gpio_chip {
66 struct gpio_chip chip;
68 u8 regs[RAMIPS_GPIO_REG_MAX];
71 static void __iomem *ramips_gpio_base;
73 static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
75 struct ramips_gpio_chip *rg;
77 rg = container_of(chip, struct ramips_gpio_chip, chip);
81 static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
83 __raw_writel(val, ramips_gpio_base + rg->regs[reg]);
86 static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
88 return __raw_readl(ramips_gpio_base + rg->regs[reg]);
91 static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
93 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
97 spin_lock_irqsave(&rg->lock, flags);
98 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
100 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
101 spin_unlock_irqrestore(&rg->lock, flags);
106 static int ramips_gpio_direction_output(struct gpio_chip *chip,
107 unsigned offset, int value)
109 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
114 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
116 spin_lock_irqsave(&rg->lock, flags);
117 ramips_gpio_wr(rg, reg, 1 << offset);
119 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
121 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
122 spin_unlock_irqrestore(&rg->lock, flags);
127 static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
129 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
132 reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
133 ramips_gpio_wr(rg, reg, 1 << offset);
136 static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
138 struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
141 t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
142 return !!(t & (1 << offset));
145 static struct ramips_gpio_chip ramips_gpio_chip0 = {
147 .label = "ramips-gpio0",
148 .direction_input = ramips_gpio_direction_input,
149 .direction_output = ramips_gpio_direction_output,
150 .get = ramips_gpio_get,
151 .set = ramips_gpio_set,
153 .ngpio = RALINK_SOC_GPIO0_COUNT,
156 [RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,
157 [RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,
158 [RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,
159 [RAMIPS_GPIO_REG_FENA] = GPIO0_REG_FENA,
160 [RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,
161 [RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,
162 [RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,
163 [RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,
164 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
165 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
169 static struct ramips_gpio_chip ramips_gpio_chip1 = {
171 .label = "ramips-gpio1",
172 .direction_input = ramips_gpio_direction_input,
173 .direction_output = ramips_gpio_direction_output,
174 .get = ramips_gpio_get,
175 .set = ramips_gpio_set,
177 .ngpio = RALINK_SOC_GPIO1_COUNT,
180 [RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,
181 [RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,
182 [RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,
183 [RAMIPS_GPIO_REG_FENA] = GPIO1_REG_FENA,
184 [RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,
185 [RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,
186 [RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,
187 [RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,
188 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
189 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
193 static struct ramips_gpio_chip ramips_gpio_chip2 = {
195 .label = "ramips-gpio2",
196 .direction_input = ramips_gpio_direction_input,
197 .direction_output = ramips_gpio_direction_output,
198 .get = ramips_gpio_get,
199 .set = ramips_gpio_set,
201 .ngpio = RALINK_SOC_GPIO2_COUNT,
204 [RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,
205 [RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,
206 [RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,
207 [RAMIPS_GPIO_REG_FENA] = GPIO2_REG_FENA,
208 [RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,
209 [RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,
210 [RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,
211 [RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,
212 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
213 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
217 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
219 spin_lock_init(&rg->lock);
221 /* set polarity to low for all lines */
222 ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
224 gpiochip_add(&rg->chip);
227 __init int ramips_gpio_init(void)
229 ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE);
231 ramips_gpio_chip_add(&ramips_gpio_chip0);
232 ramips_gpio_chip_add(&ramips_gpio_chip1);
233 ramips_gpio_chip_add(&ramips_gpio_chip2);