2 * Ralink RT288x SoC PCI register definitions
4 * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Parts of this file are based on Ralink's 2.6.21 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/types.h>
15 #include <linux/pci.h>
17 #include <linux/init.h>
19 #include <asm/mach-ralink/rt288x.h>
20 #include <asm/mach-ralink/rt288x_regs.h>
22 #define RT2880_PCI_MEM_BASE 0x20000000
23 #define RT2880_PCI_MEM_SIZE 0x10000000
24 #define RT2880_PCI_IO_BASE 0x00460000
25 #define RT2880_PCI_IO_SIZE 0x00010000
27 #define RT2880_PCI_REG_PCICFG_ADDR 0x00
28 #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
29 #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
30 #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
31 #define RT2880_PCI_REG_CONFIG_ADDR 0x20
32 #define RT2880_PCI_REG_CONFIG_DATA 0x24
33 #define RT2880_PCI_REG_MEMBASE 0x28
34 #define RT2880_PCI_REG_IOBASE 0x2c
35 #define RT2880_PCI_REG_ID 0x30
36 #define RT2880_PCI_REG_CLASS 0x34
37 #define RT2880_PCI_REG_SUBID 0x38
38 #define RT2880_PCI_REG_ARBCTL 0x80
40 static void __iomem *rt2880_pci_base;
41 static DEFINE_SPINLOCK(rt2880_pci_lock);
43 static u32 rt2880_pci_reg_read(u32 reg)
45 return readl(rt2880_pci_base + reg);
48 static void rt2880_pci_reg_write(u32 val, u32 reg)
50 writel(val, rt2880_pci_base + reg);
53 static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
54 unsigned int func, unsigned int where)
56 return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
60 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
61 int where, int size, u32 *val)
67 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
68 PCI_FUNC(devfn), where);
70 spin_lock_irqsave(&rt2880_pci_lock, flags);
71 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
72 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
73 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
77 *val = (data >> ((where & 3) << 3)) & 0xff;
80 *val = (data >> ((where & 3) << 3)) & 0xffff;
87 return PCIBIOS_SUCCESSFUL;
90 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
91 int where, int size, u32 val)
97 address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
98 PCI_FUNC(devfn), where);
100 spin_lock_irqsave(&rt2880_pci_lock, flags);
101 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
102 data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
106 data = (data & ~(0xff << ((where & 3) << 3))) |
107 (val << ((where & 3) << 3));
110 data = (data & ~(0xffff << ((where & 3) << 3))) |
111 (val << ((where & 3) << 3));
118 rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
119 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
121 return PCIBIOS_SUCCESSFUL;
124 static struct pci_ops rt2880_pci_ops = {
125 .read = rt2880_pci_config_read,
126 .write = rt2880_pci_config_write,
129 static struct resource rt2880_pci_io_resource = {
130 .name = "PCI MEM space",
131 .start = RT2880_PCI_MEM_BASE,
132 .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
133 .flags = IORESOURCE_MEM,
136 static struct resource rt2880_pci_mem_resource = {
137 .name = "PCI IO space",
138 .start = RT2880_PCI_IO_BASE,
139 .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
140 .flags = IORESOURCE_IO,
143 static struct pci_controller rt2880_pci_controller = {
144 .pci_ops = &rt2880_pci_ops,
145 .mem_resource = &rt2880_pci_io_resource,
146 .io_resource = &rt2880_pci_mem_resource,
149 static inline void read_config(unsigned long bus, unsigned long dev,
150 unsigned long func, unsigned long reg,
153 unsigned long address;
156 address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
158 spin_lock_irqsave(&rt2880_pci_lock, flags);
159 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
160 *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
161 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
164 static inline void write_config(unsigned long bus, unsigned long dev,
165 unsigned long func, unsigned long reg,
168 unsigned long address;
171 address = rt2880_pci_get_cfgaddr(bus, dev, func, reg);
173 spin_lock_irqsave(&rt2880_pci_lock, flags);
174 rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
175 rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
176 spin_unlock_irqrestore(&rt2880_pci_lock, flags);
179 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
185 if (dev->bus->number != 0)
188 switch (PCI_SLOT(dev->devfn)) {
190 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
191 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
194 irq = RT288X_CPU_IRQ_PCI;
197 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
198 __FILE__, __func__, __LINE__);
203 pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
204 pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
205 pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
206 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
207 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
208 PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
209 pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
210 pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
215 static int __init rt2880_pci_init(void)
217 unsigned long val = 0;
220 rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
222 rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
223 for(i = 0; i < 0xfffff; i++) {}
225 rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
226 rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
227 rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
228 rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
229 rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
230 rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
231 rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
232 rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
233 rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
234 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
235 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
237 register_pci_controller(&rt2880_pci_controller);
241 int pcibios_plat_dev_init(struct pci_dev *dev)
246 arch_initcall(rt2880_pci_init);