target/linux/pxa/patches-2.6.21/036-270-usb-gadget-udc.patch

   1 Index: linux-2.6.21gum/drivers/usb/gadget/Kconfig
   2 ===================================================================
   3 --- linux-2.6.21gum.orig/drivers/usb/gadget/Kconfig
   4 +++ linux-2.6.21gum/drivers/usb/gadget/Kconfig
   5 @@ -129,6 +129,28 @@ config USB_PXA2XX_SMALL
   6         default y if USB_ETH
   7         default y if USB_G_SERIAL
   8
   9 +config USB_GADGET_PXA27X
  10 +        boolean "PXA 27x"
  11 +        depends on ARCH_PXA && PXA27x
  12 +        help
  13 +           Intel's PXA 27x series XScale ARM-5TE processors include
  14 +           an integrated full speed USB 1.1 device controller.
  15 +
  16 +           Say "y" to link the driver statically, or "m" to build a
  17 +           dynamically linked module called "pxa27x_udc" and force all
  18 +           gadget drivers to also be dynamically linked.
  19 +
  20 +config USB_PXA27X
  21 +        tristate
  22 +        depends on USB_GADGET_PXA27X
  23 +        default USB_GADGET
  24 +        select USB_GADGET_SELECTED
  25 +
  26 +config USB_PXA27X_DMA
  27 +        bool # "Use DMA support"
  28 +        depends on USB_GADGET_PXA27X
  29 +        default n
  30 +
  31  config USB_GADGET_GOKU
  32         boolean "Toshiba TC86C001 'Goku-S'"
  33         depends on PCI
  34 Index: linux-2.6.21gum/drivers/usb/gadget/Makefile
  35 ===================================================================
  36 --- linux-2.6.21gum.orig/drivers/usb/gadget/Makefile
  37 +++ linux-2.6.21gum/drivers/usb/gadget/Makefile
  38 @@ -7,6 +7,7 @@ obj-$(CONFIG_USB_PXA2XX)        += pxa2xx_udc.o
  39  obj-$(CONFIG_USB_GOKU)         += goku_udc.o
  40  obj-$(CONFIG_USB_OMAP)         += omap_udc.o
  41  obj-$(CONFIG_USB_LH7A40X)      += lh7a40x_udc.o
  42 +obj-$(CONFIG_USB_PXA27X)       += pxa27x_udc.o
  43  obj-$(CONFIG_USB_AT91)         += at91_udc.o
  44  obj-$(CONFIG_USB_GADGET_GUMSTIX)       += gumstix_gadget.o
  45
  46 Index: linux-2.6.21gum/drivers/usb/gadget/pxa27x_udc.c
  47 ===================================================================
  48 --- /dev/null
  49 +++ linux-2.6.21gum/drivers/usb/gadget/pxa27x_udc.c
  50 @@ -0,0 +1,2352 @@
  51 +/*
  52 + * linux/drivers/usb/gadget/pxa27x_udc.c
  53 + * Intel PXA2xx and IXP4xx on-chip full speed USB device controllers
  54 + *
  55 + * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
  56 + * Copyright (C) 2003 Robert Schwebel, Pengutronix
  57 + * Copyright (C) 2003 Benedikt Spranger, Pengutronix
  58 + * Copyright (C) 2003 David Brownell
  59 + * Copyright (C) 2003 Joshua Wise
  60 + * Copyright (C) 2004 Intel Corporation
  61 + * Copyright (C) 2005 SDG Systems, LLC  (Aric Blumer)
  62 + *
  63 + * This program is free software; you can redistribute it and/or modify
  64 + * it under the terms of the GNU General Public License as published by
  65 + * the Free Software Foundation; either version 2 of the License, or
  66 + * (at your option) any later version.
  67 + *
  68 + * This program is distributed in the hope that it will be useful,
  69 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  70 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  71 + * GNU General Public License for more details.
  72 + *
  73 + * You should have received a copy of the GNU General Public License
  74 + * along with this program; if not, write to the Free Software
  75 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  76 + *
  77 + */
  78 +
  79 +#undef DEBUG
  80 + // #define DEBUG 1
  81 + //#define     VERBOSE DBG_VERBOSE
  82 +
  83 +#include <linux/module.h>
  84 +#include <linux/kernel.h>
  85 +#include <linux/ioport.h>
  86 +#include <linux/types.h>
  87 +#include <linux/version.h>
  88 +#include <linux/errno.h>
  89 +#include <linux/delay.h>
  90 +#include <linux/sched.h>
  91 +#include <linux/slab.h>
  92 +#include <linux/init.h>
  93 +#include <linux/timer.h>
  94 +#include <linux/list.h>
  95 +#include <linux/interrupt.h>
  96 +#include <linux/proc_fs.h>
  97 +#include <linux/mm.h>
  98 +#include <linux/platform_device.h>
  99 +#include <linux/dma-mapping.h>
 100 +#include <linux/irq.h>
 101 +
 102 +#include <asm/byteorder.h>
 103 +#include <asm/dma.h>
 104 +#include <asm/io.h>
 105 +#include <asm/system.h>
 106 +#include <asm/mach-types.h>
 107 +#include <asm/unaligned.h>
 108 +#include <asm/hardware.h>
 109 +#include <asm/mach/irq.h>
 110 +#include <asm/arch/pxa-regs.h>
 111 +
 112 +#include <linux/usb/ch9.h>
 113 +#include <linux/usb_gadget.h>
 114 +
 115 +#include <asm/arch/udc.h>
 116 +
 117 +
 118 +/*
 119 + * This driver handles the USB Device Controller (UDC) in Intel's PXA 27777777x
 120 + * series processors.
 121 + * Such controller drivers work with a gadget driver.  The gadget driver
 122 + * returns descriptors, implements configuration and data protocols used
 123 + * by the host to interact with this device, and allocates endpoints to
 124 + * the different protocol interfaces.  The controller driver virtualizes
 125 + * usb hardware so that the gadget drivers will be more portable.
 126 + *
 127 + * This UDC hardware wants to implement a bit too much USB protocol, so
 128 + * it constrains the sorts of USB configuration change events that work.
 129 + * The errata for these chips are misleading; some "fixed" bugs from
 130 + * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
 131 + */
 132 +
 133 +#define        DRIVER_VERSION  "21-Jul-2005"
 134 +#define        DRIVER_DESC     "PXA 27x USB Device Controller driver"
 135 +
 136 +
 137 +static const char driver_name [] = "pxa27x_udc";
 138 +
 139 +static const char ep0name [] = "ep0";
 140 +
 141 +
 142 +#define        USE_DMA
 143 +//#define      DISABLE_TEST_MODE
 144 +
 145 +#ifdef CONFIG_PROC_FS
 146 +#define        UDC_PROC_FILE
 147 +#endif
 148 +
 149 +#include "pxa27x_udc.h"
 150 +
 151 +#if 0
 152 +#ifdef CONFIG_EMBEDDED
 153 +/* few strings, and little code to use them */
 154 +#undef DEBUG
 155 +#undef UDC_PROC_FILE
 156 +#endif
 157 +#endif
 158 +
 159 +#ifdef USE_DMA
 160 +static int use_dma = 1;
 161 +module_param(use_dma, bool, 0);
 162 +MODULE_PARM_DESC (use_dma, "true to use dma");
 163 +
 164 +static void dma_nodesc_handler (int dmach, void *_ep);
 165 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req);
 166 +
 167 +#define        DMASTR " (dma support)"
 168 +
 169 +#else  /* !USE_DMA */
 170 +#define        DMASTR " (pio only)"
 171 +#endif
 172 +
 173 +#ifdef CONFIG_USB_PXA27X_SMALL
 174 +#define SIZE_STR       " (small)"
 175 +#else
 176 +#define SIZE_STR       ""
 177 +#endif
 178 +
 179 +#ifdef DISABLE_TEST_MODE
 180 +/* (mode == 0) == no undocumented chip tweaks
 181 + * (mode & 1)  == double buffer bulk IN
 182 + * (mode & 2)  == double buffer bulk OUT
 183 + * ... so mode = 3 (or 7, 15, etc) does it for both
 184 + */
 185 +static ushort fifo_mode = 0;
 186 +module_param(fifo_mode, ushort, 0);
 187 +MODULE_PARM_DESC (fifo_mode, "pxa27x udc fifo mode");
 188 +#endif
 189 +
 190 +#define UDCISR0_IR0     0x3
 191 +#define UDCISR_INT_MASK         (UDC_INT_FIFOERROR | UDC_INT_PACKETCMP)
 192 +#define UDCICR_INT_MASK         UDCISR_INT_MASK
 193 +
 194 +#define UDCCSR_MASK    (UDCCSR_FST | UDCCSR_DME)
 195 +/* ---------------------------------------------------------------------------
 196 + *     endpoint related parts of the api to the usb controller hardware,
 197 + *     used by gadget driver; and the inner talker-to-hardware core.
 198 + * ---------------------------------------------------------------------------
 199 + */
 200 +
 201 +static void pxa27x_ep_fifo_flush (struct usb_ep *ep);
 202 +static void nuke (struct pxa27x_ep *, int status);
 203 +
 204 +static void pio_irq_enable(int ep_num)
 205 +{
 206 +        if (ep_num < 16)
 207 +                UDCICR0 |= 3 << (ep_num * 2);
 208 +        else {
 209 +                ep_num -= 16;
 210 +                UDCICR1 |= 3 << (ep_num * 2);
 211 +       }
 212 +}
 213 +
 214 +static void pio_irq_disable(int ep_num)
 215 +{
 216 +        ep_num &= 0xf;
 217 +        if (ep_num < 16)
 218 +                UDCICR0 &= ~(3 << (ep_num * 2));
 219 +        else {
 220 +                ep_num -= 16;
 221 +                UDCICR1 &= ~(3 << (ep_num * 2));
 222 +        }
 223 +}
 224 +
 225 +/* The UDCCR reg contains mask and interrupt status bits,
 226 + * so using '|=' isn't safe as it may ack an interrupt.
 227 + */
 228 +#define UDCCR_MASK_BITS         (UDCCR_OEN | UDCCR_UDE)
 229 +
 230 +static inline void udc_set_mask_UDCCR(int mask)
 231 +{
 232 +       UDCCR = (UDCCR & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS);
 233 +}
 234 +
 235 +static inline void udc_clear_mask_UDCCR(int mask)
 236 +{
 237 +       UDCCR = (UDCCR & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS);
 238 +}
 239 +
 240 +static inline void udc_ack_int_UDCCR(int mask)
 241 +{
 242 +       /* udccr contains the bits we dont want to change */
 243 +       __u32 udccr = UDCCR & UDCCR_MASK_BITS;
 244 +
 245 +       UDCCR = udccr | (mask & ~UDCCR_MASK_BITS);
 246 +}
 247 +
 248 +/*
 249 + * endpoint enable/disable
 250 + *
 251 + * we need to verify the descriptors used to enable endpoints.  since pxa27x
 252 + * endpoint configurations are fixed, and are pretty much always enabled,
 253 + * there's not a lot to manage here.
 254 + *
 255 + * because pxa27x can't selectively initialize bulk (or interrupt) endpoints,
 256 + * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
 257 + * for a single interface (with only the default altsetting) and for gadget
 258 + * drivers that don't halt endpoints (not reset by set_interface).  that also
 259 + * means that if you use ISO, you must violate the USB spec rule that all
 260 + * iso endpoints must be in non-default altsettings.
 261 + */
 262 +static int pxa27x_ep_enable (struct usb_ep *_ep,
 263 +               const struct usb_endpoint_descriptor *desc)
 264 +{
 265 +       struct pxa27x_ep        *ep;
 266 +       struct pxa27x_udc       *dev;
 267 +
 268 +       ep = container_of (_ep, struct pxa27x_ep, ep);
 269 +       if (!_ep || !desc || _ep->name == ep0name
 270 +                       || desc->bDescriptorType != USB_DT_ENDPOINT
 271 +                       || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
 272 +               DMSG("%s, bad ep or descriptor\n", __FUNCTION__);
 273 +               return -EINVAL;
 274 +       }
 275 +
 276 +       /* xfer types must match, except that interrupt ~= bulk */
 277 +       if( ep->ep_type != USB_ENDPOINT_XFER_BULK
 278 +                       && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 279 +               DMSG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 280 +               return -EINVAL;
 281 +       }
 282 +
 283 +       /* hardware _could_ do smaller, but driver doesn't */
 284 +       if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 285 +                               && le16_to_cpu (desc->wMaxPacketSize)
 286 +                                               != BULK_FIFO_SIZE)
 287 +                       || !desc->wMaxPacketSize) {
 288 +               DMSG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 289 +               return -ERANGE;
 290 +       }
 291 +
 292 +       dev = ep->dev;
 293 +       if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
 294 +               DMSG("%s, bogus device state\n", __FUNCTION__);
 295 +               return -ESHUTDOWN;
 296 +       }
 297 +
 298 +       ep->desc = desc;
 299 +       ep->dma = -1;
 300 +       ep->stopped = 0;
 301 +       ep->pio_irqs = ep->dma_irqs = 0;
 302 +       ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize);
 303 +
 304 +       /* flush fifo (mostly for OUT buffers) */
 305 +       pxa27x_ep_fifo_flush (_ep);
 306 +
 307 +       /* ... reset halt state too, if we could ... */
 308 +
 309 +#ifdef USE_DMA
 310 +       /* for (some) bulk and ISO endpoints, try to get a DMA channel and
 311 +        * bind it to the endpoint.  otherwise use PIO.
 312 +        */
 313 +       DMSG("%s: called attributes=%d\n", __FUNCTION__, ep->ep_type);
 314 +       switch (ep->ep_type) {
 315 +       case USB_ENDPOINT_XFER_ISOC:
 316 +               if (le16_to_cpu(desc->wMaxPacketSize) % 32)
 317 +                       break;
 318 +               // fall through
 319 +       case USB_ENDPOINT_XFER_BULK:
 320 +               if (!use_dma || !ep->reg_drcmr)
 321 +                       break;
 322 +               ep->dma = pxa_request_dma ((char *)_ep->name,
 323 +                               (le16_to_cpu (desc->wMaxPacketSize) > 64)
 324 +                                       ? DMA_PRIO_MEDIUM /* some iso */
 325 +                                       : DMA_PRIO_LOW,
 326 +                               dma_nodesc_handler, ep);
 327 +               if (ep->dma >= 0) {
 328 +                       *ep->reg_drcmr = DRCMR_MAPVLD | ep->dma;
 329 +                       DMSG("%s using dma%d\n", _ep->name, ep->dma);
 330 +               }
 331 +       default:
 332 +               break;
 333 +       }
 334 +#endif
 335 +       DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
 336 +       return 0;
 337 +}
 338 +
 339 +static int pxa27x_ep_disable (struct usb_ep *_ep)
 340 +{
 341 +       struct pxa27x_ep        *ep;
 342 +
 343 +       ep = container_of (_ep, struct pxa27x_ep, ep);
 344 +       if (!_ep || !ep->desc) {
 345 +               DMSG("%s, %s not enabled\n", __FUNCTION__,
 346 +                       _ep ? ep->ep.name : NULL);
 347 +               return -EINVAL;
 348 +       }
 349 +       nuke (ep, -ESHUTDOWN);
 350 +
 351 +#ifdef USE_DMA
 352 +       if (ep->dma >= 0) {
 353 +               *ep->reg_drcmr = 0;
 354 +               pxa_free_dma (ep->dma);
 355 +               ep->dma = -1;
 356 +       }
 357 +#endif
 358 +
 359 +       /* flush fifo (mostly for IN buffers) */
 360 +       pxa27x_ep_fifo_flush (_ep);
 361 +
 362 +       ep->desc = 0;
 363 +       ep->stopped = 1;
 364 +
 365 +       DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
 366 +       return 0;
 367 +}
 368 +
 369 +/*-------------------------------------------------------------------------*/
 370 +
 371 +/* for the pxa27x, these can just wrap kmalloc/kfree.  gadget drivers
 372 + * must still pass correctly initialized endpoints, since other controller
 373 + * drivers may care about how it's currently set up (dma issues etc).
 374 + */
 375 +
 376 +/*
 377 + *     pxa27x_ep_alloc_request - allocate a request data structure
 378 + */
 379 +static struct usb_request *
 380 +pxa27x_ep_alloc_request (struct usb_ep *_ep, unsigned gfp_flags)
 381 +{
 382 +       struct pxa27x_request *req;
 383 +
 384 +       req = kmalloc (sizeof *req, gfp_flags);
 385 +       if (!req)
 386 +               return 0;
 387 +
 388 +       memset (req, 0, sizeof *req);
 389 +       INIT_LIST_HEAD (&req->queue);
 390 +       return &req->req;
 391 +}
 392 +
 393 +
 394 +/*
 395 + *     pxa27x_ep_free_request - deallocate a request data structure
 396 + */
 397 +static void
 398 +pxa27x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
 399 +{
 400 +       struct pxa27x_request *req;
 401 +
 402 +       req = container_of(_req, struct pxa27x_request, req);
 403 +       WARN_ON (!list_empty (&req->queue));
 404 +       kfree(req);
 405 +}
 406 +
 407 +
 408 +/* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
 409 + * no device-affinity and the heap works perfectly well for i/o buffers.
 410 + * It wastes much less memory than dma_alloc_coherent() would, and even
 411 + * prevents cacheline (32 bytes wide) sharing problems.
 412 + */
 413 +static void *
 414 +pxa27x_ep_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
 415 +       dma_addr_t *dma, unsigned gfp_flags)
 416 +{
 417 +       char                    *retval;
 418 +
 419 +       retval = kmalloc (bytes, gfp_flags & ~(__GFP_DMA|__GFP_HIGHMEM));
 420 +       if (retval)
 421 +               *dma = virt_to_bus (retval);
 422 +       return retval;
 423 +}
 424 +
 425 +static void
 426 +pxa27x_ep_free_buffer(struct usb_ep *_ep, void *buf, dma_addr_t dma,
 427 +               unsigned bytes)
 428 +{
 429 +       kfree (buf);
 430 +}
 431 +
 432 +/*-------------------------------------------------------------------------*/
 433 +
 434 +/*
 435 + *     done - retire a request; caller blocked irqs
 436 + */
 437 +static void done(struct pxa27x_ep *ep, struct pxa27x_request *req, int status)
 438 +{
 439 +       list_del_init(&req->queue);
 440 +       if (likely (req->req.status == -EINPROGRESS))
 441 +               req->req.status = status;
 442 +       else
 443 +               status = req->req.status;
 444 +
 445 +       if (status && status != -ESHUTDOWN)
 446 +               DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
 447 +                       ep->ep.name, &req->req, status,
 448 +                       req->req.actual, req->req.length);
 449 +
 450 +       /* don't modify queue heads during completion callback */
 451 +       req->req.complete(&ep->ep, &req->req);
 452 +}
 453 +
 454 +
 455 +static inline void ep0_idle (struct pxa27x_udc *dev)
 456 +{
 457 +       dev->ep0state = EP0_IDLE;
 458 +       LED_EP0_OFF;
 459 +}
 460 +
 461 +static int
 462 +write_packet(volatile u32 *uddr, struct pxa27x_request *req, unsigned max)
 463 +{
 464 +       u32             *buf;
 465 +       int     length, count, remain;
 466 +
 467 +       buf = (u32*)(req->req.buf + req->req.actual);
 468 +       prefetch(buf);
 469 +
 470 +       /* how big will this packet be? */
 471 +       length = min(req->req.length - req->req.actual, max);
 472 +       req->req.actual += length;
 473 +
 474 +       remain = length & 0x3;
 475 +       count = length & ~(0x3);
 476 +
 477 +       while (likely(count)) {
 478 +               *uddr = *buf++;
 479 +               count -= 4;
 480 +       }
 481 +
 482 +       if (remain) {
 483 +               volatile u8* reg=(u8*)uddr;
 484 +               char *rd =(u8*)buf;
 485 +
 486 +               while (remain--) {
 487 +                       *reg=*rd++;
 488 +               }
 489 +       }
 490 +
 491 +       return length;
 492 +}
 493 +
 494 +/*
 495 + * write to an IN endpoint fifo, as many packets as possible.
 496 + * irqs will use this to write the rest later.
 497 + * caller guarantees at least one packet buffer is ready (or a zlp).
 498 + */
 499 +static int
 500 +write_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 501 +{
 502 +       unsigned                max;
 503 +
 504 +       max = le16_to_cpu(ep->desc->wMaxPacketSize);
 505 +       do {
 506 +               int     count;
 507 +               int             is_last, is_short;
 508 +
 509 +               count = write_packet(ep->reg_udcdr, req, max);
 510 +
 511 +               /* last packet is usually short (or a zlp) */
 512 +               if (unlikely (count != max))
 513 +                       is_last = is_short = 1;
 514 +               else {
 515 +                       if (likely(req->req.length != req->req.actual)
 516 +                                       || req->req.zero)
 517 +                               is_last = 0;
 518 +                       else
 519 +                               is_last = 1;
 520 +                       /* interrupt/iso maxpacket may not fill the fifo */
 521 +                       is_short = unlikely (max < ep->fifo_size);
 522 +               }
 523 +
 524 +               DMSG("wrote %s count:%d bytes%s%s %d left %p\n",
 525 +                       ep->ep.name, count,
 526 +                       is_last ? "/L" : "", is_short ? "/S" : "",
 527 +                       req->req.length - req->req.actual, &req->req);
 528 +
 529 +               /* let loose that packet. maybe try writing another one,
 530 +                * double buffering might work.  TSP, TPC, and TFS
 531 +                * bit values are the same for all normal IN endpoints.
 532 +                */
 533 +               *ep->reg_udccsr = UDCCSR_PC;
 534 +               if (is_short)
 535 +                       *ep->reg_udccsr = UDCCSR_SP;
 536 +
 537 +               /* requests complete when all IN data is in the FIFO */
 538 +               if (is_last) {
 539 +                       done (ep, req, 0);
 540 +                       if (list_empty(&ep->queue) || unlikely(ep->dma >= 0)) {
 541 +                               pio_irq_disable (ep->ep_num);
 542 +#ifdef USE_DMA
 543 +                               /* unaligned data and zlps couldn't use dma */
 544 +                               if (unlikely(!list_empty(&ep->queue))) {
 545 +                                       req = list_entry(ep->queue.next,
 546 +                                               struct pxa27x_request, queue);
 547 +                                       kick_dma(ep,req);
 548 +                                       return 0;
 549 +                               }
 550 +#endif
 551 +                       }
 552 +                       return 1;
 553 +               }
 554 +
 555 +               // TODO experiment: how robust can fifo mode tweaking be?
 556 +               // double buffering is off in the default fifo mode, which
 557 +               // prevents TFS from being set here.
 558 +
 559 +       } while (*ep->reg_udccsr & UDCCSR_FS);
 560 +       return 0;
 561 +}
 562 +
 563 +/* caller asserts req->pending (ep0 irq status nyet cleared); starts
 564 + * ep0 data stage.  these chips want very simple state transitions.
 565 + */
 566 +static inline
 567 +void ep0start(struct pxa27x_udc *dev, u32 flags, const char *tag)
 568 +{
 569 +       UDCCSR0 = flags|UDCCSR0_SA|UDCCSR0_OPC;
 570 +       UDCISR0 = UDCICR_INT(0, UDC_INT_FIFOERROR | UDC_INT_PACKETCMP);
 571 +       dev->req_pending = 0;
 572 +       DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
 573 +               __FUNCTION__, tag, UDCCSR0, flags);
 574 +}
 575 +
 576 +static int
 577 +write_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 578 +{
 579 +       unsigned        count;
 580 +       int             is_short;
 581 +
 582 +       count = write_packet(&UDCDR0, req, EP0_FIFO_SIZE);
 583 +       ep->dev->stats.write.bytes += count;
 584 +
 585 +       /* last packet "must be" short (or a zlp) */
 586 +       is_short = (count != EP0_FIFO_SIZE);
 587 +
 588 +       DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
 589 +               req->req.length - req->req.actual, &req->req);
 590 +
 591 +       if (unlikely (is_short)) {
 592 +               if (ep->dev->req_pending)
 593 +                       ep0start(ep->dev, UDCCSR0_IPR, "short IN");
 594 +               else
 595 +                       UDCCSR0 = UDCCSR0_IPR;
 596 +
 597 +               count = req->req.length;
 598 +               done (ep, req, 0);
 599 +               ep0_idle(ep->dev);
 600 +#if 0
 601 +               /* This seems to get rid of lost status irqs in some cases:
 602 +                * host responds quickly, or next request involves config
 603 +                * change automagic, or should have been hidden, or ...
 604 +                *
 605 +                * FIXME get rid of all udelays possible...
 606 +                */
 607 +               if (count >= EP0_FIFO_SIZE) {
 608 +                       count = 100;
 609 +                       do {
 610 +                               if ((UDCCSR0 & UDCCSR0_OPC) != 0) {
 611 +                                       /* clear OPC, generate ack */
 612 +                                       UDCCSR0 = UDCCSR0_OPC;
 613 +                                       break;
 614 +                               }
 615 +                               count--;
 616 +                               udelay(1);
 617 +                       } while (count);
 618 +               }
 619 +#endif
 620 +       } else if (ep->dev->req_pending)
 621 +               ep0start(ep->dev, 0, "IN");
 622 +       return is_short;
 623 +}
 624 +
 625 +
 626 +/*
 627 + * read_fifo -  unload packet(s) from the fifo we use for usb OUT
 628 + * transfers and put them into the request.  caller should have made
 629 + * sure there's at least one packet ready.
 630 + *
 631 + * returns true if the request completed because of short packet or the
 632 + * request buffer having filled (and maybe overran till end-of-packet).
 633 + */
 634 +static int
 635 +read_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 636 +{
 637 +       for (;;) {
 638 +               u32             *buf;
 639 +               int     bufferspace, count, is_short;
 640 +
 641 +               /* make sure there's a packet in the FIFO.*/
 642 +               if (unlikely ((*ep->reg_udccsr & UDCCSR_PC) == 0))
 643 +                       break;
 644 +               buf =(u32*) (req->req.buf + req->req.actual);
 645 +               prefetchw(buf);
 646 +               bufferspace = req->req.length - req->req.actual;
 647 +
 648 +               /* read all bytes from this packet */
 649 +               if (likely (*ep->reg_udccsr & UDCCSR_BNE)) {
 650 +                       count = 0x3ff & *ep->reg_udcbcr;
 651 +                       req->req.actual += min (count, bufferspace);
 652 +               } else /* zlp */
 653 +                       count = 0;
 654 +
 655 +               is_short = (count < ep->ep.maxpacket);
 656 +               DMSG("read %s udccsr:%02x, count:%d bytes%s req %p %d/%d\n",
 657 +                       ep->ep.name, *ep->reg_udccsr, count,
 658 +                       is_short ? "/S" : "",
 659 +                       &req->req, req->req.actual, req->req.length);
 660 +
 661 +//             dump_regs(ep->ep_num );
 662 +               count = min(count, bufferspace);
 663 +               while (likely (count > 0)) {
 664 +                       *buf++ = *ep->reg_udcdr;
 665 +                       count -= 4;
 666 +               }
 667 +               DMSG("Buf:0x%p\n", req->req.buf);
 668 +
 669 +               *ep->reg_udccsr =  UDCCSR_PC;
 670 +               /* RPC/RSP/RNE could now reflect the other packet buffer */
 671 +
 672 +               /* completion */
 673 +               if (is_short || req->req.actual == req->req.length) {
 674 +                       done (ep, req, 0);
 675 +                       if (list_empty(&ep->queue))
 676 +                               pio_irq_disable (ep->ep_num);
 677 +                       return 1;
 678 +               }
 679 +
 680 +               /* finished that packet.  the next one may be waiting... */
 681 +       }
 682 +       return 0;
 683 +}
 684 +
 685 +/*
 686 + * special ep0 version of the above.  no UBCR0 or double buffering; status
 687 + * handshaking is magic.  most device protocols don't need control-OUT.
 688 + * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
 689 + * protocols do use them.
 690 + */
 691 +static int
 692 +read_ep0_fifo (struct pxa27x_ep *ep, struct pxa27x_request *req)
 693 +{
 694 +       u32             *buf, word;
 695 +       unsigned        bufferspace;
 696 +
 697 +       buf = (u32*) (req->req.buf + req->req.actual);
 698 +       bufferspace = req->req.length - req->req.actual;
 699 +
 700 +       while (UDCCSR0 & UDCCSR0_RNE) {
 701 +               word = UDCDR0;
 702 +
 703 +               if (unlikely (bufferspace == 0)) {
 704 +                       /* this happens when the driver's buffer
 705 +                        * is smaller than what the host sent.
 706 +                        * discard the extra data.
 707 +                        */
 708 +                       if (req->req.status != -EOVERFLOW)
 709 +                               DMSG("%s overflow\n", ep->ep.name);
 710 +                       req->req.status = -EOVERFLOW;
 711 +               } else {
 712 +                       *buf++ = word;
 713 +                       req->req.actual += 4;
 714 +                       bufferspace -= 4;
 715 +               }
 716 +       }
 717 +
 718 +       UDCCSR0 = UDCCSR0_OPC ;
 719 +
 720 +       /* completion */
 721 +       if (req->req.actual >= req->req.length)
 722 +               return 1;
 723 +
 724 +       /* finished that packet.  the next one may be waiting... */
 725 +       return 0;
 726 +}
 727 +
 728 +#ifdef USE_DMA
 729 +
 730 +#define        MAX_IN_DMA      ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
 731 +static void kick_dma(struct pxa27x_ep *ep, struct pxa27x_request *req)
 732 +{
 733 +       u32     dcmd = 0;
 734 +       u32     len = req->req.length;
 735 +       u32     buf = req->req.dma;
 736 +       u32     fifo = io_v2p ((u32)ep->reg_udcdr);
 737 +
 738 +       buf += req->req.actual;
 739 +       len -= req->req.actual;
 740 +       ep->dma_con = 0;
 741 +
 742 +       DMSG("%s: req:0x%p length:%d, actual:%d dma:%d\n",
 743 +                       __FUNCTION__, &req->req, req->req.length,
 744 +                       req->req.actual,ep->dma);
 745 +
 746 +       /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
 747 +       DCSR(ep->dma) = DCSR_NODESC;
 748 +       if (buf & 0x3)
 749 +               DALGN |= 1 << ep->dma;
 750 +       else
 751 +               DALGN &= ~(1 << ep->dma);
 752 +
 753 +       if (ep->dir_in) {
 754 +               DSADR(ep->dma) = buf;
 755 +               DTADR(ep->dma) = fifo;
 756 +               if (len > MAX_IN_DMA) {
 757 +                       len= MAX_IN_DMA;
 758 +                       ep->dma_con =1 ;
 759 +               } else if (len >= ep->ep.maxpacket) {
 760 +                       if ((ep->dma_con = (len % ep->ep.maxpacket) != 0))
 761 +                               len = ep->ep.maxpacket;
 762 +               }
 763 +                dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
 764 +                       | DCMD_FLOWTRG | DCMD_INCSRCADDR;
 765 +       } else {
 766 +               DSADR(ep->dma) = fifo;
 767 +               DTADR(ep->dma) = buf;
 768 +               dcmd = len | DCMD_BURST32 | DCMD_WIDTH4 | DCMD_ENDIRQEN
 769 +                       | DCMD_FLOWSRC | DCMD_INCTRGADDR;
 770 +       }
 771 +       *ep->reg_udccsr = UDCCSR_DME;
 772 +       DCMD(ep->dma) = dcmd;
 773 +       DCSR(ep->dma) =  DCSR_NODESC | DCSR_EORIRQEN \
 774 +                               | ((ep->dir_in) ? DCSR_STOPIRQEN : 0);
 775 +       *ep->reg_drcmr = ep->dma | DRCMR_MAPVLD;
 776 +       DCSR(ep->dma) |= DCSR_RUN;
 777 +}
 778 +
 779 +static void cancel_dma(struct pxa27x_ep *ep)
 780 +{
 781 +       struct pxa27x_request   *req;
 782 +       u32                     tmp;
 783 +
 784 +       if (DCSR(ep->dma) == 0 || list_empty(&ep->queue))
 785 +               return;
 786 +
 787 +       DMSG("hehe dma:%d,dcsr:0x%x\n", ep->dma, DCSR(ep->dma));
 788 +       DCSR(ep->dma) = 0;
 789 +       while ((DCSR(ep->dma) & DCSR_STOPSTATE) == 0)
 790 +               cpu_relax();
 791 +
 792 +       req = list_entry(ep->queue.next, struct pxa27x_request, queue);
 793 +       tmp = DCMD(ep->dma) & DCMD_LENGTH;
 794 +       req->req.actual = req->req.length - tmp;
 795 +
 796 +       /* the last tx packet may be incomplete, so flush the fifo.
 797 +        * FIXME correct req.actual if we can
 798 +        */
 799 +       *ep->reg_udccsr = UDCCSR_FEF;
 800 +}
 801 +
 802 +static void dma_nodesc_handler(int dmach, void *_ep)
 803 +{
 804 +       struct pxa27x_ep        *ep = _ep;
 805 +       struct pxa27x_request   *req, *req_next;
 806 +       u32                     dcsr, tmp, completed;
 807 +
 808 +       local_irq_disable();
 809 +
 810 +       req = list_entry(ep->queue.next, struct pxa27x_request, queue);
 811 +
 812 +       DMSG("%s, buf:0x%p\n",__FUNCTION__, req->req.buf);
 813 +
 814 +       ep->dma_irqs++;
 815 +       ep->dev->stats.irqs++;
 816 +       HEX_DISPLAY(ep->dev->stats.irqs);
 817 +
 818 +       completed = 0;
 819 +
 820 +       dcsr = DCSR(dmach);
 821 +       DCSR(ep->dma) &= ~DCSR_RUN;
 822 +
 823 +       if (dcsr & DCSR_BUSERR) {
 824 +               DCSR(dmach) = DCSR_BUSERR;
 825 +               printk(KERN_ERR " Buss Error\n");
 826 +               req->req.status = -EIO;
 827 +               completed = 1;
 828 +       } else if (dcsr & DCSR_ENDINTR) {
 829 +               DCSR(dmach) = DCSR_ENDINTR;
 830 +               if (ep->dir_in) {
 831 +                       tmp = req->req.length - req->req.actual;
 832 +                       /* Last packet is a short one*/
 833 +                       if ( tmp < ep->ep.maxpacket) {
 834 +                               int count = 0;
 835 +
 836 +                               *ep->reg_udccsr = UDCCSR_SP | \
 837 +                                       (*ep->reg_udccsr & UDCCSR_MASK);
 838 +                               /*Wait for packet out */
 839 +                               while( (count++ < 10000) && \
 840 +                                       !(*ep->reg_udccsr & UDCCSR_FS));
 841 +                               if (count >= 10000)
 842 +                                       DMSG("Failed to send packet\n");
 843 +                               else
 844 +                                       DMSG("%s: short packet sent len:%d,"
 845 +                                       "length:%d,actual:%d\n", __FUNCTION__,
 846 +                                       tmp, req->req.length, req->req.actual);
 847 +                               req->req.actual = req->req.length;
 848 +                               completed = 1;
 849 +                       /* There are still packets to transfer */
 850 +                       } else if ( ep->dma_con) {
 851 +                               DMSG("%s: more packets,length:%d,actual:%d\n",
 852 +                                        __FUNCTION__,req->req.length,
 853 +                                        req->req.actual);
 854 +                               req->req.actual += ep->ep.maxpacket;
 855 +                               completed = 0;
 856 +                       } else {
 857 +                               DMSG("%s: no more packets,length:%d,"
 858 +                                       "actual:%d\n", __FUNCTION__,
 859 +                                       req->req.length, req->req.actual);
 860 +                               req->req.actual = req->req.length;
 861 +                               completed = 1;
 862 +                       }
 863 +               } else {
 864 +                       req->req.actual = req->req.length;
 865 +                       completed = 1;
 866 +               }
 867 +       } else if (dcsr & DCSR_EORINTR) { //Only happened in OUT DMA
 868 +               int remain,udccsr ;
 869 +
 870 +               DCSR(dmach) = DCSR_EORINTR;
 871 +               remain = DCMD(dmach) & DCMD_LENGTH;
 872 +               req->req.actual = req->req.length - remain;
 873 +
 874 +               udccsr = *ep->reg_udccsr;
 875 +               if (udccsr & UDCCSR_SP) {
 876 +                       *ep->reg_udccsr = UDCCSR_PC | (udccsr & UDCCSR_MASK);
 877 +                       completed = 1;
 878 +               }
 879 +               DMSG("%s: length:%d actual:%d\n",
 880 +                               __FUNCTION__, req->req.length, req->req.actual);
 881 +       } else
 882 +               DMSG("%s: Others dma:%d DCSR:0x%x DCMD:0x%x\n",
 883 +                               __FUNCTION__, dmach, DCSR(dmach), DCMD(dmach));
 884 +
 885 +       if (likely(completed)) {
 886 +               if (req->queue.next != &ep->queue) {
 887 +                       req_next = list_entry(req->queue.next,
 888 +                                       struct pxa27x_request, queue);
 889 +                       kick_dma(ep, req_next);
 890 +               }
 891 +               done(ep, req, 0);
 892 +       } else {
 893 +               kick_dma(ep, req);
 894 +       }
 895 +
 896 +       local_irq_enable();
 897 +}
 898 +
 899 +#endif
 900 +/*-------------------------------------------------------------------------*/
 901 +
 902 +static int
 903 +pxa27x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, unsigned gfp_flags)
 904 +{
 905 +       struct pxa27x_ep        *ep;
 906 +       struct pxa27x_request   *req;
 907 +       struct pxa27x_udc       *dev;
 908 +       unsigned long           flags;
 909 +
 910 +       req = container_of(_req, struct pxa27x_request, req);
 911 +       if (unlikely (!_req || !_req->complete || !_req->buf||
 912 +                       !list_empty(&req->queue))) {
 913 +               DMSG("%s, bad params\n", __FUNCTION__);
 914 +               return -EINVAL;
 915 +       }
 916 +
 917 +       ep = container_of(_ep, struct pxa27x_ep, ep);
 918 +       if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
 919 +               DMSG("%s, bad ep\n", __FUNCTION__);
 920 +               return -EINVAL;
 921 +       }
 922 +
 923 +       DMSG("%s, ep point %d is queue\n", __FUNCTION__, ep->ep_num);
 924 +
 925 +       dev = ep->dev;
 926 +       if (unlikely (!dev->driver
 927 +                       || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
 928 +               DMSG("%s, bogus device state\n", __FUNCTION__);
 929 +               return -ESHUTDOWN;
 930 +       }
 931 +
 932 +       /* iso is always one packet per request, that's the only way
 933 +        * we can report per-packet status.  that also helps with dma.
 934 +        */
 935 +       if (unlikely (ep->ep_type == USB_ENDPOINT_XFER_ISOC
 936 +                       && req->req.length > le16_to_cpu
 937 +                                               (ep->desc->wMaxPacketSize)))
 938 +               return -EMSGSIZE;
 939 +
 940 +#ifdef USE_DMA
 941 +       // FIXME caller may already have done the dma mapping
 942 +       if (ep->dma >= 0) {
 943 +               _req->dma = dma_map_single(dev->dev, _req->buf, _req->length,
 944 +                       (ep->dir_in) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 945 +       }
 946 +#endif
 947 +
 948 +       DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
 949 +            _ep->name, _req, _req->length, _req->buf);
 950 +
 951 +       local_irq_save(flags);
 952 +
 953 +       _req->status = -EINPROGRESS;
 954 +       _req->actual = 0;
 955 +
 956 +       /* kickstart this i/o queue? */
 957 +       if (list_empty(&ep->queue) && !ep->stopped) {
 958 +               if (ep->desc == 0 /* ep0 */) {
 959 +                       unsigned        length = _req->length;
 960 +
 961 +                       switch (dev->ep0state) {
 962 +                       case EP0_IN_DATA_PHASE:
 963 +                               dev->stats.write.ops++;
 964 +                               if (write_ep0_fifo(ep, req))
 965 +                                       req = 0;
 966 +                               break;
 967 +
 968 +                       case EP0_OUT_DATA_PHASE:
 969 +                               dev->stats.read.ops++;
 970 +                               if (dev->req_pending)
 971 +                                       ep0start(dev, UDCCSR0_IPR, "OUT");
 972 +                               if (length == 0 || ((UDCCSR0 & UDCCSR0_RNE) != 0
 973 +                                               && read_ep0_fifo(ep, req))) {
 974 +                                       ep0_idle(dev);
 975 +                                       done(ep, req, 0);
 976 +                                       req = 0;
 977 +                               }
 978 +                               break;
 979 +                       case EP0_NO_ACTION:
 980 +                               ep0_idle(dev);
 981 +                               req=0;
 982 +                               break;
 983 +                       default:
 984 +                               DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
 985 +                               local_irq_restore (flags);
 986 +                               return -EL2HLT;
 987 +                       }
 988 +#ifdef USE_DMA
 989 +               /* either start dma or prime pio pump */
 990 +               } else if (ep->dma >= 0) {
 991 +                       kick_dma(ep, req);
 992 +#endif
 993 +               /* can the FIFO can satisfy the request immediately? */
 994 +               } else if (ep->dir_in
 995 +                               && (*ep->reg_udccsr & UDCCSR_FS) != 0
 996 +                               && write_fifo(ep, req)) {
 997 +                       req = 0;
 998 +               } else if ((*ep->reg_udccsr & UDCCSR_FS) != 0
 999 +                               && read_fifo(ep, req)) {
1000 +                       req = 0;
1001 +               }
1002 +               DMSG("req:%p,ep->desc:%p,ep->dma:%d\n", req, ep->desc, ep->dma);
1003 +               if (likely (req && ep->desc) && ep->dma < 0)
1004 +                       pio_irq_enable(ep->ep_num);
1005 +       }
1006 +
1007 +       /* pio or dma irq handler advances the queue. */
1008 +       if (likely (req != 0))
1009 +               list_add_tail(&req->queue, &ep->queue);
1010 +       local_irq_restore(flags);
1011 +
1012 +       return 0;
1013 +}
1014 +
1015 +
1016 +/*
1017 + *     nuke - dequeue ALL requests
1018 + */
1019 +static void nuke(struct pxa27x_ep *ep, int status)
1020 +{
1021 +       struct pxa27x_request *req;
1022 +
1023 +       /* called with irqs blocked */
1024 +#ifdef USE_DMA
1025 +       if (ep->dma >= 0 && !ep->stopped)
1026 +               cancel_dma(ep);
1027 +#endif
1028 +       while (!list_empty(&ep->queue)) {
1029 +               req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1030 +               done(ep, req, status);
1031 +       }
1032 +       if (ep->desc)
1033 +               pio_irq_disable (ep->ep_num);
1034 +}
1035 +
1036 +
1037 +/* dequeue JUST ONE request */
1038 +static int pxa27x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1039 +{
1040 +       struct pxa27x_ep        *ep;
1041 +       struct pxa27x_request   *req;
1042 +       unsigned long           flags;
1043 +
1044 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1045 +       if (!_ep || ep->ep.name == ep0name)
1046 +               return -EINVAL;
1047 +
1048 +       local_irq_save(flags);
1049 +
1050 +       /* make sure it's actually queued on this endpoint */
1051 +       list_for_each_entry (req, &ep->queue, queue) {
1052 +               if (&req->req == _req)
1053 +                       break;
1054 +       }
1055 +       if (&req->req != _req) {
1056 +               local_irq_restore(flags);
1057 +               return -EINVAL;
1058 +       }
1059 +
1060 +#ifdef USE_DMA
1061 +       if (ep->dma >= 0 && ep->queue.next == &req->queue && !ep->stopped) {
1062 +               cancel_dma(ep);
1063 +               done(ep, req, -ECONNRESET);
1064 +               /* restart i/o */
1065 +               if (!list_empty(&ep->queue)) {
1066 +                       req = list_entry(ep->queue.next,
1067 +                                       struct pxa27x_request, queue);
1068 +                       kick_dma(ep, req);
1069 +               }
1070 +       } else
1071 +#endif
1072 +               done(ep, req, -ECONNRESET);
1073 +
1074 +       local_irq_restore(flags);
1075 +       return 0;
1076 +}
1077 +
1078 +/*-------------------------------------------------------------------------*/
1079 +
1080 +static int pxa27x_ep_set_halt(struct usb_ep *_ep, int value)
1081 +{
1082 +       struct pxa27x_ep        *ep;
1083 +       unsigned long           flags;
1084 +
1085 +       DMSG("%s is called\n", __FUNCTION__);
1086 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1087 +       if (unlikely (!_ep
1088 +                       || (!ep->desc && ep->ep.name != ep0name))
1089 +                       || ep->ep_type == USB_ENDPOINT_XFER_ISOC) {
1090 +               DMSG("%s, bad ep\n", __FUNCTION__);
1091 +               return -EINVAL;
1092 +       }
1093 +       if (value == 0) {
1094 +               /* this path (reset toggle+halt) is needed to implement
1095 +                * SET_INTERFACE on normal hardware.  but it can't be
1096 +                * done from software on the PXA UDC, and the hardware
1097 +                * forgets to do it as part of SET_INTERFACE automagic.
1098 +                */
1099 +               DMSG("only host can clear %s halt\n", _ep->name);
1100 +               return -EROFS;
1101 +       }
1102 +
1103 +       local_irq_save(flags);
1104 +
1105 +       if (ep->dir_in  && ((*ep->reg_udccsr & UDCCSR_FS) == 0
1106 +                          || !list_empty(&ep->queue))) {
1107 +               local_irq_restore(flags);
1108 +               return -EAGAIN;
1109 +       }
1110 +
1111 +       /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1112 +       *ep->reg_udccsr = UDCCSR_FST|UDCCSR_FEF;
1113 +
1114 +       /* ep0 needs special care */
1115 +       if (!ep->desc) {
1116 +               start_watchdog(ep->dev);
1117 +               ep->dev->req_pending = 0;
1118 +               ep->dev->ep0state = EP0_STALL;
1119 +               LED_EP0_OFF;
1120 +
1121 +       /* and bulk/intr endpoints like dropping stalls too */
1122 +       } else {
1123 +               unsigned i;
1124 +               for (i = 0; i < 1000; i += 20) {
1125 +                       if (*ep->reg_udccsr & UDCCSR_SST)
1126 +                               break;
1127 +                       udelay(20);
1128 +               }
1129 +       }
1130 +       local_irq_restore(flags);
1131 +
1132 +       DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1133 +       return 0;
1134 +}
1135 +
1136 +static int pxa27x_ep_fifo_status(struct usb_ep *_ep)
1137 +{
1138 +       struct pxa27x_ep        *ep;
1139 +
1140 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1141 +       if (!_ep) {
1142 +               DMSG("%s, bad ep\n", __FUNCTION__);
1143 +               return -ENODEV;
1144 +       }
1145 +       /* pxa can't report unclaimed bytes from IN fifos */
1146 +       if (ep->dir_in)
1147 +               return -EOPNOTSUPP;
1148 +       if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1149 +                       || (*ep->reg_udccsr & UDCCSR_FS) == 0)
1150 +               return 0;
1151 +       else
1152 +               return (*ep->reg_udcbcr & 0xfff) + 1;
1153 +}
1154 +
1155 +static void pxa27x_ep_fifo_flush(struct usb_ep *_ep)
1156 +{
1157 +       struct pxa27x_ep        *ep;
1158 +
1159 +       ep = container_of(_ep, struct pxa27x_ep, ep);
1160 +       if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1161 +               DMSG("%s, bad ep\n", __FUNCTION__);
1162 +               return;
1163 +       }
1164 +
1165 +       /* toggle and halt bits stay unchanged */
1166 +
1167 +       /* for OUT, just read and discard the FIFO contents. */
1168 +       if (!ep->dir_in) {
1169 +               while (((*ep->reg_udccsr) & UDCCSR_BNE) != 0)
1170 +                       (void) *ep->reg_udcdr;
1171 +               return;
1172 +       }
1173 +
1174 +       /* most IN status is the same, but ISO can't stall */
1175 +       *ep->reg_udccsr = UDCCSR_PC|UDCCSR_FST|UDCCSR_TRN
1176 +               | (ep->ep_type == USB_ENDPOINT_XFER_ISOC)
1177 +                       ? 0 : UDCCSR_SST;
1178 +}
1179 +
1180 +
1181 +static struct usb_ep_ops pxa27x_ep_ops = {
1182 +       .enable         = pxa27x_ep_enable,
1183 +       .disable        = pxa27x_ep_disable,
1184 +
1185 +       .alloc_request  = pxa27x_ep_alloc_request,
1186 +       .free_request   = pxa27x_ep_free_request,
1187 +
1188 +       .alloc_buffer   = pxa27x_ep_alloc_buffer,
1189 +       .free_buffer    = pxa27x_ep_free_buffer,
1190 +
1191 +       .queue          = pxa27x_ep_queue,
1192 +       .dequeue        = pxa27x_ep_dequeue,
1193 +
1194 +       .set_halt       = pxa27x_ep_set_halt,
1195 +       .fifo_status    = pxa27x_ep_fifo_status,
1196 +       .fifo_flush     = pxa27x_ep_fifo_flush,
1197 +};
1198 +
1199 +
1200 +/* ---------------------------------------------------------------------------
1201 + *     device-scoped parts of the api to the usb controller hardware
1202 + * ---------------------------------------------------------------------------
1203 + */
1204 +
1205 +static int pxa27x_udc_get_frame(struct usb_gadget *_gadget)
1206 +{
1207 +       return (UDCFNR & 0x3FF);
1208 +}
1209 +
1210 +static int pxa27x_udc_wakeup(struct usb_gadget *_gadget)
1211 +{
1212 +       /* host may not have enabled remote wakeup */
1213 +       if ((UDCCR & UDCCR_DWRE) == 0)
1214 +               return -EHOSTUNREACH;
1215 +       udc_set_mask_UDCCR(UDCCR_UDR);
1216 +       return 0;
1217 +}
1218 +
1219 +static const struct usb_gadget_ops pxa27x_udc_ops = {
1220 +       .get_frame       = pxa27x_udc_get_frame,
1221 +       .wakeup          = pxa27x_udc_wakeup,
1222 +       // current versions must always be self-powered
1223 +};
1224 +
1225 +
1226 +/*-------------------------------------------------------------------------*/
1227 +
1228 +#ifdef UDC_PROC_FILE
1229 +
1230 +static const char proc_node_name [] = "driver/udc";
1231 +
1232 +static int
1233 +udc_proc_read(char *page, char **start, off_t off, int count,
1234 +               int *eof, void *_dev)
1235 +{
1236 +       char                    *buf = page;
1237 +       struct pxa27x_udc       *dev = _dev;
1238 +       char                    *next = buf;
1239 +       unsigned                size = count;
1240 +       unsigned long           flags;
1241 +       int                     i, t;
1242 +       u32                     tmp;
1243 +
1244 +       if (off != 0)
1245 +               return 0;
1246 +
1247 +       local_irq_save(flags);
1248 +
1249 +       /* basic device status */
1250 +       t = scnprintf(next, size, DRIVER_DESC "\n"
1251 +               "%s version: %s\nGadget driver: %s\n",
1252 +               driver_name, DRIVER_VERSION SIZE_STR DMASTR,
1253 +               dev->driver ? dev->driver->driver.name : "(none)");
1254 +       size -= t;
1255 +       next += t;
1256 +
1257 +       /* registers for device and ep0 */
1258 +       t = scnprintf(next, size,
1259 +               "uicr %02X.%02X, usir %02X.%02x, ufnr %02X\n",
1260 +               UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
1261 +       size -= t;
1262 +       next += t;
1263 +
1264 +       tmp = UDCCR;
1265 +       t = scnprintf(next, size,"udccr %02X =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n", tmp,
1266 +               (tmp & UDCCR_OEN) ? " oen":"",
1267 +               (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
1268 +               (tmp & UDCCR_AHNP) ? " rem" : "",
1269 +               (tmp & UDCCR_BHNP) ? " rstir" : "",
1270 +               (tmp & UDCCR_DWRE) ? " dwre" : "",
1271 +               (tmp & UDCCR_SMAC) ? " smac" : "",
1272 +               (tmp & UDCCR_EMCE) ? " emce" : "",
1273 +               (tmp & UDCCR_UDR) ? " udr" : "",
1274 +               (tmp & UDCCR_UDA) ? " uda" : "",
1275 +               (tmp & UDCCR_UDE) ? " ude" : "",
1276 +               (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
1277 +               (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
1278 +               (tmp & UDCCR_AAISN)>> UDCCR_AAISN_S );
1279 +
1280 +       size -= t;
1281 +       next += t;
1282 +
1283 +       tmp = UDCCSR0;
1284 +       t = scnprintf(next, size,
1285 +               "udccsr0 %02X =%s%s%s%s%s%s%s\n", tmp,
1286 +               (tmp & UDCCSR0_SA) ? " sa" : "",
1287 +               (tmp & UDCCSR0_RNE) ? " rne" : "",
1288 +               (tmp & UDCCSR0_FST) ? " fst" : "",
1289 +               (tmp & UDCCSR0_SST) ? " sst" : "",
1290 +               (tmp & UDCCSR0_DME) ? " dme" : "",
1291 +               (tmp & UDCCSR0_IPR) ? " ipr" : "",
1292 +               (tmp & UDCCSR0_OPC) ? " opc" : "");
1293 +       size -= t;
1294 +       next += t;
1295 +
1296 +       if (!dev->driver)
1297 +               goto done;
1298 +
1299 +       t = scnprintf(next, size, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1300 +               dev->stats.write.bytes, dev->stats.write.ops,
1301 +               dev->stats.read.bytes, dev->stats.read.ops,
1302 +               dev->stats.irqs);
1303 +       size -= t;
1304 +       next += t;
1305 +
1306 +       /* dump endpoint queues */
1307 +       for (i = 0; i < UDC_EP_NUM; i++) {
1308 +               struct pxa27x_ep        *ep = &dev->ep [i];
1309 +               struct pxa27x_request   *req;
1310 +               int                     t;
1311 +
1312 +               if (i != 0) {
1313 +                       const struct usb_endpoint_descriptor    *d;
1314 +
1315 +                       d = ep->desc;
1316 +                       if (!d)
1317 +                               continue;
1318 +                       tmp = *dev->ep [i].reg_udccsr;
1319 +                       t = scnprintf(next, size,
1320 +                               "%s max %d %s udccs %02x udccr:0x%x\n",
1321 +                               ep->ep.name, le16_to_cpu (d->wMaxPacketSize),
1322 +                               (ep->dma >= 0) ? "dma" : "pio", tmp,
1323 +                               *dev->ep[i].reg_udccr);
1324 +                       /* TODO translate all five groups of udccs bits! */
1325 +
1326 +               } else /* ep0 should only have one transfer queued */
1327 +                       t = scnprintf(next, size, "ep0 max 16 pio irqs %lu\n",
1328 +                               ep->pio_irqs);
1329 +               if (t <= 0 || t > size)
1330 +                       goto done;
1331 +               size -= t;
1332 +               next += t;
1333 +
1334 +               if (list_empty(&ep->queue)) {
1335 +                       t = scnprintf(next, size, "\t(nothing queued)\n");
1336 +                       if (t <= 0 || t > size)
1337 +                               goto done;
1338 +                       size -= t;
1339 +                       next += t;
1340 +                       continue;
1341 +               }
1342 +               list_for_each_entry(req, &ep->queue, queue) {
1343 +#ifdef USE_DMA
1344 +                       if (ep->dma >= 0 && req->queue.prev == &ep->queue)
1345 +                               t = scnprintf(next, size,
1346 +                                       "\treq %p len %d/%d "
1347 +                                       "buf %p (dma%d dcmd %08x)\n",
1348 +                                       &req->req, req->req.actual,
1349 +                                       req->req.length, req->req.buf,
1350 +                                       ep->dma, DCMD(ep->dma)
1351 +                                       // low 13 bits == bytes-to-go
1352 +                                       );
1353 +                       else
1354 +#endif
1355 +                               t = scnprintf(next, size,
1356 +                                       "\treq %p len %d/%d buf %p\n",
1357 +                                       &req->req, req->req.actual,
1358 +                                       req->req.length, req->req.buf);
1359 +                       if (t <= 0 || t > size)
1360 +                               goto done;
1361 +                       size -= t;
1362 +                       next += t;
1363 +               }
1364 +       }
1365 +
1366 +done:
1367 +       local_irq_restore(flags);
1368 +       *eof = 1;
1369 +       return count - size;
1370 +}
1371 +
1372 +#define create_proc_files() \
1373 +       create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1374 +#define remove_proc_files() \
1375 +       remove_proc_entry(proc_node_name, NULL)
1376 +
1377 +#else  /* !UDC_PROC_FILE */
1378 +#define create_proc_files() do {} while (0)
1379 +#define remove_proc_files() do {} while (0)
1380 +
1381 +#endif /* UDC_PROC_FILE */
1382 +
1383 +/* "function" sysfs attribute */
1384 +static ssize_t
1385 +show_function (struct device *_dev, struct device_attribute *attr, char *buf)
1386 +{
1387 +       struct pxa27x_udc       *dev = dev_get_drvdata (_dev);
1388 +
1389 +       if (!dev->driver
1390 +                       || !dev->driver->function
1391 +                       || strlen (dev->driver->function) > PAGE_SIZE)
1392 +               return 0;
1393 +       return scnprintf (buf, PAGE_SIZE, "%s\n", dev->driver->function);
1394 +}
1395 +static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
1396 +
1397 +/*-------------------------------------------------------------------------*/
1398 +
1399 +/*
1400 + *     udc_disable - disable USB device controller
1401 + */
1402 +static void udc_disable(struct pxa27x_udc *dev)
1403 +{
1404 +       UDCICR0 = UDCICR1 = 0x00000000;
1405 +
1406 +       udc_clear_mask_UDCCR(UDCCR_UDE);
1407 +
1408 +        /* Disable clock for USB device */
1409 +       pxa_set_cken(CKEN11_USB, 0);
1410 +
1411 +       ep0_idle (dev);
1412 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
1413 +       LED_CONNECTED_OFF;
1414 +       if (dev->mach->udc_command)
1415 +               dev->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1416 +}
1417 +
1418 +
1419 +/*
1420 + *     udc_reinit - initialize software state
1421 + */
1422 +static void udc_reinit(struct pxa27x_udc *dev)
1423 +{
1424 +       u32     i;
1425 +
1426 +       dev->ep0state = EP0_IDLE;
1427 +
1428 +       /* basic endpoint records init */
1429 +       for (i = 0; i < UDC_EP_NUM; i++) {
1430 +               struct pxa27x_ep *ep = &dev->ep[i];
1431 +
1432 +               ep->stopped = 0;
1433 +               ep->pio_irqs = ep->dma_irqs = 0;
1434 +       }
1435 +       dev->configuration = 0;
1436 +       dev->interface = 0;
1437 +       dev->alternate = 0;
1438 +       /* the rest was statically initialized, and is read-only */
1439 +}
1440 +
1441 +/* until it's enabled, this UDC should be completely invisible
1442 + * to any USB host.
1443 + */
1444 +static void udc_enable (struct pxa27x_udc *dev)
1445 +{
1446 +       udc_clear_mask_UDCCR(UDCCR_UDE);
1447 +
1448 +       // MST_MSCWR2 &= ~(MST_MSCWR2_nUSBC_SC);
1449 +
1450 +        /* Enable clock for USB device */
1451 +       pxa_set_cken(CKEN11_USB, 1);
1452 +
1453 +       UDCICR0 = UDCICR1 = 0;
1454 +
1455 +       ep0_idle(dev);
1456 +       dev->gadget.speed = USB_SPEED_FULL;
1457 +       dev->stats.irqs = 0;
1458 +
1459 +       udc_set_mask_UDCCR(UDCCR_UDE);
1460 +       udelay (2);
1461 +       if (UDCCR & UDCCR_EMCE)
1462 +       {
1463 +               printk(KERN_ERR ": There are error in configuration, udc disabled\n");
1464 +       }
1465 +
1466 +       /* caller must be able to sleep in order to cope
1467 +        * with startup transients.
1468 +        */
1469 +       msleep(100);
1470 +
1471 +       /* enable suspend/resume and reset irqs */
1472 +       UDCICR1 = UDCICR1_IECC | UDCICR1_IERU | UDCICR1_IESU | UDCICR1_IERS;
1473 +
1474 +       /* enable ep0 irqs */
1475 +       UDCICR0 = UDCICR_INT(0,UDCICR_INT_MASK);
1476 +#if 0
1477 +       for(i=1; i < UDC_EP_NUM; i++) {
1478 +               if (dev->ep[i].assigned)
1479 +                       pio_irq_enable(i);
1480 +       }
1481 +#endif
1482 +       if (dev->mach->udc_command)
1483 +               dev->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
1484 +}
1485 +
1486 +
1487 +/* when a driver is successfully registered, it will receive
1488 + * control requests including set_configuration(), which enables
1489 + * non-control requests.  then usb traffic follows until a
1490 + * disconnect is reported.  then a host may connect again, or
1491 + * the driver might get unbound.
1492 + */
1493 +int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1494 +{
1495 +       struct pxa27x_udc       *dev = the_controller;
1496 +       int                     retval;
1497 +#if 0
1498 +       DMSG("dev=0x%x, driver=0x%x, speed=%d,"
1499 +                       "bind=0x%x, unbind=0x%x, disconnect=0x%x, setup=0x%x\n",
1500 +                       (unsigned)dev, (unsigned)driver, driver->speed,
1501 +                       (unsigned)driver->bind, (unsigned)driver->unbind,
1502 +                       (unsigned)driver->disconnect, (unsigned)driver->setup);
1503 +#endif
1504 +       if (!driver     || driver->speed != USB_SPEED_FULL
1505 +                       || !driver->bind
1506 +                       || !driver->unbind
1507 +                       || !driver->disconnect
1508 +                       || !driver->setup)
1509 +               return -EINVAL;
1510 +       if (!dev)
1511 +               return -ENODEV;
1512 +       if (dev->driver)
1513 +               return -EBUSY;
1514 +
1515 +       /* first hook up the driver ... */
1516 +       dev->driver = driver;
1517 +       dev->gadget.dev.driver = &driver->driver;
1518 +
1519 +       device_add (&dev->gadget.dev);
1520 +       retval = driver->bind(&dev->gadget);
1521 +       if (retval) {
1522 +               DMSG("bind to driver %s --> error %d\n",
1523 +                               driver->driver.name, retval);
1524 +               device_del (&dev->gadget.dev);
1525 +
1526 +               dev->driver = 0;
1527 +               dev->gadget.dev.driver = 0;
1528 +               return retval;
1529 +       }
1530 +       device_create_file(dev->dev, &dev_attr_function);
1531 +
1532 +       /* ... then enable host detection and ep0; and we're ready
1533 +        * for set_configuration as well as eventual disconnect.
1534 +        * NOTE:  this shouldn't power up until later.
1535 +        */
1536 +       DMSG("registered gadget driver '%s'\n", driver->driver.name);
1537 +       udc_enable(dev);
1538 +       dump_state(dev);
1539 +       return 0;
1540 +}
1541 +EXPORT_SYMBOL(usb_gadget_register_driver);
1542 +
1543 +static void
1544 +stop_activity(struct pxa27x_udc *dev, struct usb_gadget_driver *driver)
1545 +{
1546 +       int i;
1547 +
1548 +       DMSG("Trace path 1\n");
1549 +       /* don't disconnect drivers more than once */
1550 +       if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1551 +               driver = 0;
1552 +       dev->gadget.speed = USB_SPEED_UNKNOWN;
1553 +
1554 +       /* prevent new request submissions, kill any outstanding requests  */
1555 +       for (i = 0; i < UDC_EP_NUM; i++) {
1556 +               struct pxa27x_ep *ep = &dev->ep[i];
1557 +
1558 +               ep->stopped = 1;
1559 +               nuke(ep, -ESHUTDOWN);
1560 +       }
1561 +       del_timer_sync(&dev->timer);
1562 +
1563 +       /* report disconnect; the driver is already quiesced */
1564 +       if (driver)
1565 +               driver->disconnect(&dev->gadget);
1566 +
1567 +       /* re-init driver-visible data structures */
1568 +       udc_reinit(dev);
1569 +}
1570 +
1571 +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1572 +{
1573 +       struct pxa27x_udc       *dev = the_controller;
1574 +
1575 +       if (!dev)
1576 +               return -ENODEV;
1577 +       if (!driver || driver != dev->driver)
1578 +               return -EINVAL;
1579 +
1580 +       local_irq_disable();
1581 +       udc_disable(dev);
1582 +       stop_activity(dev, driver);
1583 +       local_irq_enable();
1584 +
1585 +       driver->unbind(&dev->gadget);
1586 +       dev->driver = 0;
1587 +
1588 +       device_del (&dev->gadget.dev);
1589 +       device_remove_file(dev->dev, &dev_attr_function);
1590 +
1591 +       DMSG("unregistered gadget driver '%s'\n", driver->driver.name);
1592 +       dump_state(dev);
1593 +       return 0;
1594 +}
1595 +EXPORT_SYMBOL(usb_gadget_unregister_driver);
1596 +
1597 +#ifndef        enable_disconnect_irq
1598 +#define        enable_disconnect_irq()         do {} while (0)
1599 +#define        disable_disconnect_irq()        do {} while (0)
1600 +#endif
1601 +
1602 +
1603 +/*-------------------------------------------------------------------------*/
1604 +
1605 +static inline void clear_ep_state (struct pxa27x_udc *dev)
1606 +{
1607 +       unsigned i;
1608 +
1609 +       /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1610 +        * fifos, and pending transactions mustn't be continued in any case.
1611 +        */
1612 +       for (i = 1; i < UDC_EP_NUM; i++)
1613 +               nuke(&dev->ep[i], -ECONNABORTED);
1614 +}
1615 +
1616 +static void udc_watchdog(unsigned long _dev)
1617 +{
1618 +       struct pxa27x_udc       *dev = (void *)_dev;
1619 +
1620 +       local_irq_disable();
1621 +       if (dev->ep0state == EP0_STALL
1622 +                       && (UDCCSR0 & UDCCSR0_FST) == 0
1623 +                       && (UDCCSR0 & UDCCSR0_SST) == 0) {
1624 +               UDCCSR0 = UDCCSR0_FST|UDCCSR0_FTF;
1625 +               DBG(DBG_VERBOSE, "ep0 re-stall\n");
1626 +               start_watchdog(dev);
1627 +       }
1628 +       local_irq_enable();
1629 +}
1630 +
1631 +static void handle_ep0 (struct pxa27x_udc *dev)
1632 +{
1633 +       u32                     udccsr0 = UDCCSR0;
1634 +       struct pxa27x_ep        *ep = &dev->ep [0];
1635 +       struct pxa27x_request   *req;
1636 +       union {
1637 +               struct usb_ctrlrequest  r;
1638 +               u8                      raw [8];
1639 +               u32                     word [2];
1640 +       } u;
1641 +
1642 +       if (list_empty(&ep->queue))
1643 +               req = 0;
1644 +       else
1645 +               req = list_entry(ep->queue.next, struct pxa27x_request, queue);
1646 +
1647 +       /* clear stall status */
1648 +       if (udccsr0 & UDCCSR0_SST) {
1649 +               nuke(ep, -EPIPE);
1650 +               UDCCSR0 = UDCCSR0_SST;
1651 +               del_timer(&dev->timer);
1652 +               ep0_idle(dev);
1653 +       }
1654 +
1655 +       /* previous request unfinished?  non-error iff back-to-back ... */
1656 +       if ((udccsr0 & UDCCSR0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1657 +               nuke(ep, 0);
1658 +               del_timer(&dev->timer);
1659 +               ep0_idle(dev);
1660 +       }
1661 +
1662 +       switch (dev->ep0state) {
1663 +       case EP0_NO_ACTION:
1664 +               printk(KERN_INFO"%s: Busy\n", __FUNCTION__);
1665 +               /*Fall through */
1666 +       case EP0_IDLE:
1667 +               /* late-breaking status? */
1668 +               udccsr0 = UDCCSR0;
1669 +
1670 +               /* start control request? */
1671 +               if (likely((udccsr0 & (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))
1672 +                               == (UDCCSR0_OPC|UDCCSR0_SA|UDCCSR0_RNE))) {
1673 +                       int i;
1674 +
1675 +                       nuke (ep, -EPROTO);
1676 +                       /* read SETUP packet */
1677 +                       for (i = 0; i < 2; i++) {
1678 +                               if (unlikely(!(UDCCSR0 & UDCCSR0_RNE))) {
1679 +bad_setup:
1680 +                                       DMSG("SETUP %d!\n", i);
1681 +                                       goto stall;
1682 +                               }
1683 +                               u.word [i] =  UDCDR0;
1684 +                       }
1685 +                       if (unlikely((UDCCSR0 & UDCCSR0_RNE) != 0))
1686 +                               goto bad_setup;
1687 +
1688 +                       le16_to_cpus (&u.r.wValue);
1689 +                       le16_to_cpus (&u.r.wIndex);
1690 +                       le16_to_cpus (&u.r.wLength);
1691 +
1692 +                       LED_EP0_ON;
1693 +
1694 +                       DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1695 +                               u.r.bRequestType, u.r.bRequest,
1696 +                               u.r.wValue, u.r.wIndex, u.r.wLength);
1697 +                       /* cope with automagic for some standard requests. */
1698 +                       dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1699 +                                               == USB_TYPE_STANDARD;
1700 +                       dev->req_config = 0;
1701 +                       dev->req_pending = 1;
1702 +#if 0
1703 +                       switch (u.r.bRequest) {
1704 +                       /* hardware was supposed to hide this */
1705 +                       case USB_REQ_SET_CONFIGURATION:
1706 +                       case USB_REQ_SET_INTERFACE:
1707 +                       case USB_REQ_SET_ADDRESS:
1708 +                               printk(KERN_ERR "Should not come here\n");
1709 +                               break;
1710 +                       }
1711 +
1712 +#endif
1713 +                       if (u.r.bRequestType & USB_DIR_IN)
1714 +                               dev->ep0state = EP0_IN_DATA_PHASE;
1715 +                       else
1716 +                               dev->ep0state = EP0_OUT_DATA_PHASE;
1717 +                       i = dev->driver->setup(&dev->gadget, &u.r);
1718 +
1719 +                       if (i < 0) {
1720 +                               /* hardware automagic preventing STALL... */
1721 +                               if (dev->req_config) {
1722 +                                       /* hardware sometimes neglects to tell
1723 +                                        * tell us about config change events,
1724 +                                        * so later ones may fail...
1725 +                                        */
1726 +                                       WARN("config change %02x fail %d?\n",
1727 +                                               u.r.bRequest, i);
1728 +                                       return;
1729 +                                       /* TODO experiment:  if has_cfr,
1730 +                                        * hardware didn't ACK; maybe we
1731 +                                        * could actually STALL!
1732 +                                        */
1733 +                               }
1734 +                               DBG(DBG_VERBOSE, "protocol STALL, "
1735 +                                       "%02x err %d\n", UDCCSR0, i);
1736 +stall:
1737 +                               /* the watchdog timer helps deal with cases
1738 +                                * where udc seems to clear FST wrongly, and
1739 +                                * then NAKs instead of STALLing.
1740 +                                */
1741 +                               ep0start(dev, UDCCSR0_FST|UDCCSR0_FTF, "stall");
1742 +                               start_watchdog(dev);
1743 +                               dev->ep0state = EP0_STALL;
1744 +                               LED_EP0_OFF;
1745 +
1746 +                       /* deferred i/o == no response yet */
1747 +                       } else if (dev->req_pending) {
1748 +                               if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1749 +                                               || dev->req_std || u.r.wLength))
1750 +                                       ep0start(dev, 0, "defer");
1751 +                               else
1752 +                                       ep0start(dev, UDCCSR0_IPR, "defer/IPR");
1753 +                       }
1754 +
1755 +                       /* expect at least one data or status stage irq */
1756 +                       return;
1757 +
1758 +               } else {
1759 +                       /* some random early IRQ:
1760 +                        * - we acked FST
1761 +                        * - IPR cleared
1762 +                        * - OPC got set, without SA (likely status stage)
1763 +                        */
1764 +                       UDCCSR0 = udccsr0 & (UDCCSR0_SA|UDCCSR0_OPC);
1765 +               }
1766 +               break;
1767 +       case EP0_IN_DATA_PHASE:                 /* GET_DESCRIPTOR etc */
1768 +               if (udccsr0 & UDCCSR0_OPC) {
1769 +                       UDCCSR0 = UDCCSR0_OPC|UDCCSR0_FTF;
1770 +                       DBG(DBG_VERBOSE, "ep0in premature status\n");
1771 +                       if (req)
1772 +                               done(ep, req, 0);
1773 +                       ep0_idle(dev);
1774 +               } else /* irq was IPR clearing */ {
1775 +                       if (req) {
1776 +                               /* this IN packet might finish the request */
1777 +                               (void) write_ep0_fifo(ep, req);
1778 +                       } /* else IN token before response was written */
1779 +               }
1780 +               break;
1781 +       case EP0_OUT_DATA_PHASE:                /* SET_DESCRIPTOR etc */
1782 +               if (udccsr0 & UDCCSR0_OPC) {
1783 +                       if (req) {
1784 +                               /* this OUT packet might finish the request */
1785 +                               if (read_ep0_fifo(ep, req))
1786 +                                       done(ep, req, 0);
1787 +                               /* else more OUT packets expected */
1788 +                       } /* else OUT token before read was issued */
1789 +               } else /* irq was IPR clearing */ {
1790 +                       DBG(DBG_VERBOSE, "ep0out premature status\n");
1791 +                       if (req)
1792 +                               done(ep, req, 0);
1793 +                       ep0_idle(dev);
1794 +               }
1795 +               break;
1796 +       case EP0_STALL:
1797 +               UDCCSR0 = UDCCSR0_FST;
1798 +               break;
1799 +               }
1800 +       UDCISR0 = UDCISR_INT(0, UDCISR_INT_MASK);
1801 +}
1802 +
1803 +
1804 +static void handle_ep(struct pxa27x_ep *ep)
1805 +{
1806 +       struct pxa27x_request   *req;
1807 +       int                     completed;
1808 +       u32                     udccsr=0;
1809 +
1810 +       DMSG("%s is called\n", __FUNCTION__);
1811 +       do {
1812 +               completed = 0;
1813 +               if (likely (!list_empty(&ep->queue))) {
1814 +                       req = list_entry(ep->queue.next,
1815 +                                       struct pxa27x_request, queue);
1816 +               } else
1817 +                       req = 0;
1818 +
1819 +//             udccsr = *ep->reg_udccsr;
1820 +               DMSG("%s: req:%p, udcisr0:0x%x udccsr %p:0x%x\n", __FUNCTION__,
1821 +                               req, UDCISR0, ep->reg_udccsr, *ep->reg_udccsr);
1822 +               if (unlikely(ep->dir_in)) {
1823 +                       udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
1824 +                       if (unlikely (udccsr))
1825 +                               *ep->reg_udccsr = udccsr;
1826 +
1827 +                       if (req && likely ((*ep->reg_udccsr & UDCCSR_FS) != 0))
1828 +                               completed = write_fifo(ep, req);
1829 +
1830 +               } else {
1831 +                       udccsr = (UDCCSR_SST | UDCCSR_TRN) & *ep->reg_udccsr;
1832 +                       if (unlikely(udccsr))
1833 +                               *ep->reg_udccsr = udccsr;
1834 +
1835 +                       /* fifos can hold packets, ready for reading... */
1836 +                       if (likely(req)) {
1837 +                               completed = read_fifo(ep, req);
1838 +                       } else {
1839 +                               pio_irq_disable (ep->ep_num);
1840 +                               *ep->reg_udccsr = UDCCSR_FEF;
1841 +                               DMSG("%s: no req for out data\n",
1842 +                                               __FUNCTION__);
1843 +                       }
1844 +               }
1845 +               ep->pio_irqs++;
1846 +       } while (completed);
1847 +}
1848 +
1849 +static void pxa27x_change_configuration (struct pxa27x_udc *dev)
1850 +{
1851 +       struct usb_ctrlrequest req ;
1852 +
1853 +       req.bRequestType = 0;
1854 +       req.bRequest = USB_REQ_SET_CONFIGURATION;
1855 +       req.wValue = dev->configuration;
1856 +       req.wIndex = 0;
1857 +       req.wLength = 0;
1858 +
1859 +       dev->ep0state = EP0_NO_ACTION;
1860 +       dev->driver->setup(&dev->gadget, &req);
1861 +
1862 +}
1863 +
1864 +static void pxa27x_change_interface (struct pxa27x_udc *dev)
1865 +{
1866 +       struct usb_ctrlrequest  req;
1867 +
1868 +       req.bRequestType = USB_RECIP_INTERFACE;
1869 +       req.bRequest = USB_REQ_SET_INTERFACE;
1870 +       req.wValue = dev->alternate;
1871 +       req.wIndex = dev->interface;
1872 +       req.wLength = 0;
1873 +
1874 +       dev->ep0state = EP0_NO_ACTION;
1875 +       dev->driver->setup(&dev->gadget, &req);
1876 +}
1877 +
1878 +/*
1879 + *     pxa27x_udc_irq - interrupt handler
1880 + *
1881 + * avoid delays in ep0 processing. the control handshaking isn't always
1882 + * under software control (pxa250c0 and the pxa255 are better), and delays
1883 + * could cause usb protocol errors.
1884 + */
1885 +static irqreturn_t
1886 +pxa27x_udc_irq(int irq, void *_dev)
1887 +{
1888 +       struct pxa27x_udc       *dev = _dev;
1889 +       int                     handled;
1890 +
1891 +       dev->stats.irqs++;
1892 +       HEX_DISPLAY(dev->stats.irqs);
1893 +
1894 +//     printk("\n");
1895 +       DBG(DBG_VERBOSE, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
1896 +                       "UDCCR:0x%08x\n", UDCISR0, UDCISR1, UDCCR);
1897 +       do {
1898 +               u32 udcir = UDCISR1 & 0xF8000000;
1899 +
1900 +               handled = 0;
1901 +
1902 +               /* SUSpend Interrupt Request */
1903 +               if (unlikely(udcir & UDCISR1_IRSU)) {
1904 +                       UDCISR1 = UDCISR1_IRSU;
1905 +                       handled = 1;
1906 +                       DBG(DBG_VERBOSE, "USB suspend\n");
1907 +                       if (dev->gadget.speed != USB_SPEED_UNKNOWN
1908 +                                       && dev->driver
1909 +                                       && dev->driver->suspend)
1910 +                               dev->driver->suspend(&dev->gadget);
1911 +                       ep0_idle (dev);
1912 +               }
1913 +
1914 +               /* RESume Interrupt Request */
1915 +               if (unlikely(udcir & UDCISR1_IRRU)) {
1916 +                       UDCISR1 = UDCISR1_IRRU;
1917 +                       handled = 1;
1918 +                       DBG(DBG_VERBOSE, "USB resume\n");
1919 +
1920 +                       if (dev->gadget.speed != USB_SPEED_UNKNOWN
1921 +                                       && dev->driver
1922 +                                       && dev->driver->resume)
1923 +                               dev->driver->resume(&dev->gadget);
1924 +               }
1925 +
1926 +               if (unlikely(udcir & UDCISR1_IRCC)) {
1927 +                       unsigned config, interface, alternate;
1928 +
1929 +                       handled = 1;
1930 +                       DBG(DBG_VERBOSE, "USB SET_CONFIGURATION or "
1931 +                               "SET_INTERFACE command received\n");
1932 +
1933 +                       UDCCR |= UDCCR_SMAC;
1934 +
1935 +                       config = (UDCCR & UDCCR_ACN) >> UDCCR_ACN_S;
1936 +
1937 +                       if (dev->configuration != config) {
1938 +                               dev->configuration = config;
1939 +                               pxa27x_change_configuration(dev) ;
1940 +                       }
1941 +
1942 +                       interface =  (UDCCR & UDCCR_AIN) >> UDCCR_AIN_S;
1943 +                       alternate = (UDCCR & UDCCR_AAISN) >> UDCCR_AAISN_S;
1944 +
1945 +                       if ( (dev->configuration != interface) || \
1946 +                                       (dev->alternate != alternate)){
1947 +                               dev->interface = config;
1948 +                               dev->alternate = alternate;
1949 +                               pxa27x_change_interface(dev);
1950 +                       }
1951 +
1952 +                       UDCISR1 = UDCISR1_IRCC;
1953 +                       DMSG("%s: con:%d,inter:%d,alt:%d\n",
1954 +                               __FUNCTION__, config,interface, alternate);
1955 +               }
1956 +
1957 +               /* ReSeT Interrupt Request - USB reset */
1958 +               if (unlikely(udcir & UDCISR1_IRRS)) {
1959 +                       UDCISR1 = UDCISR1_IRRS;
1960 +                       handled = 1;
1961 +
1962 +                       if ((UDCCR & UDCCR_UDA) == 0) {
1963 +                               DBG(DBG_VERBOSE, "USB reset start\n");
1964 +
1965 +                               /* reset driver and endpoints,
1966 +                                * in case that's not yet done
1967 +                                */
1968 +                               stop_activity (dev, dev->driver);
1969 +
1970 +                       }
1971 +                       INFO("USB reset\n");
1972 +                       dev->gadget.speed = USB_SPEED_FULL;
1973 +                       memset(&dev->stats, 0, sizeof dev->stats);
1974 +
1975 +               } else {
1976 +                       u32     udcisr0 = UDCISR0 ;
1977 +                       u32     udcisr1 = UDCISR1 & 0xFFFF;
1978 +                       int     i;
1979 +
1980 +                       if (unlikely (!udcisr0 && !udcisr1))
1981 +                               continue;
1982 +
1983 +                       DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", udcisr1,udcisr0);
1984 +
1985 +                       /* control traffic */
1986 +                       if (udcisr0 & UDCISR0_IR0) {
1987 +                               dev->ep[0].pio_irqs++;
1988 +                               handle_ep0(dev);
1989 +                               handled = 1;
1990 +                       }
1991 +
1992 +                       udcisr0 >>= 2;
1993 +                       /* endpoint data transfers */
1994 +                       for (i = 1; udcisr0!=0 && i < 16; udcisr0>>=2,i++) {
1995 +                               UDCISR0 = UDCISR_INT(i, UDCISR_INT_MASK);
1996 +
1997 +                               if (udcisr0 & UDC_INT_FIFOERROR)
1998 +                                       printk(KERN_ERR" Endpoint %d Fifo error\n", i);
1999 +                               if (udcisr0 & UDC_INT_PACKETCMP) {
2000 +                                       handle_ep(&dev->ep[i]);
2001 +                                       handled = 1;
2002 +                               }
2003 +
2004 +                       }
2005 +
2006 +                       for (i = 0; udcisr1!=0 && i < 8; udcisr1 >>= 2, i++) {
2007 +                               UDCISR1 = UDCISR_INT(i, UDCISR_INT_MASK);
2008 +
2009 +                               if (udcisr1 & UDC_INT_FIFOERROR) {
2010 +                                       printk(KERN_ERR" Endpoint %d fifo error\n", (i+16));
2011 +                               }
2012 +
2013 +                               if (udcisr1 & UDC_INT_PACKETCMP) {
2014 +                                       handle_ep(&dev->ep[i+16]);
2015 +                                       handled = 1;
2016 +                               }
2017 +                       }
2018 +               }
2019 +
2020 +               /* we could also ask for 1 msec SOF (SIR) interrupts */
2021 +
2022 +       } while (handled);
2023 +       return IRQ_HANDLED;
2024 +}
2025 +
2026 +static inline void validate_fifo_size(struct pxa27x_ep *pxa_ep, u8 bmAttributes)
2027 +{
2028 +       switch (bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2029 +       case USB_ENDPOINT_XFER_CONTROL:
2030 +               pxa_ep->fifo_size = EP0_FIFO_SIZE;
2031 +               break;
2032 +       case USB_ENDPOINT_XFER_ISOC:
2033 +               pxa_ep->fifo_size = ISO_FIFO_SIZE;
2034 +               break;
2035 +       case USB_ENDPOINT_XFER_BULK:
2036 +               pxa_ep->fifo_size = BULK_FIFO_SIZE;
2037 +               break;
2038 +       case USB_ENDPOINT_XFER_INT:
2039 +               pxa_ep->fifo_size = INT_FIFO_SIZE;
2040 +               break;
2041 +       default:
2042 +               break;
2043 +       }
2044 +}
2045 +
2046 +static void udc_init_ep(struct pxa27x_udc *dev)
2047 +{
2048 +       int i;
2049 +
2050 +       INIT_LIST_HEAD (&dev->gadget.ep_list);
2051 +       INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
2052 +
2053 +       for (i = 0; i < UDC_EP_NUM; i++) {
2054 +               struct pxa27x_ep *ep = &dev->ep[i];
2055 +
2056 +               ep->dma = -1;
2057 +               if (i != 0) {
2058 +                       memset(ep, 0, sizeof(*ep));
2059 +               }
2060 +               INIT_LIST_HEAD (&ep->queue);
2061 +       }
2062 +}
2063 +#define NAME_SIZE 18
2064 +
2065 +struct usb_ep* pxa27x_ep_config(
2066 +       struct usb_gadget *gadget,
2067 +       struct usb_endpoint_descriptor *desc,
2068 +       int config, int interface, int alt
2069 +)
2070 +{
2071 +       u32 tmp ;
2072 +       unsigned i;
2073 +       char* name;
2074 +       struct usb_ep * ep = NULL;
2075 +       struct pxa27x_ep *pxa_ep = NULL;
2076 +       struct pxa27x_udc *dev = the_controller;
2077 +
2078 +       DMSG("pxa27x_config_ep is called\n");
2079 +       DMSG(" usb endpoint descriptor is:\n"
2080 +               "       bLength:%d\n"
2081 +               "       bDescriptorType:%x\n"
2082 +               "       bEndpointAddress:%x\n"
2083 +               "       bmAttributes:%x\n"
2084 +               "       wMaxPacketSize:%d\n",
2085 +               desc->bLength,
2086 +               desc->bDescriptorType,desc->bEndpointAddress,
2087 +               desc->bmAttributes,desc->wMaxPacketSize);
2088 +
2089 +       for (i = 1; i < UDC_EP_NUM; i++) {
2090 +               if(!dev->ep[i].assigned) {
2091 +                       pxa_ep = &dev->ep[i];
2092 +                       pxa_ep->assigned = 1;
2093 +                       pxa_ep->ep_num = i;
2094 +                       break;
2095 +               }
2096 +       }
2097 +       if (unlikely(i == UDC_EP_NUM)) {
2098 +               printk(KERN_ERR __FILE__ ": Failed to find a spare endpoint\n");
2099 +               return ep;
2100 +       }
2101 +
2102 +
2103 +       ep = &pxa_ep->ep;
2104 +
2105 +       pxa_ep->dev = dev;
2106 +       pxa_ep->desc = desc;
2107 +       pxa_ep->pio_irqs = pxa_ep->dma_irqs = 0;
2108 +       pxa_ep->dma = -1;
2109 +
2110 +       if (!(desc->bEndpointAddress & 0xF))
2111 +               desc->bEndpointAddress |= i;
2112 +
2113 +       if (!(desc->wMaxPacketSize)) {
2114 +               validate_fifo_size(pxa_ep, desc->bmAttributes);
2115 +               desc->wMaxPacketSize = pxa_ep->fifo_size;
2116 +       } else
2117 +               pxa_ep->fifo_size = desc->wMaxPacketSize;
2118 +
2119 +       pxa_ep->dir_in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0;
2120 +       pxa_ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
2121 +       pxa_ep->stopped = 1;
2122 +       pxa_ep->dma_con = 0;
2123 +       pxa_ep->config = config;
2124 +       pxa_ep->interface = interface;
2125 +       pxa_ep->aisn = alt;
2126 +
2127 +       pxa_ep->reg_udccsr = &UDCCSR0 + i;
2128 +       pxa_ep->reg_udcbcr = &UDCBCR0 + i;
2129 +       pxa_ep->reg_udcdr = &UDCDR0 + i ;
2130 +       pxa_ep->reg_udccr = &UDCCRA - 1 + i;
2131 +#ifdef USE_DMA
2132 +       pxa_ep->reg_drcmr = &DRCMR24 + i;
2133 +#endif
2134 +
2135 +#if 0
2136 +       DMSG("udccsr=0x%8x, udcbcr=0x%8x, udcdr=0x%8x,"
2137 +                       "udccr0=0x%8x\n",
2138 +                       (unsigned)pxa_ep->reg_udccsr,
2139 +                       (unsigned)pxa_ep->reg_udcbcr,
2140 +                       (unsigned)pxa_ep->reg_udcdr,
2141 +                       (unsigned)pxa_ep->reg_udccr);
2142 +#endif
2143 +       /* Configure UDCCR */
2144 +       tmp = 0;
2145 +       tmp |= (pxa_ep->config << UDCCONR_CN_S) & UDCCONR_CN;
2146 +       tmp |= (pxa_ep->interface << UDCCONR_IN_S) & UDCCONR_IN;
2147 +       tmp |= (pxa_ep->aisn << UDCCONR_AISN_S) & UDCCONR_AISN;
2148 +       tmp |= (desc->bEndpointAddress << UDCCONR_EN_S) & UDCCONR_EN;
2149 +       tmp |= (pxa_ep->ep_type << UDCCONR_ET_S) & UDCCONR_ET;
2150 +       tmp |= (pxa_ep->dir_in) ? UDCCONR_ED : 0;
2151 +       tmp |= (min(pxa_ep->fifo_size,  (unsigned)desc->wMaxPacketSize) \
2152 +                       << UDCCONR_MPS_S ) & UDCCONR_MPS;
2153 +       tmp |= UDCCONR_DE | UDCCONR_EE;
2154 +//     tmp |= UDCCONR_EE;
2155 +
2156 +       *pxa_ep->reg_udccr = tmp;
2157 +
2158 +#ifdef USE_DMA
2159 +       /* Only BULK use DMA */
2160 +       if ((pxa_ep->ep_type & USB_ENDPOINT_XFERTYPE_MASK)\
2161 +                       == USB_ENDPOINT_XFER_BULK)
2162 +               *pxa_ep->reg_udccsr = UDCCSR_DME;
2163 +#endif
2164 +
2165 +       DMSG("UDCCR: 0x%p is 0x%x\n", pxa_ep->reg_udccr,*pxa_ep->reg_udccr);
2166 +
2167 +       /* Fill ep name*/
2168 +       name = kmalloc(NAME_SIZE, GFP_KERNEL);
2169 +       if (!name) {
2170 +               printk(KERN_ERR "%s: Error\n", __FUNCTION__);
2171 +               return NULL;
2172 +       }
2173 +
2174 +       switch (pxa_ep->ep_type) {
2175 +       case USB_ENDPOINT_XFER_BULK:
2176 +               sprintf(name, "Bulk-%s-%d", (pxa_ep->dir_in ? "in":"out"), i);
2177 +               break;
2178 +       case USB_ENDPOINT_XFER_INT:
2179 +               sprintf(name, "Interrupt-%s-%d", (pxa_ep->dir_in ? \
2180 +                               "in":"out"), i);
2181 +               break;
2182 +       default:
2183 +               sprintf(name, "endpoint-%s-%d", (pxa_ep->dir_in ? \
2184 +                               "in":"out"), i);
2185 +               break;
2186 +       }
2187 +       ep->name = name;
2188 +
2189 +       ep->ops = &pxa27x_ep_ops;
2190 +       ep->maxpacket = min((ushort)pxa_ep->fifo_size, desc->wMaxPacketSize);
2191 +
2192 +       list_add_tail (&ep->ep_list, &gadget->ep_list);
2193 +       return ep;
2194 +}
2195 +
2196 +EXPORT_SYMBOL(pxa27x_ep_config);
2197 +
2198 +/*-------------------------------------------------------------------------*/
2199 +
2200 +static void nop_release (struct device *dev)
2201 +{
2202 +       DMSG("%s %s\n", __FUNCTION__, dev->bus_id);
2203 +}
2204 +
2205 +/* this uses load-time allocation and initialization (instead of
2206 + * doing it at run-time) to save code, eliminate fault paths, and
2207 + * be more obviously correct.
2208 + */
2209 +static struct pxa27x_udc memory = {
2210 +       .gadget = {
2211 +               .ops            = &pxa27x_udc_ops,
2212 +               .ep0            = &memory.ep[0].ep,
2213 +               .name           = driver_name,
2214 +               .dev = {
2215 +                       .bus_id         = "gadget",
2216 +                       .release        = nop_release,
2217 +               },
2218 +       },
2219 +
2220 +       /* control endpoint */
2221 +       .ep[0] = {
2222 +               .ep = {
2223 +                       .name           = ep0name,
2224 +                       .ops            = &pxa27x_ep_ops,
2225 +                       .maxpacket      = EP0_FIFO_SIZE,
2226 +               },
2227 +               .dev            = &memory,
2228 +               .reg_udccsr     = &UDCCSR0,
2229 +               .reg_udcdr      = &UDCDR0,
2230 +       }
2231 +};
2232 +
2233 +#define CP15R0_VENDOR_MASK     0xffffe000
2234 +
2235 +#define CP15R0_XSCALE_VALUE    0x69054000      /* intel/arm/xscale */
2236 +
2237 +/*
2238 + *     probe - binds to the platform device
2239 + */
2240 +static int __init pxa27x_udc_probe(struct platform_device *_dev)
2241 +{
2242 +       struct pxa27x_udc *dev = &memory;
2243 +       int retval;
2244 +       u32 chiprev;
2245 +
2246 +       /* insist on Intel/ARM/XScale */
2247 +       asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev));
2248 +       if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2249 +               printk(KERN_ERR "%s: not XScale!\n", driver_name);
2250 +               return -ENODEV;
2251 +       }
2252 +       /* other non-static parts of init */
2253 +       dev->dev = &_dev->dev;
2254 +       dev->mach = _dev->dev.platform_data;
2255 +
2256 +       init_timer(&dev->timer);
2257 +       dev->timer.function = udc_watchdog;
2258 +       dev->timer.data = (unsigned long) dev;
2259 +
2260 +       device_initialize(&dev->gadget.dev);
2261 +       dev->gadget.dev.parent = &_dev->dev;
2262 +       dev->gadget.dev.dma_mask = _dev->dev.dma_mask;
2263 +
2264 +       the_controller = dev;
2265 +       platform_set_drvdata(_dev, dev);
2266 +
2267 +       udc_disable(dev);
2268 +       udc_init_ep(dev);
2269 +       udc_reinit(dev);
2270 +
2271 +       /* irq setup after old hardware state is cleaned up */
2272 +       retval = request_irq(IRQ_USB, pxa27x_udc_irq,
2273 +                       SA_INTERRUPT, driver_name, dev);
2274 +       if (retval != 0) {
2275 +               printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2276 +                       driver_name, IRQ_USB, retval);
2277 +               return -EBUSY;
2278 +       }
2279 +       dev->got_irq = 1;
2280 +
2281 +       create_proc_files();
2282 +
2283 +       return 0;
2284 +}
2285 +
2286 +static int __exit pxa27x_udc_remove(struct platform_device *_dev)
2287 +{
2288 +       struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2289 +
2290 +       udc_disable(dev);
2291 +       remove_proc_files();
2292 +       usb_gadget_unregister_driver(dev->driver);
2293 +
2294 +       if (dev->got_irq) {
2295 +               free_irq(IRQ_USB, dev);
2296 +               dev->got_irq = 0;
2297 +       }
2298 +       if (machine_is_lubbock() && dev->got_disc) {
2299 +               free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2300 +               dev->got_disc = 0;
2301 +       }
2302 +       platform_set_drvdata(_dev, 0);
2303 +       the_controller = 0;
2304 +       return 0;
2305 +}
2306 +
2307 +#ifdef CONFIG_PM
2308 +static void pxa27x_udc_shutdown(struct platform_device *_dev)
2309 +{
2310 +       struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2311 +
2312 +        udc_disable(dev);
2313 +}
2314 +
2315 +static int pxa27x_udc_suspend(struct platform_device *_dev, pm_message_t state)
2316 +{
2317 +       int i;
2318 +       struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2319 +
2320 +       DMSG("%s is called\n", __FUNCTION__);
2321 +       dev->udccsr0 = UDCCSR0;
2322 +       for(i=1; (i<UDC_EP_NUM); i++) {
2323 +               if (dev->ep[i].assigned) {
2324 +                       struct pxa27x_ep *ep = &dev->ep[i];
2325 +
2326 +                       ep->udccsr_value = *ep->reg_udccsr;
2327 +                       ep->udccr_value = *ep->reg_udccr;
2328 +                       DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2329 +                               i, *ep->reg_udccsr, *ep->reg_udccr);
2330 +               }
2331 +       }
2332 +
2333 +       udc_clear_mask_UDCCR(UDCCR_UDE);
2334 +       pxa_set_cken(CKEN11_USB, 0);
2335 +       // MST_MSCWR2 |= MST_MSCWR2_nUSBC_SC;
2336 +
2337 +       return 0;
2338 +}
2339 +
2340 +static int pxa27x_udc_resume(struct platform_device *_dev)
2341 +{
2342 +       int i;
2343 +       struct pxa27x_udc *dev = (struct pxa27x_udc*)platform_get_drvdata(_dev);
2344 +
2345 +       DMSG("%s is called\n", __FUNCTION__);
2346 +
2347 +       UDCCSR0 = dev->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME);
2348 +       for (i=1; i < UDC_EP_NUM; i++) {
2349 +               if (dev->ep[i].assigned) {
2350 +                       struct pxa27x_ep *ep = &dev->ep[i];
2351 +
2352 +                       *ep->reg_udccsr = ep->udccsr_value;
2353 +                       *ep->reg_udccr = ep->udccr_value;
2354 +                       DMSG("EP%d, udccsr:0x%x, udccr:0x%x\n",
2355 +                               i, *ep->reg_udccsr, *ep->reg_udccr);
2356 +               }
2357 +       }
2358 +       udc_enable(dev);
2359 +       /* OTGPH bit is set when sleep mode is entered.
2360 +           * it indicates that OTG pad is retaining its state.
2361 +           * Upon exit from sleep mode and before clearing OTGPH,
2362 +           * Software must configure the USB OTG pad, UDC, and UHC
2363 +           * to the state they were in before entering sleep mode.*/
2364 +       PSSR  |= PSSR_OTGPH;
2365 +       return 0;
2366 +}
2367 +#endif
2368 +
2369 +/*-------------------------------------------------------------------------*/
2370 +
2371 +static struct platform_driver udc_driver = {
2372 +       .driver         = {
2373 +               .name   = "pxa2xx-udc",
2374 +       },
2375 +       .probe          = pxa27x_udc_probe,
2376 +       .remove         = __exit_p(pxa27x_udc_remove),
2377 +
2378 +#ifdef CONFIG_PM
2379 +       // FIXME power management support
2380 +        .shutdown = pxa27x_udc_shutdown,
2381 +       .suspend = pxa27x_udc_suspend,
2382 +       .resume = pxa27x_udc_resume
2383 +#endif
2384 +};
2385 +
2386 +static int __init udc_init(void)
2387 +{
2388 +       printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
2389 +       return platform_driver_register(&udc_driver);
2390 +}
2391 +module_init(udc_init);
2392 +
2393 +static void __exit udc_exit(void)
2394 +{
2395 +       platform_driver_unregister(&udc_driver);
2396 +}
2397 +module_exit(udc_exit);
2398 +
2399 +MODULE_DESCRIPTION(DRIVER_DESC);
2400 +MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2401 +MODULE_LICENSE("GPL");
2402 +
2403 Index: linux-2.6.21gum/drivers/usb/gadget/pxa27x_udc.h
2404 ===================================================================
2405 --- /dev/null
2406 +++ linux-2.6.21gum/drivers/usb/gadget/pxa27x_udc.h
2407 @@ -0,0 +1,332 @@
2408 +/*
2409 + * linux/drivers/usb/gadget/pxa27x_udc.h
2410 + * Intel PXA27x on-chip full speed USB device controller
2411 + *
2412 + * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
2413 + * Copyright (C) 2003 David Brownell
2414 + * Copyright (C) 2004 Intel Corporation
2415 + *
2416 + * This program is free software; you can redistribute it and/or modify
2417 + * it under the terms of the GNU General Public License as published by
2418 + * the Free Software Foundation; either version 2 of the License, or
2419 + * (at your option) any later version.
2420 + *
2421 + * This program is distributed in the hope that it will be useful,
2422 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2423 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2424 + * GNU General Public License for more details.
2425 + *
2426 + * You should have received a copy of the GNU General Public License
2427 + * along with this program; if not, write to the Free Software
2428 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2429 + */
2430 +
2431 +#ifndef __LINUX_USB_GADGET_PXA27X_H
2432 +#define __LINUX_USB_GADGET_PXA27X_H
2433 +
2434 +#include <linux/types.h>
2435 +
2436 +struct pxa27x_udc;
2437 +
2438 +struct pxa27x_ep {
2439 +       struct usb_ep                           ep;
2440 +       struct pxa27x_udc                       *dev;
2441 +
2442 +       const struct usb_endpoint_descriptor    *desc;
2443 +       struct list_head                        queue;
2444 +       unsigned long                           pio_irqs;
2445 +       unsigned long                           dma_irqs;
2446 +
2447 +       int                                     dma;
2448 +       unsigned                                fifo_size;
2449 +       unsigned                                ep_num;
2450 +       unsigned                                ep_type;
2451 +
2452 +       unsigned                                stopped : 1;
2453 +       unsigned                                dma_con : 1;
2454 +       unsigned                                dir_in : 1;
2455 +       unsigned                                assigned : 1;
2456 +
2457 +       unsigned                                config;
2458 +       unsigned                                interface;
2459 +       unsigned                                aisn;
2460 +       /* UDCCSR = UDC Control/Status Register for this EP
2461 +        * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
2462 +        * UDCDR = UDC Endpoint Data Register (the fifo)
2463 +        * UDCCR = UDC Endpoint Configuration Registers
2464 +        * DRCM = DMA Request Channel Map
2465 +        */
2466 +       volatile u32                            *reg_udccsr;
2467 +       volatile u32                            *reg_udcbcr;
2468 +       volatile u32                            *reg_udcdr;
2469 +       volatile u32                            *reg_udccr;
2470 +#ifdef USE_DMA
2471 +       volatile u32                            *reg_drcmr;
2472 +#define        drcmr(n)  .reg_drcmr = & DRCMR ## n ,
2473 +#else
2474 +#define        drcmr(n)
2475 +#endif
2476 +
2477 +#ifdef CONFIG_PM
2478 +       unsigned                                udccsr_value;
2479 +       unsigned                                udccr_value;
2480 +#endif
2481 +};
2482 +
2483 +struct pxa27x_request {
2484 +       struct usb_request                      req;
2485 +       struct list_head                        queue;
2486 +};
2487 +
2488 +enum ep0_state {
2489 +       EP0_IDLE,
2490 +       EP0_IN_DATA_PHASE,
2491 +       EP0_OUT_DATA_PHASE,
2492 +//     EP0_END_XFER,
2493 +       EP0_STALL,
2494 +       EP0_NO_ACTION
2495 +};
2496 +
2497 +#define EP0_FIFO_SIZE  ((unsigned)16)
2498 +#define BULK_FIFO_SIZE ((unsigned)64)
2499 +#define ISO_FIFO_SIZE  ((unsigned)256)
2500 +#define INT_FIFO_SIZE  ((unsigned)8)
2501 +
2502 +struct udc_stats {
2503 +       struct ep0stats {
2504 +               unsigned long           ops;
2505 +               unsigned long           bytes;
2506 +       } read, write;
2507 +       unsigned long                   irqs;
2508 +};
2509 +
2510 +#ifdef CONFIG_USB_PXA27X_SMALL
2511 +/* when memory's tight, SMALL config saves code+data.  */
2512 +//#undef       USE_DMA
2513 +//#define      UDC_EP_NUM      3
2514 +#endif
2515 +
2516 +#ifndef        UDC_EP_NUM
2517 +#define        UDC_EP_NUM      24
2518 +#endif
2519 +
2520 +struct pxa27x_udc {
2521 +       struct usb_gadget                       gadget;
2522 +       struct usb_gadget_driver                *driver;
2523 +
2524 +       enum ep0_state                          ep0state;
2525 +       struct udc_stats                        stats;
2526 +       unsigned                                got_irq : 1,
2527 +                                               got_disc : 1,
2528 +                                               has_cfr : 1,
2529 +                                               req_pending : 1,
2530 +                                               req_std : 1,
2531 +                                               req_config : 1;
2532 +
2533 +#define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200))
2534 +       struct timer_list                       timer;
2535 +
2536 +       struct device                           *dev;
2537 +       struct pxa2xx_udc_mach_info             *mach;
2538 +       u64                                     dma_mask;
2539 +       struct pxa27x_ep                        ep [UDC_EP_NUM];
2540 +
2541 +       unsigned                                configuration,
2542 +                                               interface,
2543 +                                               alternate;
2544 +#ifdef CONFIG_PM
2545 +       unsigned                                udccsr0;
2546 +#endif
2547 +};
2548 +
2549 +/*-------------------------------------------------------------------------*/
2550 +#if 0
2551 +#ifdef DEBUG
2552 +#define HEX_DISPLAY(n) do { \
2553 +       if (machine_is_mainstone())\
2554 +                { MST_LEDDAT1 = (n); } \
2555 +       } while(0)
2556 +
2557 +#define HEX_DISPLAY1(n)        HEX_DISPLAY(n)
2558 +
2559 +#define HEX_DISPLAY2(n)        do { \
2560 +       if (machine_is_mainstone()) \
2561 +               { MST_LEDDAT2 = (n); } \
2562 +       } while(0)
2563 +
2564 +#endif /* DEBUG */
2565 +#endif
2566 +/*-------------------------------------------------------------------------*/
2567 +
2568 +/* LEDs are only for debug */
2569 +#ifndef HEX_DISPLAY
2570 +#define HEX_DISPLAY(n)         do {} while(0)
2571 +#endif
2572 +
2573 +#ifndef LED_CONNECTED_ON
2574 +#define LED_CONNECTED_ON       do {} while(0)
2575 +#define LED_CONNECTED_OFF      do {} while(0)
2576 +#endif
2577 +#ifndef LED_EP0_ON
2578 +#define LED_EP0_ON             do {} while (0)
2579 +#define LED_EP0_OFF            do {} while (0)
2580 +#endif
2581 +
2582 +static struct pxa27x_udc *the_controller;
2583 +
2584 +#if 0
2585 +/*-------------------------------------------------------------------------*/
2586 +
2587 +
2588 +/* one GPIO should be used to detect host disconnect */
2589 +static inline int is_usb_connected(void)
2590 +{
2591 +       if (!the_controller->mach->udc_is_connected)
2592 +               return 1;
2593 +       return the_controller->mach->udc_is_connected();
2594 +}
2595 +
2596 +/* one GPIO should force the host to see this device (or not) */
2597 +static inline void make_usb_disappear(void)
2598 +{
2599 +       if (!the_controller->mach->udc_command)
2600 +               return;
2601 +       the_controller->mach->udc_command(PXA27X_UDC_CMD_DISCONNECT);
2602 +}
2603 +
2604 +static inline void let_usb_appear(void)
2605 +{
2606 +       if (!the_controller->mach->udc_command)
2607 +               return;
2608 +       the_controller->mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
2609 +}
2610 +#endif
2611 +
2612 +/*-------------------------------------------------------------------------*/
2613 +
2614 +/*
2615 + * Debugging support vanishes in non-debug builds.  DBG_NORMAL should be
2616 + * mostly silent during normal use/testing, with no timing side-effects.
2617 + */
2618 +#define DBG_NORMAL     1       /* error paths, device state transitions */
2619 +#define DBG_VERBOSE    2       /* add some success path trace info */
2620 +#define DBG_NOISY      3       /* ... even more: request level */
2621 +#define DBG_VERY_NOISY 4       /* ... even more: packet level */
2622 +
2623 +#ifdef DEBUG
2624 +
2625 +static const char *state_name[] = {
2626 +       "EP0_IDLE",
2627 +       "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
2628 +       "EP0_END_XFER", "EP0_STALL"
2629 +};
2630 +
2631 +#define DMSG(stuff...) printk(KERN_ERR "udc: " stuff)
2632 +
2633 +#ifdef VERBOSE
2634 +#    define UDC_DEBUG DBG_VERBOSE
2635 +#else
2636 +#    define UDC_DEBUG DBG_NORMAL
2637 +#endif
2638 +
2639 +static void __attribute__ ((__unused__))
2640 +dump_udccr(const char *label)
2641 +{
2642 +       u32     udccr = UDCCR;
2643 +       DMSG("%s 0x%08x =%s%s%s%s%s%s%s%s%s%s, con=%d,inter=%d,altinter=%d\n",
2644 +               label, udccr,
2645 +               (udccr & UDCCR_OEN) ? " oen":"",
2646 +               (udccr & UDCCR_AALTHNP) ? " aalthnp":"",
2647 +               (udccr & UDCCR_AHNP) ? " rem" : "",
2648 +               (udccr & UDCCR_BHNP) ? " rstir" : "",
2649 +               (udccr & UDCCR_DWRE) ? " dwre" : "",
2650 +               (udccr & UDCCR_SMAC) ? " smac" : "",
2651 +               (udccr & UDCCR_EMCE) ? " emce" : "",
2652 +               (udccr & UDCCR_UDR) ? " udr" : "",
2653 +               (udccr & UDCCR_UDA) ? " uda" : "",
2654 +               (udccr & UDCCR_UDE) ? " ude" : "",
2655 +               (udccr & UDCCR_ACN) >> UDCCR_ACN_S,
2656 +               (udccr & UDCCR_AIN) >> UDCCR_AIN_S,
2657 +               (udccr & UDCCR_AAISN)>> UDCCR_AAISN_S );
2658 +}
2659 +
2660 +static void __attribute__ ((__unused__))
2661 +dump_udccsr0(const char *label)
2662 +{
2663 +       u32             udccsr0 = UDCCSR0;
2664 +
2665 +       DMSG("%s %s 0x%08x =%s%s%s%s%s%s%s\n",
2666 +               label, state_name[the_controller->ep0state], udccsr0,
2667 +               (udccsr0 & UDCCSR0_SA) ? " sa" : "",
2668 +               (udccsr0 & UDCCSR0_RNE) ? " rne" : "",
2669 +               (udccsr0 & UDCCSR0_FST) ? " fst" : "",
2670 +               (udccsr0 & UDCCSR0_SST) ? " sst" : "",
2671 +               (udccsr0 & UDCCSR0_DME) ? " dme" : "",
2672 +               (udccsr0 & UDCCSR0_IPR) ? " ipr" : "",
2673 +               (udccsr0 & UDCCSR0_OPC) ? " opr" : "");
2674 +}
2675 +
2676 +static void __attribute__ ((__unused__))
2677 +dump_state(struct pxa27x_udc *dev)
2678 +{
2679 +       unsigned        i;
2680 +
2681 +       DMSG("%s, udcicr %02X.%02X, udcsir %02X.%02x, udcfnr %02X\n",
2682 +               state_name[dev->ep0state],
2683 +               UDCICR1, UDCICR0, UDCISR1, UDCISR0, UDCFNR);
2684 +       dump_udccr("udccr");
2685 +
2686 +       if (!dev->driver) {
2687 +               DMSG("no gadget driver bound\n");
2688 +               return;
2689 +       } else
2690 +               DMSG("ep0 driver '%s'\n", dev->driver->driver.name);
2691 +
2692 +
2693 +       dump_udccsr0 ("udccsr0");
2694 +       DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n",
2695 +               dev->stats.write.bytes, dev->stats.write.ops,
2696 +               dev->stats.read.bytes, dev->stats.read.ops);
2697 +
2698 +       for (i = 1; i < UDC_EP_NUM; i++) {
2699 +               if (dev->ep [i].desc == 0)
2700 +                       continue;
2701 +               DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccsr);
2702 +       }
2703 +}
2704 +
2705 +#if 0
2706 +static void dump_regs(u8 ep)
2707 +{
2708 +       DMSG("EP:%d UDCCSR:0x%08x UDCBCR:0x%08x\n UDCCR:0x%08x\n",
2709 +               ep,UDCCSN(ep), UDCBCN(ep), UDCCN(ep));
2710 +}
2711 +static void dump_req (struct pxa27x_request *req)
2712 +{
2713 +       struct usb_request *r = &req->req;
2714 +
2715 +       DMSG("%s: buf:0x%08x length:%d dma:0x%08x actual:%d\n",
2716 +                       __FUNCTION__, (unsigned)r->buf, r->length,
2717 +                       r->dma, r->actual);
2718 +}
2719 +#endif
2720 +
2721 +#else
2722 +
2723 +#define DMSG(stuff...)         do{}while(0)
2724 +
2725 +#define        dump_udccr(x)   do{}while(0)
2726 +#define        dump_udccsr0(x) do{}while(0)
2727 +#define        dump_state(x)   do{}while(0)
2728 +
2729 +#define UDC_DEBUG ((unsigned)0)
2730 +
2731 +#endif
2732 +
2733 +#define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0)
2734 +
2735 +#define WARN(stuff...) printk(KERN_WARNING "udc: " stuff)
2736 +#define INFO(stuff...) printk(KERN_INFO "udc: " stuff)
2737 +
2738 +
2739 +#endif /* __LINUX_USB_GADGET_PXA27X_H */