remove 2.6.28 support from ppc40x
[openwrt.git] / target / linux / ppc40x / patches-2.6.30 / 005-openrb.patch
1 --- /dev/null
2 +++ b/arch/powerpc/boot/cuboot-openrb.c
3 @@ -0,0 +1,71 @@
4 +/*
5 + * Old U-boot compatibility for OpenRB boards
6 + *
7 + * Author: Gabor Juhos <juhosg@openwrt.org>
8 + *         Imre Kaloz <kaloz@openwrt.org>
9 + *
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License version 2 as published
12 + * by the Free Software Foundation.
13 + */
14 +
15 +#include "ops.h"
16 +#include "io.h"
17 +#include "dcr.h"
18 +#include "stdio.h"
19 +#include "4xx.h"
20 +#include "44x.h"
21 +#include "cuboot.h"
22 +
23 +#define TARGET_4xx
24 +#define TARGET_405EP
25 +#include "ppcboot.h"
26 +
27 +static bd_t bd;
28 +
29 +static void fixup_cf_card(void)
30 +{
31 +#define DCRN_CPC0_PCI_BASE     0xf9
32 +#define CF_CS0_BASE            0xff100000
33 +#define CF_CS1_BASE            0xff200000
34 +
35 +       /* Turn on PerWE instead of PCIsomething */
36 +       mtdcr(DCRN_CPC0_PCI_BASE,
37 +             mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
38 +
39 +       /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
40 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
41 +       mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
42 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
43 +       mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
44 +
45 +       /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
46 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
47 +       mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
48 +       mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
49 +       mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
50 +
51 +#undef DCRN_CPC0_PCI_BASE
52 +#undef CF_CS0_BASE
53 +#undef CF_CS1_BASE
54 +}
55 +
56 +static void openrb_fixups(void)
57 +{
58 +       ibm405ep_fixup_clocks(bd.bi_procfreq / 8);
59 +       ibm4xx_sdram_fixup_memsize();
60 +
61 +       fixup_cf_card();
62 +
63 +       dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
64 +}
65 +
66 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
67 +               unsigned long r6, unsigned long r7)
68 +{
69 +       CUBOOT_INIT();
70 +       platform_ops.fixups = openrb_fixups;
71 +       platform_ops.exit = ibm40x_dbcr_reset;
72 +       fdt_init(_dtb_start);
73 +       serial_console_init();
74 +}
75 --- /dev/null
76 +++ b/arch/powerpc/boot/dts/openrb.dts
77 @@ -0,0 +1,276 @@
78 +/*
79 + * Device Tree Source for OpenRB boards
80 + *
81 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
82 + * Copyright 2009 Imre Kaloz <kaloz@openwrt.org>
83 + *
84 + * Based on walnut.dts
85 + *
86 + * This file is licensed under the terms of the GNU General Public
87 + * License version 2.  This program is licensed "as is" without
88 + * any warranty of any kind, whether express or implied.
89 + */
90 +
91 +/dts-v1/;
92 +
93 +/ {
94 +       #address-cells = <1>;
95 +       #size-cells = <1>;
96 +       model = "openrb";
97 +       compatible = "openrb";
98 +       dcr-parent = <&{/cpus/cpu@0}>;
99 +
100 +       aliases {
101 +               ethernet0 = &EMAC0;
102 +               ethernet1 = &EMAC1;
103 +               serial0 = &UART0;
104 +               serial1 = &UART1;
105 +       };
106 +
107 +       cpus {
108 +               #address-cells = <1>;
109 +               #size-cells = <0>;
110 +
111 +               cpu@0 {
112 +                       device_type = "cpu";
113 +                       model = "PowerPC,405EP";
114 +                       reg = <0x00000000>;
115 +                       clock-frequency = <0>; /* Filled in by zImage */
116 +                       timebase-frequency = <0>; /* Filled in by zImage */
117 +                       i-cache-line-size = <0x20>;
118 +                       d-cache-line-size = <0x20>;
119 +                       i-cache-size = <0x4000>;
120 +                       d-cache-size = <0x4000>;
121 +                       dcr-controller;
122 +                       dcr-access-method = "native";
123 +               };
124 +       };
125 +
126 +       memory {
127 +               device_type = "memory";
128 +               reg = <0x00000000 0x00000000>; /* Filled in by zImage */
129 +       };
130 +
131 +       UIC0: interrupt-controller {
132 +               compatible = "ibm,uic";
133 +               interrupt-controller;
134 +               cell-index = <0>;
135 +               dcr-reg = <0x0c0 0x009>;
136 +               #address-cells = <0>;
137 +               #size-cells = <0>;
138 +               #interrupt-cells = <2>;
139 +       };
140 +
141 +       plb {
142 +               compatible = "ibm,plb3";
143 +               #address-cells = <1>;
144 +               #size-cells = <1>;
145 +               ranges;
146 +               clock-frequency = <0>; /* Filled in by zImage */
147 +
148 +               SDRAM0: memory-controller {
149 +                       compatible = "ibm,sdram-405ep";
150 +                       dcr-reg = <0x010 0x002>;
151 +               };
152 +
153 +               MAL: mcmal {
154 +                       compatible = "ibm,mcmal-405ep", "ibm,mcmal";
155 +                       dcr-reg = <0x180 0x062>;
156 +                       num-tx-chans = <4>;
157 +                       num-rx-chans = <2>;
158 +                       interrupt-parent = <&UIC0>;
159 +                       interrupts = <
160 +                               0xb 0x4 /* TXEOB */
161 +                               0xc 0x4 /* RXEOB */
162 +                               0xa 0x4 /* SERR */
163 +                               0xd 0x4 /* TXDE */
164 +                               0xe 0x4 /* RXDE */>;
165 +               };
166 +
167 +               POB0: opb {
168 +                       compatible = "ibm,opb-405ep", "ibm,opb";
169 +                       #address-cells = <1>;
170 +                       #size-cells = <1>;
171 +                       ranges = <0xef600000 0xef600000 0x00a00000>;
172 +                       dcr-reg = <0x0a0 0x005>;
173 +                       clock-frequency = <0>; /* Filled in by zImage */
174 +
175 +                       UART0: serial@ef600300 {
176 +                               device_type = "serial";
177 +                               compatible = "ns16550";
178 +                               reg = <0xef600300 0x00000008>;
179 +                               virtual-reg = <0xef600300>;
180 +                               clock-frequency = <0>; /* Filled in by zImage */
181 +                               current-speed = <115200>;
182 +                               interrupt-parent = <&UIC0>;
183 +                               interrupts = <0x0 0x4>;
184 +                       };
185 +
186 +                       UART1: serial@ef600400 {
187 +                               device_type = "serial";
188 +                               compatible = "ns16550";
189 +                               reg = <0xef600400 0x00000008>;
190 +                               virtual-reg = <0xef600400>;
191 +                               clock-frequency = <0>; /* Filled in by zImage */
192 +                               current-speed = <115200>;
193 +                               interrupt-parent = <&UIC0>;
194 +                               interrupts = <0x1 0x4>;
195 +                       };
196 +
197 +                       IIC: i2c@ef600500 {
198 +                               compatible = "ibm,iic-405ep", "ibm,iic";
199 +                               #address-cells = <1>;
200 +                               #size-cells = <0>;
201 +                               reg = <0xef600500 0x00000011>;
202 +                               interrupt-parent = <&UIC0>;
203 +                               interrupts = <0x2 0x4>;
204 +
205 +                               eeprom@50 {
206 +                                       compatible = "at24,24c16";
207 +                                       reg = <0x50>;
208 +                               };
209 +                       };
210 +
211 +                       GPIO0: gpio-controller@ef600700 {
212 +                               compatible = "ibm,ppc4xx-gpio";
213 +                               reg = <0xef600700 0x00000020>;
214 +                               #gpio-cells = <2>;
215 +                               gpio-controller;
216 +                       };
217 +
218 +                       EMAC0: ethernet@ef600800 {
219 +                               linux,network-index = <0x0>;
220 +                               device_type = "network";
221 +                               compatible = "ibm,emac-405ep", "ibm,emac";
222 +                               interrupt-parent = <&UIC0>;
223 +                               interrupts = <
224 +                                       0xf 0x4 /* Ethernet */
225 +                                       0x9 0x4 /* Ethernet Wake Up */>;
226 +                               local-mac-address = [000000000000]; /* Filled in by zImage */
227 +                               reg = <0xef600800 0x00000070>;
228 +                               mal-device = <&MAL>;
229 +                               mal-tx-channel = <0>;
230 +                               mal-rx-channel = <0>;
231 +                               cell-index = <0>;
232 +                               max-frame-size = <0x5dc>;
233 +                               rx-fifo-size = <0x1000>;
234 +                               tx-fifo-size = <0x800>;
235 +                               phy-mode = "mii";
236 +                               phy-map = <0x00000000>;
237 +                       };
238 +
239 +                       EMAC1: ethernet@ef600900 {
240 +                               linux,network-index = <0x1>;
241 +                               device_type = "network";
242 +                               compatible = "ibm,emac-405ep", "ibm,emac";
243 +                               interrupt-parent = <&UIC0>;
244 +                               interrupts = <
245 +                                       0x11 0x4 /* Ethernet */
246 +                                       0x09 0x4 /* Ethernet Wake Up */>;
247 +                               local-mac-address = [000000000000]; /* Filled in by zImage */
248 +                               reg = <0xef600900 0x00000070>;
249 +                               mal-device = <&MAL>;
250 +                               mal-tx-channel = <2>;
251 +                               mal-rx-channel = <1>;
252 +                               cell-index = <1>;
253 +                               max-frame-size = <0x5dc>;
254 +                               rx-fifo-size = <0x1000>;
255 +                               tx-fifo-size = <0x800>;
256 +                               mdio-device = <&EMAC0>;
257 +                               phy-mode = "mii";
258 +                               phy-map = <0x00000001>;
259 +                       };
260 +
261 +                       leds {
262 +                               compatible = "gpio-leds";
263 +                               user {
264 +                                       label = "openrb:green:user";
265 +                                       gpios = <&GPIO0 2 1>;
266 +                               };
267 +                       };
268 +               };
269 +
270 +               EBC0: ebc {
271 +                       compatible = "ibm,ebc-405ep", "ibm,ebc";
272 +                       dcr-reg = <0x012 0x002>;
273 +                       #address-cells = <2>;
274 +                       #size-cells = <1>;
275 +                       /* The ranges property is supplied by the bootwrapper
276 +                        * and is based on the firmware's configuration of the
277 +                        * EBC bridge
278 +                        */
279 +                       clock-frequency = <0>; /* Filled in by zImage */
280 +
281 +                       cf_card@ff100000 {
282 +                               compatible = "magicbox-cf", "pata-magicbox-cf";
283 +                               reg = <0x00000000 0xff100000 0x00001000
284 +                                      0x00000000 0xff200000 0x00001000>;
285 +                               interrupt-parent = <&UIC0>;
286 +                               interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
287 +                       };
288 +
289 +                       nor_flash@ff800000 {
290 +                               compatible = "cfi-flash";
291 +                               bank-width = <2>;
292 +                               reg = <0x00000000 0xff800000 0x00800000>;
293 +                               #address-cells = <1>;
294 +                               #size-cells = <1>;
295 +                               partition@0 {
296 +                                       label = "linux";
297 +                                       reg = <0x0 0x120000>;
298 +                               };
299 +                               partition@120000 {
300 +                                       label = "rootfs";
301 +                                       reg = <0x120000 0x6a0000>;
302 +                               };
303 +                               partition@7c0000 {
304 +                                       label = "u-boot";
305 +                                       reg = <0x7c0000 0x30000>;
306 +                                       read-only;
307 +                               };
308 +                       };
309 +               };
310 +
311 +               PCI0: pci@ec000000 {
312 +                       device_type = "pci";
313 +                       #interrupt-cells = <1>;
314 +                       #size-cells = <2>;
315 +                       #address-cells = <3>;
316 +                       compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
317 +                       primary;
318 +                       reg = <0xeec00000 0x00000008    /* Config space access */
319 +                              0xeed80000 0x00000004    /* IACK */
320 +                              0xeed80000 0x00000004    /* Special cycle */
321 +                              0xef480000 0x00000040>;  /* Internal registers */
322 +
323 +                       /* Outbound ranges, one memory and one IO,
324 +                        * later cannot be changed. Chip supports a second
325 +                        * IO range but we don't use it for now
326 +                        */
327 +                       ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
328 +                                 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
329 +
330 +                       /* Inbound 2GB range starting at 0 */
331 +                       dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
332 +
333 +                       interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
334 +                       interrupt-map = <
335 +                               /* IDSEL 1 */
336 +                               0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
337 +
338 +                               /* IDSEL 2 */
339 +                               0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
340 +
341 +                               /* IDSEL 3 */
342 +                               0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
343 +
344 +                               /* IDSEL 4 */
345 +                               0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
346 +                       >;
347 +               };
348 +       };
349 +
350 +       chosen {
351 +               linux,stdout-path = "/plb/opb/serial@ef600300";
352 +       };
353 +};
354 --- a/arch/powerpc/boot/Makefile
355 +++ b/arch/powerpc/boot/Makefile
356 @@ -43,6 +43,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -
357  $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440
358  $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
359  $(obj)/cuboot-magicbox.o: BOOTCFLAGS += -mcpu=405
360 +$(obj)/cuboot-openrb.o: BOOTCFLAGS += -mcpu=405
361  $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
362  $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
363  
364 @@ -76,7 +77,8 @@ src-plat := of.c cuboot-52xx.c cuboot-82
365                 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
366                 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
367                 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
368 -               cuboot-acadia.c cuboot-amigaone.c cuboot-magicbox.c
369 +               cuboot-acadia.c cuboot-amigaone.c cuboot-magicbox.c \
370 +               cuboot-openrb.c
371  src-boot := $(src-wlib) $(src-plat) empty.c
372  
373  src-boot := $(addprefix $(obj)/, $(src-boot))
374 @@ -194,6 +196,7 @@ image-$(CONFIG_EP405)                       += dtbImage.ep40
375  image-$(CONFIG_WALNUT)                 += treeImage.walnut
376  image-$(CONFIG_ACADIA)                 += cuImage.acadia
377  image-$(CONFIG_MAGICBOX)               += cuImage.magicbox
378 +image-$(CONFIG_OPENRB)                 += cuImage.openrb
379  
380  # Board ports in arch/powerpc/platform/44x/Kconfig
381  image-$(CONFIG_EBONY)                  += treeImage.ebony cuImage.ebony
382 --- a/arch/powerpc/platforms/40x/Kconfig
383 +++ b/arch/powerpc/platforms/40x/Kconfig
384 @@ -60,6 +60,16 @@ config MAGICBOX
385         help
386           This option enables support for the Magicbox boards.
387  
388 +config OPENRB
389 +       bool "OpenRB"
390 +       depends on 40x
391 +       default n
392 +       select PPC40x_SIMPLE
393 +       select 405EP
394 +       select PCI
395 +       help
396 +         This option enables support for the OpenRB boards.
397 +
398  config MAKALU
399         bool "Makalu"
400         depends on 40x
401 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
402 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
403 @@ -55,7 +55,8 @@ static char *board[] __initdata = {
404         "amcc,haleakala",
405         "amcc,kilauea",
406         "amcc,makalu",
407 -       "magicbox"
408 +       "magicbox",
409 +       "openrb"
410  };
411  
412  static int __init ppc40x_probe(void)