target/linux/omap35xx/patches-2.6.32/002-OMAP.patch

   1 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
   2 index 1c4119c..e861e32 100644
   3 --- a/arch/arm/Kconfig
   4 +++ b/arch/arm/Kconfig
   5 @@ -1508,6 +1508,10 @@ source "net/Kconfig"
   6
   7  source "drivers/Kconfig"
   8
   9 +if ARCH_OMAP
  10 +source "drivers/cbus/Kconfig"
  11 +endif
  12 +
  13  source "fs/Kconfig"
  14
  15  source "arch/arm/Kconfig.debug"
  16 diff --git a/arch/arm/configs/n8x0_defconfig b/arch/arm/configs/n8x0_defconfig
  17 index 8da75de..264f52b 100644
  18 --- a/arch/arm/configs/n8x0_defconfig
  19 +++ b/arch/arm/configs/n8x0_defconfig
  20 @@ -304,7 +304,7 @@ CONFIG_ALIGNMENT_TRAP=y
  21  CONFIG_ZBOOT_ROM_TEXT=0x10C08000
  22  CONFIG_ZBOOT_ROM_BSS=0x10200000
  23  # CONFIG_ZBOOT_ROM is not set
  24 -CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS0,115200n8"
  25 +CONFIG_CMDLINE="root=1f03 rootfstype=jffs2 console=ttyS2,115200n8"
  26  # CONFIG_XIP_KERNEL is not set
  27  # CONFIG_KEXEC is not set
  28
  29 diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
  30 index a7ead1b..74720e6 100644
  31 --- a/arch/arm/mach-omap1/board-fsample.c
  32 +++ b/arch/arm/mach-omap1/board-fsample.c
  33 @@ -107,7 +107,7 @@ static struct resource smc91x_resources[] = {
  34                 .flags  = IORESOURCE_MEM,
  35         },
  36         [1] = {
  37 -               .start  = INT_730_MPU_EXT_NIRQ,
  38 +               .start  = INT_7XX_MPU_EXT_NIRQ,
  39                 .end    = 0,
  40                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  41         },
  42 @@ -196,8 +196,8 @@ static struct platform_device smc91x_device = {
  43
  44  static struct resource kp_resources[] = {
  45         [0] = {
  46 -               .start  = INT_730_MPUIO_KEYPAD,
  47 -               .end    = INT_730_MPUIO_KEYPAD,
  48 +               .start  = INT_7XX_MPUIO_KEYPAD,
  49 +               .end    = INT_7XX_MPUIO_KEYPAD,
  50                 .flags  = IORESOURCE_IRQ,
  51         },
  52  };
  53 @@ -309,7 +309,7 @@ static void __init omap_fsample_map_io(void)
  54         /*
  55          * Hold GSM Reset until needed
  56          */
  57 -       omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
  58 +       omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
  59
  60         /*
  61          * UARTs -> done automagically by 8250 driver
  62 @@ -320,21 +320,21 @@ static void __init omap_fsample_map_io(void)
  63          */
  64
  65         /* Flash: CS0 timings setup */
  66 -       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
  67 -       omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
  68 +       omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
  69 +       omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
  70
  71         /*
  72          * Ethernet support through the debug board
  73          * CS1 timings setup
  74          */
  75 -       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
  76 -       omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
  77 +       omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
  78 +       omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
  79
  80         /*
  81          * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
  82          * It is used as the Ethernet controller interrupt
  83          */
  84 -       omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
  85 +       omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
  86  }
  87
  88  MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
  89 diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
  90 index 8340669..2f897cf 100644
  91 --- a/arch/arm/mach-omap1/board-perseus2.c
  92 +++ b/arch/arm/mach-omap1/board-perseus2.c
  93 @@ -74,7 +74,7 @@ static struct resource smc91x_resources[] = {
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97 -               .start  = INT_730_MPU_EXT_NIRQ,
  98 +               .start  = INT_7XX_MPU_EXT_NIRQ,
  99                 .end    = 0,
 100                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 101         },
 102 @@ -163,8 +163,8 @@ static struct platform_device smc91x_device = {
 103
 104  static struct resource kp_resources[] = {
 105         [0] = {
 106 -               .start  = INT_730_MPUIO_KEYPAD,
 107 -               .end    = INT_730_MPUIO_KEYPAD,
 108 +               .start  = INT_7XX_MPUIO_KEYPAD,
 109 +               .end    = INT_7XX_MPUIO_KEYPAD,
 110                 .flags  = IORESOURCE_IRQ,
 111         },
 112  };
 113 @@ -270,7 +270,7 @@ static void __init omap_perseus2_map_io(void)
 114         /*
 115          * Hold GSM Reset until needed
 116          */
 117 -       omap_writew(omap_readw(OMAP730_DSP_M_CTL) & ~1, OMAP730_DSP_M_CTL);
 118 +       omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
 119
 120         /*
 121          * UARTs -> done automagically by 8250 driver
 122 @@ -281,21 +281,21 @@ static void __init omap_perseus2_map_io(void)
 123          */
 124
 125         /* Flash: CS0 timings setup */
 126 -       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_0);
 127 -       omap_writel(0x00000088, OMAP730_FLASH_ACFG_0);
 128 +       omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
 129 +       omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
 130
 131         /*
 132          * Ethernet support through the debug board
 133          * CS1 timings setup
 134          */
 135 -       omap_writel(0x0000fff3, OMAP730_FLASH_CFG_1);
 136 -       omap_writel(0x00000000, OMAP730_FLASH_ACFG_1);
 137 +       omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
 138 +       omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
 139
 140         /*
 141          * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
 142          * It is used as the Ethernet controller interrupt
 143          */
 144 -       omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
 145 +       omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
 146  }
 147
 148  MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
 149 diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
 150 index 436eed2..5f77b83 100644
 151 --- a/arch/arm/mach-omap1/clock.c
 152 +++ b/arch/arm/mach-omap1/clock.c
 153 @@ -69,13 +69,13 @@ struct omap_clk {
 154         }
 155
 156  #define CK_310 (1 << 0)
 157 -#define CK_730 (1 << 1)
 158 +#define CK_7XX (1 << 1)
 159  #define CK_1510        (1 << 2)
 160  #define CK_16XX        (1 << 3)
 161
 162  static struct omap_clk omap_clks[] = {
 163         /* non-ULPD clocks */
 164 -       CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310),
 165 +       CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 166         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310),
 167         /* CK_GEN1 clocks */
 168         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 169 @@ -83,7 +83,7 @@ static struct omap_clk omap_clks[] = {
 170         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 171         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 172         CLK(NULL,       "arm_gpio_ck",  &arm_gpio_ck,   CK_1510 | CK_310),
 173 -       CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 174 +       CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 175         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 176         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 177         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 178 @@ -97,7 +97,7 @@ static struct omap_clk omap_clks[] = {
 179         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 180         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 181         /* CK_GEN3 clocks */
 182 -       CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_730),
 183 +       CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 184         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 185         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX),
 186         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 187 @@ -108,7 +108,7 @@ static struct omap_clk omap_clks[] = {
 188         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 189         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 190         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 191 -       CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_730),
 192 +       CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 193         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 194         /* ULPD clocks */
 195         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 196 @@ -398,7 +398,7 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
 197          * Reprogramming the DPLL is tricky, it must be done from SRAM.
 198          * (on 730, bit 13 must always be 1)
 199          */
 200 -       if (cpu_is_omap730())
 201 +       if (cpu_is_omap7xx())
 202                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
 203         else
 204                 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
 205 @@ -783,8 +783,8 @@ int __init omap1_clk_init(void)
 206                 cpu_mask |= CK_16XX;
 207         if (cpu_is_omap1510())
 208                 cpu_mask |= CK_1510;
 209 -       if (cpu_is_omap730())
 210 -               cpu_mask |= CK_730;
 211 +       if (cpu_is_omap7xx())
 212 +               cpu_mask |= CK_7XX;
 213         if (cpu_is_omap310())
 214                 cpu_mask |= CK_310;
 215
 216 @@ -800,7 +800,7 @@ int __init omap1_clk_init(void)
 217                         crystal_type = info->system_clock_type;
 218         }
 219
 220 -#if defined(CONFIG_ARCH_OMAP730)
 221 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 222         ck_ref.rate = 13000000;
 223  #elif defined(CONFIG_ARCH_OMAP16XX)
 224         if (crystal_type == 2)
 225 @@ -847,7 +847,7 @@ int __init omap1_clk_init(void)
 226                 printk(KERN_ERR "System frequencies not set. Check your config.\n");
 227                 /* Guess sane values (60MHz) */
 228                 omap_writew(0x2290, DPLL_CTL);
 229 -               omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
 230 +               omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
 231                 ck_dpll1.rate = 60000000;
 232         }
 233  #endif
 234 @@ -862,7 +862,7 @@ int __init omap1_clk_init(void)
 235
 236  #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
 237         /* Select slicer output as OMAP input clock */
 238 -       omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
 239 +       omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
 240  #endif
 241
 242         /* Amstrad Delta wants BCLK high when inactive */
 243 @@ -873,7 +873,7 @@ int __init omap1_clk_init(void)
 244
 245         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 246         /* (on 730, bit 13 must not be cleared) */
 247 -       if (cpu_is_omap730())
 248 +       if (cpu_is_omap7xx())
 249                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 250         else
 251                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 252 diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
 253 index 7030f92..a27df2c 100644
 254 --- a/arch/arm/mach-omap1/io.c
 255 +++ b/arch/arm/mach-omap1/io.c
 256 @@ -36,33 +36,17 @@ static struct map_desc omap_io_desc[] __initdata = {
 257         }
 258  };
 259
 260 -#ifdef CONFIG_ARCH_OMAP730
 261 -static struct map_desc omap730_io_desc[] __initdata = {
 262 +#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
 263 +static struct map_desc omap7xx_io_desc[] __initdata = {
 264         {
 265 -               .virtual        = OMAP730_DSP_BASE,
 266 -               .pfn            = __phys_to_pfn(OMAP730_DSP_START),
 267 -               .length         = OMAP730_DSP_SIZE,
 268 +               .virtual        = OMAP7XX_DSP_BASE,
 269 +               .pfn            = __phys_to_pfn(OMAP7XX_DSP_START),
 270 +               .length         = OMAP7XX_DSP_SIZE,
 271                 .type           = MT_DEVICE
 272         }, {
 273 -               .virtual        = OMAP730_DSPREG_BASE,
 274 -               .pfn            = __phys_to_pfn(OMAP730_DSPREG_START),
 275 -               .length         = OMAP730_DSPREG_SIZE,
 276 -               .type           = MT_DEVICE
 277 -       }
 278 -};
 279 -#endif
 280 -
 281 -#ifdef CONFIG_ARCH_OMAP850
 282 -static struct map_desc omap850_io_desc[] __initdata = {
 283 -       {
 284 -               .virtual        = OMAP850_DSP_BASE,
 285 -               .pfn            = __phys_to_pfn(OMAP850_DSP_START),
 286 -               .length         = OMAP850_DSP_SIZE,
 287 -               .type           = MT_DEVICE
 288 -       }, {
 289 -               .virtual        = OMAP850_DSPREG_BASE,
 290 -               .pfn            = __phys_to_pfn(OMAP850_DSPREG_START),
 291 -               .length         = OMAP850_DSPREG_SIZE,
 292 +               .virtual        = OMAP7XX_DSPREG_BASE,
 293 +               .pfn            = __phys_to_pfn(OMAP7XX_DSPREG_START),
 294 +               .length         = OMAP7XX_DSPREG_SIZE,
 295                 .type           = MT_DEVICE
 296         }
 297  };
 298 @@ -120,18 +104,11 @@ void __init omap1_map_common_io(void)
 299          */
 300         omap_check_revision();
 301
 302 -#ifdef CONFIG_ARCH_OMAP730
 303 -       if (cpu_is_omap730()) {
 304 -               iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
 305 -       }
 306 -#endif
 307 -
 308 -#ifdef CONFIG_ARCH_OMAP850
 309 -       if (cpu_is_omap850()) {
 310 -               iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc));
 311 +#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
 312 +       if (cpu_is_omap7xx()) {
 313 +               iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
 314         }
 315  #endif
 316 -
 317  #ifdef CONFIG_ARCH_OMAP15XX
 318         if (cpu_is_omap15xx()) {
 319                 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
 320 diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
 321 index de03c84..8f98b58 100644
 322 --- a/arch/arm/mach-omap1/irq.c
 323 +++ b/arch/arm/mach-omap1/irq.c
 324 @@ -137,16 +137,8 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
 325         irq_bank_writel(val, bank, offset);
 326  }
 327
 328 -#ifdef CONFIG_ARCH_OMAP730
 329 -static struct omap_irq_bank omap730_irq_banks[] = {
 330 -       { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
 331 -       { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
 332 -       { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
 333 -};
 334 -#endif
 335 -
 336 -#ifdef CONFIG_ARCH_OMAP850
 337 -static struct omap_irq_bank omap850_irq_banks[] = {
 338 +#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
 339 +static struct omap_irq_bank omap7xx_irq_banks[] = {
 340         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
 341         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
 342         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
 343 @@ -186,16 +178,10 @@ void __init omap_init_irq(void)
 344  {
 345         int i, j;
 346
 347 -#ifdef CONFIG_ARCH_OMAP730
 348 -       if (cpu_is_omap730()) {
 349 -               irq_banks = omap730_irq_banks;
 350 -               irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
 351 -       }
 352 -#endif
 353 -#ifdef CONFIG_ARCH_OMAP850
 354 -       if (cpu_is_omap850()) {
 355 -               irq_banks = omap850_irq_banks;
 356 -               irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
 357 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 358 +       if (cpu_is_omap7xx()) {
 359 +               irq_banks = omap7xx_irq_banks;
 360 +               irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
 361         }
 362  #endif
 363  #ifdef CONFIG_ARCH_OMAP15XX
 364 @@ -247,10 +233,8 @@ void __init omap_init_irq(void)
 365
 366         /* Unmask level 2 handler */
 367
 368 -       if (cpu_is_omap730())
 369 -               omap_unmask_irq(INT_730_IH2_IRQ);
 370 -       else if (cpu_is_omap850())
 371 -               omap_unmask_irq(INT_850_IH2_IRQ);
 372 +       if (cpu_is_omap7xx())
 373 +               omap_unmask_irq(INT_7XX_IH2_IRQ);
 374         else if (cpu_is_omap15xx())
 375                 omap_unmask_irq(INT_1510_IH2_IRQ);
 376         else if (cpu_is_omap16xx())
 377 diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
 378 index 505d98c..3a51cb2 100644
 379 --- a/arch/arm/mach-omap1/mcbsp.c
 380 +++ b/arch/arm/mach-omap1/mcbsp.c
 381 @@ -79,29 +79,29 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
 382         .free           = omap1_mcbsp_free,
 383  };
 384
 385 -#ifdef CONFIG_ARCH_OMAP730
 386 -static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
 387 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 388 +static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
 389         {
 390 -               .phys_base      = OMAP730_MCBSP1_BASE,
 391 +               .phys_base      = OMAP7XX_MCBSP1_BASE,
 392                 .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
 393                 .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
 394 -               .rx_irq         = INT_730_McBSP1RX,
 395 -               .tx_irq         = INT_730_McBSP1TX,
 396 +               .rx_irq         = INT_7XX_McBSP1RX,
 397 +               .tx_irq         = INT_7XX_McBSP1TX,
 398                 .ops            = &omap1_mcbsp_ops,
 399         },
 400         {
 401 -               .phys_base      = OMAP730_MCBSP2_BASE,
 402 +               .phys_base      = OMAP7XX_MCBSP2_BASE,
 403                 .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
 404                 .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
 405 -               .rx_irq         = INT_730_McBSP2RX,
 406 -               .tx_irq         = INT_730_McBSP2TX,
 407 +               .rx_irq         = INT_7XX_McBSP2RX,
 408 +               .tx_irq         = INT_7XX_McBSP2TX,
 409                 .ops            = &omap1_mcbsp_ops,
 410         },
 411  };
 412 -#define OMAP730_MCBSP_PDATA_SZ         ARRAY_SIZE(omap730_mcbsp_pdata)
 413 +#define OMAP7XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap7xx_mcbsp_pdata)
 414  #else
 415 -#define omap730_mcbsp_pdata            NULL
 416 -#define OMAP730_MCBSP_PDATA_SZ         0
 417 +#define omap7xx_mcbsp_pdata            NULL
 418 +#define OMAP7XX_MCBSP_PDATA_SZ         0
 419  #endif
 420
 421  #ifdef CONFIG_ARCH_OMAP15XX
 422 @@ -172,8 +172,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
 423
 424  int __init omap1_mcbsp_init(void)
 425  {
 426 -       if (cpu_is_omap730())
 427 -               omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
 428 +       if (cpu_is_omap7xx())
 429 +               omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
 430         if (cpu_is_omap15xx())
 431                 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
 432         if (cpu_is_omap16xx())
 433 @@ -184,9 +184,9 @@ int __init omap1_mcbsp_init(void)
 434         if (!mcbsp_ptr)
 435                 return -ENOMEM;
 436
 437 -       if (cpu_is_omap730())
 438 -               omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
 439 -                                               OMAP730_MCBSP_PDATA_SZ);
 440 +       if (cpu_is_omap7xx())
 441 +               omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
 442 +                                               OMAP7XX_MCBSP_PDATA_SZ);
 443
 444         if (cpu_is_omap15xx())
 445                 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
 446 diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
 447 index 721e0d9..d59899d 100644
 448 --- a/arch/arm/mach-omap1/mux.c
 449 +++ b/arch/arm/mach-omap1/mux.c
 450 @@ -35,47 +35,28 @@
 451
 452  static struct omap_mux_cfg arch_mux_cfg;
 453
 454 -#ifdef CONFIG_ARCH_OMAP730
 455 -static struct pin_config __initdata_or_module omap730_pins[] = {
 456 -MUX_CFG_730("E2_730_KBR0",        12,   21,    0,   20,   1, 0)
 457 -MUX_CFG_730("J7_730_KBR1",        12,   25,    0,   24,   1, 0)
 458 -MUX_CFG_730("E1_730_KBR2",        12,   29,    0,   28,   1, 0)
 459 -MUX_CFG_730("F3_730_KBR3",        13,    1,    0,    0,   1, 0)
 460 -MUX_CFG_730("D2_730_KBR4",        13,    5,    0,    4,   1, 0)
 461 -MUX_CFG_730("C2_730_KBC0",        13,    9,    0,    8,   1, 0)
 462 -MUX_CFG_730("D3_730_KBC1",        13,   13,    0,   12,   1, 0)
 463 -MUX_CFG_730("E4_730_KBC2",        13,   17,    0,   16,   1, 0)
 464 -MUX_CFG_730("F4_730_KBC3",        13,   21,    0,   20,   1, 0)
 465 -MUX_CFG_730("E3_730_KBC4",        13,   25,    0,   24,   1, 0)
 466 -
 467 -MUX_CFG_730("AA17_730_USB_DM",     2,   21,    0,   20,   0, 0)
 468 -MUX_CFG_730("W16_730_USB_PU_EN",   2,   25,    0,   24,   0, 0)
 469 -MUX_CFG_730("W17_730_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 470 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 471 +static struct pin_config __initdata_or_module omap7xx_pins[] = {
 472 +MUX_CFG_7XX("E2_7XX_KBR0",        12,   21,    0,   20,   1, 0)
 473 +MUX_CFG_7XX("J7_7XX_KBR1",        12,   25,    0,   24,   1, 0)
 474 +MUX_CFG_7XX("E1_7XX_KBR2",        12,   29,    0,   28,   1, 0)
 475 +MUX_CFG_7XX("F3_7XX_KBR3",        13,    1,    0,    0,   1, 0)
 476 +MUX_CFG_7XX("D2_7XX_KBR4",        13,    5,    0,    4,   1, 0)
 477 +MUX_CFG_7XX("C2_7XX_KBC0",        13,    9,    0,    8,   1, 0)
 478 +MUX_CFG_7XX("D3_7XX_KBC1",        13,   13,    0,   12,   1, 0)
 479 +MUX_CFG_7XX("E4_7XX_KBC2",        13,   17,    0,   16,   1, 0)
 480 +MUX_CFG_7XX("F4_7XX_KBC3",        13,   21,    0,   20,   1, 0)
 481 +MUX_CFG_7XX("E3_7XX_KBC4",        13,   25,    0,   24,   1, 0)
 482 +
 483 +MUX_CFG_7XX("AA17_7XX_USB_DM",     2,   21,    0,   20,   0, 0)
 484 +MUX_CFG_7XX("W16_7XX_USB_PU_EN",   2,   25,    0,   24,   0, 0)
 485 +MUX_CFG_7XX("W17_7XX_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 486  };
 487 -#define OMAP730_PINS_SZ                ARRAY_SIZE(omap730_pins)
 488 +#define OMAP7XX_PINS_SZ                ARRAY_SIZE(omap7xx_pins)
 489  #else
 490 -#define omap730_pins           NULL
 491 -#define OMAP730_PINS_SZ                0
 492 -#endif /* CONFIG_ARCH_OMAP730 */
 493 -
 494 -#ifdef CONFIG_ARCH_OMAP850
 495 -struct pin_config __initdata_or_module omap850_pins[] = {
 496 -MUX_CFG_850("E2_850_KBR0",        12,   21,    0,   20,   1, 0)
 497 -MUX_CFG_850("J7_850_KBR1",        12,   25,    0,   24,   1, 0)
 498 -MUX_CFG_850("E1_850_KBR2",        12,   29,    0,   28,   1, 0)
 499 -MUX_CFG_850("F3_850_KBR3",        13,    1,    0,    0,   1, 0)
 500 -MUX_CFG_850("D2_850_KBR4",        13,    5,    0,    4,   1, 0)
 501 -MUX_CFG_850("C2_850_KBC0",        13,    9,    0,    8,   1, 0)
 502 -MUX_CFG_850("D3_850_KBC1",        13,   13,    0,   12,   1, 0)
 503 -MUX_CFG_850("E4_850_KBC2",        13,   17,    0,   16,   1, 0)
 504 -MUX_CFG_850("F4_850_KBC3",        13,   21,    0,   20,   1, 0)
 505 -MUX_CFG_850("E3_850_KBC4",        13,   25,    0,   24,   1, 0)
 506 -
 507 -MUX_CFG_850("AA17_850_USB_DM",     2,   21,    0,   20,   0, 0)
 508 -MUX_CFG_850("W16_850_USB_PU_EN",   2,   25,    0,   24,   0, 0)
 509 -MUX_CFG_850("W17_850_USB_VBUSI",   2,   29,    0,   28,   0, 0)
 510 -};
 511 -#endif
 512 +#define omap7xx_pins           NULL
 513 +#define OMAP7XX_PINS_SZ                0
 514 +#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
 515
 516  #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
 517  static struct pin_config __initdata_or_module omap1xxx_pins[] = {
 518 @@ -438,11 +419,6 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 519                         printk("      %s (0x%08x) = 0x%08x -> 0x%08x\n",
 520                                cfg->pull_name, cfg->pull_reg, pull_orig, pull);
 521         }
 522 -
 523 -#ifdef CONFIG_ARCH_OMAP850
 524 -       omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins));
 525 -#endif
 526 -
 527  #endif
 528
 529  #ifdef CONFIG_OMAP_MUX_ERRORS
 530 @@ -454,9 +430,9 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 531
 532  int __init omap1_mux_init(void)
 533  {
 534 -       if (cpu_is_omap730()) {
 535 -               arch_mux_cfg.pins       = omap730_pins;
 536 -               arch_mux_cfg.size       = OMAP730_PINS_SZ;
 537 +       if (cpu_is_omap7xx()) {
 538 +               arch_mux_cfg.pins       = omap7xx_pins;
 539 +               arch_mux_cfg.size       = OMAP7XX_PINS_SZ;
 540                 arch_mux_cfg.cfg_reg    = omap1_cfg_reg;
 541         }
 542
 543 diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
 544 index 5218943..10f4e4a 100644
 545 --- a/arch/arm/mach-omap1/pm.c
 546 +++ b/arch/arm/mach-omap1/pm.c
 547 @@ -62,7 +62,7 @@
 548  static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
 549  static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
 550  static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
 551 -static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
 552 +static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
 553  static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
 554  static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
 555
 556 @@ -183,9 +183,9 @@ static void omap_pm_wakeup_setup(void)
 557          * drivers must still separately call omap_set_gpio_wakeup() to
 558          * wake up to a GPIO interrupt.
 559          */
 560 -       if (cpu_is_omap730())
 561 -               level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
 562 -                       OMAP_IRQ_BIT(INT_730_IH2_IRQ);
 563 +       if (cpu_is_omap7xx())
 564 +               level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
 565 +                       OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
 566         else if (cpu_is_omap15xx())
 567                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 568                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 569 @@ -195,10 +195,10 @@ static void omap_pm_wakeup_setup(void)
 570
 571         omap_writel(~level1_wake, OMAP_IH1_MIR);
 572
 573 -       if (cpu_is_omap730()) {
 574 +       if (cpu_is_omap7xx()) {
 575                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 576 -               omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
 577 -                               OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
 578 +               omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
 579 +                               OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
 580                                 OMAP_IH2_1_MIR);
 581         } else if (cpu_is_omap15xx()) {
 582                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 583 @@ -253,15 +253,15 @@ void omap1_pm_suspend(void)
 584          * Save interrupt, MPUI, ARM and UPLD control registers.
 585          */
 586
 587 -       if (cpu_is_omap730()) {
 588 -               MPUI730_SAVE(OMAP_IH1_MIR);
 589 -               MPUI730_SAVE(OMAP_IH2_0_MIR);
 590 -               MPUI730_SAVE(OMAP_IH2_1_MIR);
 591 -               MPUI730_SAVE(MPUI_CTRL);
 592 -               MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 593 -               MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 594 -               MPUI730_SAVE(EMIFS_CONFIG);
 595 -               MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 596 +       if (cpu_is_omap7xx()) {
 597 +               MPUI7XX_SAVE(OMAP_IH1_MIR);
 598 +               MPUI7XX_SAVE(OMAP_IH2_0_MIR);
 599 +               MPUI7XX_SAVE(OMAP_IH2_1_MIR);
 600 +               MPUI7XX_SAVE(MPUI_CTRL);
 601 +               MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 602 +               MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 603 +               MPUI7XX_SAVE(EMIFS_CONFIG);
 604 +               MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 605
 606         } else if (cpu_is_omap15xx()) {
 607                 MPUI1510_SAVE(OMAP_IH1_MIR);
 608 @@ -306,7 +306,7 @@ void omap1_pm_suspend(void)
 609         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 610
 611                 /* shut down dsp_ck */
 612 -       if (!cpu_is_omap730())
 613 +       if (!cpu_is_omap7xx())
 614                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 615
 616         /* temporarily enabling api_ck to access DSP registers */
 617 @@ -383,12 +383,12 @@ void omap1_pm_suspend(void)
 618         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 619         ULPD_RESTORE(ULPD_STATUS_REQ);
 620
 621 -       if (cpu_is_omap730()) {
 622 -               MPUI730_RESTORE(EMIFS_CONFIG);
 623 -               MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
 624 -               MPUI730_RESTORE(OMAP_IH1_MIR);
 625 -               MPUI730_RESTORE(OMAP_IH2_0_MIR);
 626 -               MPUI730_RESTORE(OMAP_IH2_1_MIR);
 627 +       if (cpu_is_omap7xx()) {
 628 +               MPUI7XX_RESTORE(EMIFS_CONFIG);
 629 +               MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
 630 +               MPUI7XX_RESTORE(OMAP_IH1_MIR);
 631 +               MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
 632 +               MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
 633         } else if (cpu_is_omap15xx()) {
 634                 MPUI1510_RESTORE(MPUI_CTRL);
 635                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 636 @@ -461,13 +461,13 @@ static int omap_pm_read_proc(
 637         ULPD_SAVE(ULPD_DPLL_CTRL);
 638         ULPD_SAVE(ULPD_POWER_CTRL);
 639
 640 -       if (cpu_is_omap730()) {
 641 -               MPUI730_SAVE(MPUI_CTRL);
 642 -               MPUI730_SAVE(MPUI_DSP_STATUS);
 643 -               MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
 644 -               MPUI730_SAVE(MPUI_DSP_API_CONFIG);
 645 -               MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
 646 -               MPUI730_SAVE(EMIFS_CONFIG);
 647 +       if (cpu_is_omap7xx()) {
 648 +               MPUI7XX_SAVE(MPUI_CTRL);
 649 +               MPUI7XX_SAVE(MPUI_DSP_STATUS);
 650 +               MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 651 +               MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 652 +               MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 653 +               MPUI7XX_SAVE(EMIFS_CONFIG);
 654         } else if (cpu_is_omap15xx()) {
 655                 MPUI1510_SAVE(MPUI_CTRL);
 656                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 657 @@ -517,20 +517,20 @@ static int omap_pm_read_proc(
 658                    ULPD_SHOW(ULPD_STATUS_REQ),
 659                    ULPD_SHOW(ULPD_POWER_CTRL));
 660
 661 -               if (cpu_is_omap730()) {
 662 +               if (cpu_is_omap7xx()) {
 663                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 664 -                          "MPUI730_CTRL_REG         0x%-8x \n"
 665 -                          "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
 666 -                          "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 667 -                          "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
 668 -                          "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
 669 -                          "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
 670 -                          MPUI730_SHOW(MPUI_CTRL),
 671 -                          MPUI730_SHOW(MPUI_DSP_STATUS),
 672 -                          MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
 673 -                          MPUI730_SHOW(MPUI_DSP_API_CONFIG),
 674 -                          MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
 675 -                          MPUI730_SHOW(EMIFS_CONFIG));
 676 +                          "MPUI7XX_CTRL_REG         0x%-8x \n"
 677 +                          "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
 678 +                          "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 679 +                          "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
 680 +                          "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
 681 +                          "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
 682 +                          MPUI7XX_SHOW(MPUI_CTRL),
 683 +                          MPUI7XX_SHOW(MPUI_DSP_STATUS),
 684 +                          MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
 685 +                          MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
 686 +                          MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
 687 +                          MPUI7XX_SHOW(EMIFS_CONFIG));
 688                 } else if (cpu_is_omap15xx()) {
 689                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 690                            "MPUI1510_CTRL_REG             0x%-8x \n"
 691 @@ -668,9 +668,9 @@ static int __init omap_pm_init(void)
 692          * These routines need to be in SRAM as that's the only
 693          * memory the MPU can see when it wakes up.
 694          */
 695 -       if (cpu_is_omap730()) {
 696 -               omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
 697 -                                                  omap730_cpu_suspend_sz);
 698 +       if (cpu_is_omap7xx()) {
 699 +               omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
 700 +                                                  omap7xx_cpu_suspend_sz);
 701         } else if (cpu_is_omap15xx()) {
 702                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 703                                                    omap1510_cpu_suspend_sz);
 704 @@ -686,8 +686,8 @@ static int __init omap_pm_init(void)
 705
 706         pm_idle = omap1_pm_idle;
 707
 708 -       if (cpu_is_omap730())
 709 -               setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
 710 +       if (cpu_is_omap7xx())
 711 +               setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
 712         else if (cpu_is_omap16xx())
 713                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 714
 715 @@ -700,8 +700,8 @@ static int __init omap_pm_init(void)
 716         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 717
 718         /* Configure IDLECT3 */
 719 -       if (cpu_is_omap730())
 720 -               omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
 721 +       if (cpu_is_omap7xx())
 722 +               omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
 723         else if (cpu_is_omap16xx())
 724                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 725
 726 diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h
 727 index c4f05bd..56a6479 100644
 728 --- a/arch/arm/mach-omap1/pm.h
 729 +++ b/arch/arm/mach-omap1/pm.h
 730 @@ -98,13 +98,14 @@
 731  #define OMAP1610_IDLECT3               0xfffece24
 732  #define OMAP1610_IDLE_LOOP_REQUEST     0x0400
 733
 734 -#define OMAP730_IDLECT1_SLEEP_VAL      0x16c7
 735 -#define OMAP730_IDLECT2_SLEEP_VAL      0x09c7
 736 -#define OMAP730_IDLECT3_VAL            0x3f
 737 -#define OMAP730_IDLECT3                0xfffece24
 738 -#define OMAP730_IDLE_LOOP_REQUEST      0x0C00
 739 +#define OMAP7XX_IDLECT1_SLEEP_VAL      0x16c7
 740 +#define OMAP7XX_IDLECT2_SLEEP_VAL      0x09c7
 741 +#define OMAP7XX_IDLECT3_VAL            0x3f
 742 +#define OMAP7XX_IDLECT3                0xfffece24
 743 +#define OMAP7XX_IDLE_LOOP_REQUEST      0x0C00
 744
 745  #if     !defined(CONFIG_ARCH_OMAP730) && \
 746 +       !defined(CONFIG_ARCH_OMAP850) && \
 747         !defined(CONFIG_ARCH_OMAP15XX) && \
 748         !defined(CONFIG_ARCH_OMAP16XX)
 749  #warning "Power management for this processor not implemented yet"
 750 @@ -122,17 +123,17 @@ extern void allow_idle_sleep(void);
 751  extern void omap1_pm_idle(void);
 752  extern void omap1_pm_suspend(void);
 753
 754 -extern void omap730_cpu_suspend(unsigned short, unsigned short);
 755 +extern void omap7xx_cpu_suspend(unsigned short, unsigned short);
 756  extern void omap1510_cpu_suspend(unsigned short, unsigned short);
 757  extern void omap1610_cpu_suspend(unsigned short, unsigned short);
 758 -extern void omap730_idle_loop_suspend(void);
 759 +extern void omap7xx_idle_loop_suspend(void);
 760  extern void omap1510_idle_loop_suspend(void);
 761  extern void omap1610_idle_loop_suspend(void);
 762
 763 -extern unsigned int omap730_cpu_suspend_sz;
 764 +extern unsigned int omap7xx_cpu_suspend_sz;
 765  extern unsigned int omap1510_cpu_suspend_sz;
 766  extern unsigned int omap1610_cpu_suspend_sz;
 767 -extern unsigned int omap730_idle_loop_suspend_sz;
 768 +extern unsigned int omap7xx_idle_loop_suspend_sz;
 769  extern unsigned int omap1510_idle_loop_suspend_sz;
 770  extern unsigned int omap1610_idle_loop_suspend_sz;
 771
 772 @@ -155,9 +156,9 @@ extern void omap_serial_wake_trigger(int enable);
 773  #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
 774  #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
 775
 776 -#define MPUI730_SAVE(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x] = omap_readl(x)
 777 -#define MPUI730_RESTORE(x) omap_writel((mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]), (x))
 778 -#define MPUI730_SHOW(x) mpui730_sleep_save[MPUI730_SLEEP_SAVE_##x]
 779 +#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
 780 +#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
 781 +#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
 782
 783  #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
 784  #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
 785 @@ -232,24 +233,24 @@ enum mpui1510_save_state {
 786  #endif
 787  };
 788
 789 -enum mpui730_save_state {
 790 -       MPUI730_SLEEP_SAVE_START = 0,
 791 +enum mpui7xx_save_state {
 792 +       MPUI7XX_SLEEP_SAVE_START = 0,
 793         /*
 794          * MPUI registers 32 bits
 795          */
 796 -       MPUI730_SLEEP_SAVE_MPUI_CTRL,
 797 -       MPUI730_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 798 -       MPUI730_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 799 -       MPUI730_SLEEP_SAVE_MPUI_DSP_STATUS,
 800 -       MPUI730_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 801 -       MPUI730_SLEEP_SAVE_EMIFS_CONFIG,
 802 -       MPUI730_SLEEP_SAVE_OMAP_IH1_MIR,
 803 -       MPUI730_SLEEP_SAVE_OMAP_IH2_0_MIR,
 804 -       MPUI730_SLEEP_SAVE_OMAP_IH2_1_MIR,
 805 -#if defined(CONFIG_ARCH_OMAP730)
 806 -       MPUI730_SLEEP_SAVE_SIZE
 807 +       MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
 808 +       MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 809 +       MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 810 +       MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
 811 +       MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 812 +       MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
 813 +       MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
 814 +       MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
 815 +       MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
 816 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 817 +       MPUI7XX_SLEEP_SAVE_SIZE
 818  #else
 819 -       MPUI730_SLEEP_SAVE_SIZE = 0
 820 +       MPUI7XX_SLEEP_SAVE_SIZE = 0
 821  #endif
 822  };
 823
 824 diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
 825 index d496e50..332c516 100644
 826 --- a/arch/arm/mach-omap1/serial.c
 827 +++ b/arch/arm/mach-omap1/serial.c
 828 @@ -64,7 +64,6 @@ static void __init omap_serial_reset(struct plat_serial8250_port *p)
 829
 830  static struct plat_serial8250_port serial_platform_data[] = {
 831         {
 832 -               .membase        = OMAP1_IO_ADDRESS(OMAP_UART1_BASE),
 833                 .mapbase        = OMAP_UART1_BASE,
 834                 .irq            = INT_UART1,
 835                 .flags          = UPF_BOOT_AUTOCONF,
 836 @@ -73,7 +72,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
 837                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
 838         },
 839         {
 840 -               .membase        = OMAP1_IO_ADDRESS(OMAP_UART2_BASE),
 841                 .mapbase        = OMAP_UART2_BASE,
 842                 .irq            = INT_UART2,
 843                 .flags          = UPF_BOOT_AUTOCONF,
 844 @@ -82,7 +80,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
 845                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
 846         },
 847         {
 848 -               .membase        = OMAP1_IO_ADDRESS(OMAP_UART3_BASE),
 849                 .mapbase        = OMAP_UART3_BASE,
 850                 .irq            = INT_UART3,
 851                 .flags          = UPF_BOOT_AUTOCONF,
 852 @@ -90,7 +87,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
 853                 .regshift       = 2,
 854                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
 855         },
 856 -       { },
 857  };
 858
 859  static struct platform_device serial_device = {
 860 @@ -110,18 +106,11 @@ void __init omap_serial_init(void)
 861  {
 862         int i;
 863
 864 -       if (cpu_is_omap730()) {
 865 +       if (cpu_is_omap7xx()) {
 866                 serial_platform_data[0].regshift = 0;
 867                 serial_platform_data[1].regshift = 0;
 868 -               serial_platform_data[0].irq = INT_730_UART_MODEM_1;
 869 -               serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
 870 -       }
 871 -
 872 -       if (cpu_is_omap850()) {
 873 -               serial_platform_data[0].regshift = 0;
 874 -               serial_platform_data[1].regshift = 0;
 875 -               serial_platform_data[0].irq = INT_850_UART_MODEM_1;
 876 -               serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
 877 +               serial_platform_data[0].irq = INT_7XX_UART_MODEM_1;
 878 +               serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2;
 879         }
 880
 881         if (cpu_is_omap15xx()) {
 882 @@ -130,9 +119,17 @@ void __init omap_serial_init(void)
 883                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
 884         }
 885
 886 -       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 887 +       for (i = 0; i < ARRAY_SIZE(serial_platform_data); i++) {
 888                 unsigned char reg;
 889
 890 +               /* Static mapping, never released */
 891 +               serial_platform_data[i].membase =
 892 +                       ioremap(serial_platform_data[i].mapbase, SZ_2K);
 893 +               if (!serial_platform_data[i].membase) {
 894 +                       printk(KERN_ERR "Could not ioremap uart%i\n", i);
 895 +                       continue;
 896 +               }
 897 +
 898                 switch (i) {
 899                 case 0:
 900                         uart1_ck = clk_get(NULL, "uart1_ck");
 901 diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
 902 index 22e8568..ef771ce 100644
 903 --- a/arch/arm/mach-omap1/sleep.S
 904 +++ b/arch/arm/mach-omap1/sleep.S
 905 @@ -1,7 +1,7 @@
 906  /*
 907   * linux/arch/arm/mach-omap1/sleep.S
 908   *
 909 - * Low-level OMAP730/1510/1610 sleep/wakeUp support
 910 + * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
 911   *
 912   * Initial SA1110 code:
 913   * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
 914 @@ -57,8 +57,8 @@
 915   *
 916   */
 917
 918 -#if defined(CONFIG_ARCH_OMAP730)
 919 -ENTRY(omap730_cpu_suspend)
 920 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 921 +ENTRY(omap7xx_cpu_suspend)
 922
 923         @ save registers on stack
 924         stmfd   sp!, {r0 - r12, lr}
 925 @@ -91,13 +91,13 @@ ENTRY(omap730_cpu_suspend)
 926
 927         @ turn off clock domains
 928         @ do not disable PERCK (0x04)
 929 -       mov     r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
 930 -       orr     r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
 931 +       mov     r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff
 932 +       orr     r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00
 933         strh    r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
 934
 935         @ request ARM idle
 936 -       mov     r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff
 937 -       orr     r3, r3, #OMAP730_IDLECT1_SLEEP_VAL & 0xff00
 938 +       mov     r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff
 939 +       orr     r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00
 940         strh    r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
 941
 942         @ disable instruction cache
 943 @@ -113,7 +113,7 @@ ENTRY(omap730_cpu_suspend)
 944         mov     r2, #0
 945         mcr     p15, 0, r2, c7, c0, 4           @ wait for interrupt
 946  /*
 947 - * omap730_cpu_suspend()'s resume point.
 948 + * omap7xx_cpu_suspend()'s resume point.
 949   *
 950   * It will just start executing here, so we'll restore stuff from the
 951   * stack.
 952 @@ -132,9 +132,9 @@ ENTRY(omap730_cpu_suspend)
 953         @ restore regs and return
 954         ldmfd   sp!, {r0 - r12, pc}
 955
 956 -ENTRY(omap730_cpu_suspend_sz)
 957 -       .word   . - omap730_cpu_suspend
 958 -#endif /* CONFIG_ARCH_OMAP730 */
 959 +ENTRY(omap7xx_cpu_suspend_sz)
 960 +       .word   . - omap7xx_cpu_suspend
 961 +#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
 962
 963  #ifdef CONFIG_ARCH_OMAP15XX
 964  ENTRY(omap1510_cpu_suspend)
 965 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
 966 index 8cb1677..6b7702f 100644
 967 --- a/arch/arm/mach-omap2/Makefile
 968 +++ b/arch/arm/mach-omap2/Makefile
 969 @@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_OMAP_4430SDP)               += board-4430sdp.o
 970  # Platform specific device init code
 971  obj-y                                  += usb-musb.o
 972  obj-$(CONFIG_MACH_OMAP2_TUSB6010)      += usb-tusb6010.o
 973 +obj-y                                  += usb-ehci.o
 974
 975  onenand-$(CONFIG_MTD_ONENAND_OMAP2)    := gpmc-onenand.o
 976  obj-y                                  += $(onenand-m) $(onenand-y)
 977 diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
 978 index 42217b3..e032a33 100644
 979 --- a/arch/arm/mach-omap2/board-2430sdp.c
 980 +++ b/arch/arm/mach-omap2/board-2430sdp.c
 981 @@ -221,7 +221,7 @@ static void __init omap_2430sdp_map_io(void)
 982  MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
 983         /* Maintainer: Syed Khasim - Texas Instruments Inc */
 984         .phys_io        = 0x48000000,
 985 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
 986 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
 987         .boot_params    = 0x80000100,
 988         .map_io         = omap_2430sdp_map_io,
 989         .init_irq       = omap_2430sdp_init_irq,
 990 diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
 991 index efaf053..81aabac 100644
 992 --- a/arch/arm/mach-omap2/board-3430sdp.c
 993 +++ b/arch/arm/mach-omap2/board-3430sdp.c
 994 @@ -484,6 +484,18 @@ static void enable_board_wakeup_source(void)
 995         omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
 996  }
 997
 998 +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
 999 +
1000 +       .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
1001 +       .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1002 +       .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1003 +
1004 +       .phy_reset  = true,
1005 +       .reset_gpio_port[0]  = 57,
1006 +       .reset_gpio_port[1]  = 61,
1007 +       .reset_gpio_port[2]  = -EINVAL
1008 +};
1009 +
1010  static void __init omap_3430sdp_init(void)
1011  {
1012         omap3430_i2c_init();
1013 @@ -500,6 +512,7 @@ static void __init omap_3430sdp_init(void)
1014         usb_musb_init();
1015         board_smc91x_init();
1016         enable_board_wakeup_source();
1017 +       usb_ehci_init(&ehci_pdata);
1018  }
1019
1020  static void __init omap_3430sdp_map_io(void)
1021 @@ -511,7 +524,7 @@ static void __init omap_3430sdp_map_io(void)
1022  MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
1023         /* Maintainer: Syed Khasim - Texas Instruments Inc */
1024         .phys_io        = 0x48000000,
1025 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1026 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1027         .boot_params    = 0x80000100,
1028         .map_io         = omap_3430sdp_map_io,
1029         .init_irq       = omap_3430sdp_init_irq,
1030 diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
1031 index eb37c40..50a62f2 100644
1032 --- a/arch/arm/mach-omap2/board-4430sdp.c
1033 +++ b/arch/arm/mach-omap2/board-4430sdp.c
1034 @@ -52,8 +52,17 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
1035
1036  static void __init gic_init_irq(void)
1037  {
1038 -       gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
1039 -       gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
1040 +       void __iomem *base;
1041 +
1042 +       /* Static mapping, never released */
1043 +       base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
1044 +       BUG_ON(!base);
1045 +       gic_dist_init(0, base, 29);
1046 +
1047 +       /* Static mapping, never released */
1048 +       base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
1049 +       BUG_ON(!base);
1050 +       gic_cpu_init(0, OMAP44XX_GIC_CPU_BASE);
1051  }
1052
1053  static void __init omap_4430sdp_init_irq(void)
1054 @@ -84,7 +93,7 @@ static void __init omap_4430sdp_map_io(void)
1055  MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
1056         /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
1057         .phys_io        = 0x48000000,
1058 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1059 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1060         .boot_params    = 0x80000100,
1061         .map_io         = omap_4430sdp_map_io,
1062         .init_irq       = omap_4430sdp_init_irq,
1063 diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
1064 index a113228..e8a0e56 100644
1065 --- a/arch/arm/mach-omap2/board-apollon.c
1066 +++ b/arch/arm/mach-omap2/board-apollon.c
1067 @@ -333,7 +333,7 @@ static void __init omap_apollon_map_io(void)
1068  MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
1069         /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1070         .phys_io        = 0x48000000,
1071 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1072 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1073         .boot_params    = 0x80000100,
1074         .map_io         = omap_apollon_map_io,
1075         .init_irq       = omap_apollon_init_irq,
1076 diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
1077 index 2e09a1c..1a139c0 100644
1078 --- a/arch/arm/mach-omap2/board-generic.c
1079 +++ b/arch/arm/mach-omap2/board-generic.c
1080 @@ -56,7 +56,7 @@ static void __init omap_generic_map_io(void)
1081  MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
1082         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
1083         .phys_io        = 0x48000000,
1084 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1085 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1086         .boot_params    = 0x80000100,
1087         .map_io         = omap_generic_map_io,
1088         .init_irq       = omap_generic_init_irq,
1089 diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
1090 index eaa02d0..86f78f3 100644
1091 --- a/arch/arm/mach-omap2/board-h4.c
1092 +++ b/arch/arm/mach-omap2/board-h4.c
1093 @@ -376,7 +376,7 @@ static void __init omap_h4_map_io(void)
1094  MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
1095         /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
1096         .phys_io        = 0x48000000,
1097 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1098 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1099         .boot_params    = 0x80000100,
1100         .map_io         = omap_h4_map_io,
1101         .init_irq       = omap_h4_init_irq,
1102 diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
1103 index d110a7f..4ccc01a 100644
1104 --- a/arch/arm/mach-omap2/board-ldp.c
1105 +++ b/arch/arm/mach-omap2/board-ldp.c
1106 @@ -399,7 +399,7 @@ static void __init omap_ldp_map_io(void)
1107
1108  MACHINE_START(OMAP_LDP, "OMAP LDP board")
1109         .phys_io        = 0x48000000,
1110 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1111 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1112         .boot_params    = 0x80000100,
1113         .map_io         = omap_ldp_map_io,
1114         .init_irq       = omap_ldp_init_irq,
1115 diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
1116 index 8341632..2f6ccba 100644
1117 --- a/arch/arm/mach-omap2/board-n8x0.c
1118 +++ b/arch/arm/mach-omap2/board-n8x0.c
1119 @@ -121,7 +121,7 @@ static void __init n8x0_init_machine(void)
1120
1121  MACHINE_START(NOKIA_N800, "Nokia N800")
1122         .phys_io        = 0x48000000,
1123 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1124 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1125         .boot_params    = 0x80000100,
1126         .map_io         = n8x0_map_io,
1127         .init_irq       = n8x0_init_irq,
1128 @@ -131,7 +131,7 @@ MACHINE_END
1129
1130  MACHINE_START(NOKIA_N810, "Nokia N810")
1131         .phys_io        = 0x48000000,
1132 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1133 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1134         .boot_params    = 0x80000100,
1135         .map_io         = n8x0_map_io,
1136         .init_irq       = n8x0_init_irq,
1137 @@ -141,7 +141,7 @@ MACHINE_END
1138
1139  MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
1140         .phys_io        = 0x48000000,
1141 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1142 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1143         .boot_params    = 0x80000100,
1144         .map_io         = n8x0_map_io,
1145         .init_irq       = n8x0_init_irq,
1146 diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
1147 index 70df6b4..9824073 100644
1148 --- a/arch/arm/mach-omap2/board-omap3beagle.c
1149 +++ b/arch/arm/mach-omap2/board-omap3beagle.c
1150 @@ -400,6 +400,18 @@ static void __init omap3beagle_flash_init(void)
1151         }
1152  }
1153
1154 +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1155 +
1156 +       .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
1157 +       .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1158 +       .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1159 +
1160 +       .phy_reset  = true,
1161 +       .reset_gpio_port[0]  = -EINVAL,
1162 +       .reset_gpio_port[1]  = 147,
1163 +       .reset_gpio_port[2]  = -EINVAL
1164 +};
1165 +
1166  static void __init omap3_beagle_init(void)
1167  {
1168         omap3_beagle_i2c_init();
1169 @@ -413,6 +425,7 @@ static void __init omap3_beagle_init(void)
1170         gpio_direction_output(170, true);
1171
1172         usb_musb_init();
1173 +       usb_ehci_init(&ehci_pdata);
1174         omap3beagle_flash_init();
1175
1176         /* Ensure SDRC pins are mux'd for self-refresh */
1177 @@ -429,7 +442,7 @@ static void __init omap3_beagle_map_io(void)
1178  MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
1179         /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
1180         .phys_io        = 0x48000000,
1181 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1182 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1183         .boot_params    = 0x80000100,
1184         .map_io         = omap3_beagle_map_io,
1185         .init_irq       = omap3_beagle_init_irq,
1186 diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
1187 index e4ec0c5..9e0b6e6 100644
1188 --- a/arch/arm/mach-omap2/board-omap3evm.c
1189 +++ b/arch/arm/mach-omap2/board-omap3evm.c
1190 @@ -297,6 +297,18 @@ static struct platform_device *omap3_evm_devices[] __initdata = {
1191         &omap3evm_smc911x_device,
1192  };
1193
1194 +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1195 +
1196 +       .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1197 +       .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1198 +       .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1199 +
1200 +       .phy_reset  = true,
1201 +       .reset_gpio_port[0]  = -EINVAL,
1202 +       .reset_gpio_port[1]  = 135,
1203 +       .reset_gpio_port[2]  = -EINVAL
1204 +};
1205 +
1206  static void __init omap3_evm_init(void)
1207  {
1208         omap3_evm_i2c_init();
1209 @@ -312,6 +324,9 @@ static void __init omap3_evm_init(void)
1210         usb_nop_xceiv_register();
1211  #endif
1212         usb_musb_init();
1213 +       /* Setup EHCI phy reset padconfig */
1214 +       omap_cfg_reg(AF4_34XX_GPIO135_OUT);
1215 +       usb_ehci_init(&ehci_pdata);
1216         ads7846_dev_init();
1217  }
1218
1219 @@ -324,7 +339,7 @@ static void __init omap3_evm_map_io(void)
1220  MACHINE_START(OMAP3EVM, "OMAP3 EVM")
1221         /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
1222         .phys_io        = 0x48000000,
1223 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1224 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1225         .boot_params    = 0x80000100,
1226         .map_io         = omap3_evm_map_io,
1227         .init_irq       = omap3_evm_init_irq,
1228 diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
1229 index 7f6bf87..82b2486 100644
1230 --- a/arch/arm/mach-omap2/board-omap3pandora.c
1231 +++ b/arch/arm/mach-omap2/board-omap3pandora.c
1232 @@ -387,6 +387,18 @@ static struct platform_device *omap3pandora_devices[] __initdata = {
1233         &pandora_keys_gpio,
1234  };
1235
1236 +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1237 +
1238 +       .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
1239 +       .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1240 +       .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1241 +
1242 +       .phy_reset  = true,
1243 +       .reset_gpio_port[0]  = 16,
1244 +       .reset_gpio_port[1]  = -EINVAL,
1245 +       .reset_gpio_port[2]  = -EINVAL
1246 +};
1247 +
1248  static void __init omap3pandora_init(void)
1249  {
1250         omap3pandora_i2c_init();
1251 @@ -396,6 +408,7 @@ static void __init omap3pandora_init(void)
1252         spi_register_board_info(omap3pandora_spi_board_info,
1253                         ARRAY_SIZE(omap3pandora_spi_board_info));
1254         omap3pandora_ads7846_init();
1255 +       usb_ehci_init(&ehci_pdata);
1256         pandora_keys_gpio_init();
1257         usb_musb_init();
1258
1259 @@ -412,7 +425,7 @@ static void __init omap3pandora_map_io(void)
1260
1261  MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
1262         .phys_io        = 0x48000000,
1263 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1264 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1265         .boot_params    = 0x80000100,
1266         .map_io         = omap3pandora_map_io,
1267         .init_irq       = omap3pandora_init_irq,
1268 diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
1269 index 9917d2f..d50a3f0 100644
1270 --- a/arch/arm/mach-omap2/board-overo.c
1271 +++ b/arch/arm/mach-omap2/board-overo.c
1272 @@ -384,6 +384,18 @@ static struct platform_device *overo_devices[] __initdata = {
1273         &overo_lcd_device,
1274  };
1275
1276 +static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
1277 +       .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1278 +       .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
1279 +       .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
1280 +
1281 +       .phy_reset  = true,
1282 +       .reset_gpio_port[0]  = -EINVAL,
1283 +       .reset_gpio_port[1]  = OVERO_GPIO_USBH_NRESET,
1284 +       .reset_gpio_port[2]  = -EINVAL
1285 +};
1286 +
1287 +
1288  static void __init overo_init(void)
1289  {
1290         overo_i2c_init();
1291 @@ -391,6 +403,7 @@ static void __init overo_init(void)
1292         omap_serial_init();
1293         overo_flash_init();
1294         usb_musb_init();
1295 +       usb_ehci_init(&ehci_pdata);
1296         overo_ads7846_init();
1297         overo_init_smsc911x();
1298
1299 @@ -433,14 +446,6 @@ static void __init overo_init(void)
1300         else
1301                 printk(KERN_ERR "could not obtain gpio for "
1302                                         "OVERO_GPIO_USBH_CPEN\n");
1303 -
1304 -       if ((gpio_request(OVERO_GPIO_USBH_NRESET,
1305 -                         "OVERO_GPIO_USBH_NRESET") == 0) &&
1306 -           (gpio_direction_output(OVERO_GPIO_USBH_NRESET, 1) == 0))
1307 -               gpio_export(OVERO_GPIO_USBH_NRESET, 0);
1308 -       else
1309 -               printk(KERN_ERR "could not obtain gpio for "
1310 -                                       "OVERO_GPIO_USBH_NRESET\n");
1311  }
1312
1313  static void __init overo_map_io(void)
1314 @@ -451,7 +456,7 @@ static void __init overo_map_io(void)
1315
1316  MACHINE_START(OVERO, "Gumstix Overo")
1317         .phys_io        = 0x48000000,
1318 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1319 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1320         .boot_params    = 0x80000100,
1321         .map_io         = overo_map_io,
1322         .init_irq       = overo_init_irq,
1323 diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
1324 index f9196c3..c973812 100644
1325 --- a/arch/arm/mach-omap2/board-rx51.c
1326 +++ b/arch/arm/mach-omap2/board-rx51.c
1327 @@ -85,7 +85,7 @@ static void __init rx51_map_io(void)
1328  MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
1329         /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
1330         .phys_io        = 0x48000000,
1331 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1332 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1333         .boot_params    = 0x80000100,
1334         .map_io         = rx51_map_io,
1335         .init_irq       = rx51_init_irq,
1336 diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
1337 index fd3369d..48bd2af 100644
1338 --- a/arch/arm/mach-omap2/board-zoom2.c
1339 +++ b/arch/arm/mach-omap2/board-zoom2.c
1340 @@ -283,7 +283,7 @@ static void __init omap_zoom2_map_io(void)
1341
1342  MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
1343         .phys_io        = 0x48000000,
1344 -       .io_pg_offst    = ((0xd8000000) >> 18) & 0xfffc,
1345 +       .io_pg_offst    = ((0xfa000000) >> 18) & 0xfffc,
1346         .boot_params    = 0x80000100,
1347         .map_io         = omap_zoom2_map_io,
1348         .init_irq       = omap_zoom2_init_irq,
1349 diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
1350 index cfd0b72..a2fcfcc 100644
1351 --- a/arch/arm/mach-omap2/cm.h
1352 +++ b/arch/arm/mach-omap2/cm.h
1353 @@ -17,11 +17,11 @@
1354  #include "prcm-common.h"
1355
1356  #define OMAP2420_CM_REGADDR(module, reg)                               \
1357 -                       OMAP2_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
1358 +                       OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
1359  #define OMAP2430_CM_REGADDR(module, reg)                               \
1360 -                       OMAP2_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
1361 +                       OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
1362  #define OMAP34XX_CM_REGADDR(module, reg)                               \
1363 -                       OMAP2_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
1364 +                       OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
1365
1366  /*
1367   * Architecture-specific global CM registers
1368 diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
1369 index a98201c..71d5568 100644
1370 --- a/arch/arm/mach-omap2/id.c
1371 +++ b/arch/arm/mach-omap2/id.c
1372 @@ -28,6 +28,7 @@
1373  static struct omap_chip_id omap_chip;
1374  static unsigned int omap_revision;
1375
1376 +u32 omap3_features;
1377
1378  unsigned int omap_rev(void)
1379  {
1380 @@ -155,12 +156,37 @@ void __init omap24xx_check_revision(void)
1381         pr_info("\n");
1382  }
1383
1384 -void __init omap34xx_check_revision(void)
1385 +#define OMAP3_CHECK_FEATURE(status,feat)                               \
1386 +       if (((status & OMAP3_ ##feat## _MASK)                           \
1387 +               >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
1388 +               omap3_features |= OMAP3_HAS_ ##feat;                    \
1389 +       }
1390 +
1391 +void __init omap3_check_features(void)
1392 +{
1393 +       u32 status;
1394 +
1395 +       omap3_features = 0;
1396 +
1397 +       status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
1398 +
1399 +       OMAP3_CHECK_FEATURE(status, L2CACHE);
1400 +       OMAP3_CHECK_FEATURE(status, IVA);
1401 +       OMAP3_CHECK_FEATURE(status, SGX);
1402 +       OMAP3_CHECK_FEATURE(status, NEON);
1403 +       OMAP3_CHECK_FEATURE(status, ISP);
1404 +
1405 +       /*
1406 +        * TODO: Get additional info (where applicable)
1407 +        *       e.g. Size of L2 cache.
1408 +        */
1409 +}
1410 +
1411 +void __init omap3_check_revision(void)
1412  {
1413         u32 cpuid, idcode;
1414         u16 hawkeye;
1415         u8 rev;
1416 -       char *rev_name = "ES1.0";
1417
1418         /*
1419          * We cannot access revision registers on ES1.0.
1420 @@ -170,7 +196,7 @@ void __init omap34xx_check_revision(void)
1421         cpuid = read_cpuid(CPUID_ID);
1422         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
1423                 omap_revision = OMAP3430_REV_ES1_0;
1424 -               goto out;
1425 +               return;
1426         }
1427
1428         /*
1429 @@ -183,33 +209,111 @@ void __init omap34xx_check_revision(void)
1430         hawkeye = (idcode >> 12) & 0xffff;
1431         rev = (idcode >> 28) & 0xff;
1432
1433 -       if (hawkeye == 0xb7ae) {
1434 +       switch (hawkeye) {
1435 +       case 0xb7ae:
1436 +               /* Handle 34xx/35xx devices */
1437                 switch (rev) {
1438 -               case 0:
1439 +               case 0: /* Take care of early samples */
1440 +               case 1:
1441                         omap_revision = OMAP3430_REV_ES2_0;
1442 -                       rev_name = "ES2.0";
1443                         break;
1444                 case 2:
1445                         omap_revision = OMAP3430_REV_ES2_1;
1446 -                       rev_name = "ES2.1";
1447                         break;
1448                 case 3:
1449                         omap_revision = OMAP3430_REV_ES3_0;
1450 -                       rev_name = "ES3.0";
1451                         break;
1452                 case 4:
1453                         omap_revision = OMAP3430_REV_ES3_1;
1454 -                       rev_name = "ES3.1";
1455                         break;
1456                 default:
1457                         /* Use the latest known revision as default */
1458                         omap_revision = OMAP3430_REV_ES3_1;
1459 -                       rev_name = "Unknown revision\n";
1460                 }
1461 +               break;
1462 +       case 0xb891:
1463 +               /* Handle 36xx devices */
1464 +               switch (rev) {
1465 +               case 0:
1466 +                       omap_revision = OMAP3630_REV_ES1_0;
1467 +                       break;
1468 +               default:
1469 +                       /* Use the latest known revision as default */
1470 +                       omap_revision = OMAP3630_REV_ES1_0;
1471 +               }
1472 +               break;
1473 +       default:
1474 +               /* Unknown default to latest silicon rev as default*/
1475 +               omap_revision = OMAP3630_REV_ES1_0;
1476         }
1477 +}
1478
1479 -out:
1480 -       pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
1481 +#define OMAP3_SHOW_FEATURE(feat)               \
1482 +       if (omap3_has_ ##feat()) {              \
1483 +               pr_info (" - "#feat" : Y");     \
1484 +       } else {                                \
1485 +               pr_info (" - "#feat" : N");     \
1486 +       }
1487 +
1488 +void __init omap3_cpuinfo(void)
1489 +{
1490 +       u8 rev = GET_OMAP_REVISION();
1491 +       char cpu_name[16], cpu_rev[16];
1492 +
1493 +       /* OMAP3430 and OMAP3530 are assumed to be same.
1494 +        *
1495 +        * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
1496 +        * on available features. Upon detection, update the CPU id
1497 +        * and CPU class bits.
1498 +        */
1499 +       if (cpu_is_omap3630())
1500 +               strcpy(cpu_name, "3630");
1501 +       else if (omap3_has_iva() && omap3_has_sgx())
1502 +               strcpy(cpu_name, "3430/3530");
1503 +       else if (omap3_has_sgx()) {
1504 +               omap_revision = OMAP3525_REV(rev);
1505 +               strcpy(cpu_name, "3525");
1506 +       }
1507 +       else if (omap3_has_iva()) {
1508 +               omap_revision = OMAP3515_REV(rev);
1509 +               strcpy(cpu_name, "3515");
1510 +       }
1511 +       else {
1512 +               omap_revision = OMAP3503_REV(rev);
1513 +               strcpy(cpu_name, "3503");
1514 +       }
1515 +
1516 +       switch (rev) {
1517 +       case OMAP_REVBITS_00:
1518 +               strcpy(cpu_rev, "1.0");
1519 +               break;
1520 +       case OMAP_REVBITS_10:
1521 +               strcpy(cpu_rev, "2.0");
1522 +               break;
1523 +       case OMAP_REVBITS_20:
1524 +               strcpy(cpu_rev, "2.1");
1525 +               break;
1526 +       case OMAP_REVBITS_30:
1527 +               strcpy(cpu_rev, "3.0");
1528 +               break;
1529 +       case OMAP_REVBITS_40:
1530 +               strcpy(cpu_rev, "3.1");
1531 +               break;
1532 +       default:
1533 +               /* Use the latest known revision as default */
1534 +               strcpy(cpu_rev, "3.1");
1535 +       }
1536 +
1537 +       /*
1538 +        * Print verbose information
1539 +        */
1540 +       pr_info("OMAP%s ES%s\n", cpu_name, cpu_rev);
1541 +
1542 +       OMAP3_SHOW_FEATURE(l2cache);
1543 +       OMAP3_SHOW_FEATURE(iva);
1544 +       OMAP3_SHOW_FEATURE(sgx);
1545 +       OMAP3_SHOW_FEATURE(neon);
1546 +       OMAP3_SHOW_FEATURE(isp);
1547  }
1548
1549  /*
1550 @@ -223,8 +327,11 @@ void __init omap2_check_revision(void)
1551          */
1552         if (cpu_is_omap24xx())
1553                 omap24xx_check_revision();
1554 -       else if (cpu_is_omap34xx())
1555 -               omap34xx_check_revision();
1556 +       else if (cpu_is_omap34xx()) {
1557 +               omap3_check_features();
1558 +               omap3_check_revision();
1559 +               omap3_cpuinfo();
1560 +       }
1561         else if (cpu_is_omap44xx()) {
1562                 printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
1563                 return;
1564 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
1565 index e3a3bad..fc62953 100644
1566 --- a/arch/arm/mach-omap2/io.c
1567 +++ b/arch/arm/mach-omap2/io.c
1568 @@ -203,6 +203,24 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
1569                 .type           = MT_DEVICE,
1570         },
1571         {
1572 +               .virtual        = OMAP44XX_EMIF1_VIRT,
1573 +               .pfn            = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
1574 +               .length         = OMAP44XX_EMIF1_SIZE,
1575 +               .type           = MT_DEVICE,
1576 +       },
1577 +       {
1578 +               .virtual        = OMAP44XX_EMIF2_VIRT,
1579 +               .pfn            = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
1580 +               .length         = OMAP44XX_EMIF2_SIZE,
1581 +               .type           = MT_DEVICE,
1582 +       },
1583 +       {
1584 +               .virtual        = OMAP44XX_DMM_VIRT,
1585 +               .pfn            = __phys_to_pfn(OMAP44XX_DMM_PHYS),
1586 +               .length         = OMAP44XX_DMM_SIZE,
1587 +               .type           = MT_DEVICE,
1588 +       },
1589 +       {
1590                 .virtual        = L4_PER_44XX_VIRT,
1591                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
1592                 .length         = L4_PER_44XX_SIZE,
1593 diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
1594 index b828638..1db121f 100644
1595 --- a/arch/arm/mach-omap2/irq.c
1596 +++ b/arch/arm/mach-omap2/irq.c
1597 @@ -178,12 +178,20 @@ void __init omap_init_irq(void)
1598         int i;
1599
1600         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
1601 +               unsigned long base;
1602                 struct omap_irq_bank *bank = irq_banks + i;
1603
1604                 if (cpu_is_omap24xx())
1605 -                       bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
1606 +                       base = OMAP24XX_IC_BASE;
1607                 else if (cpu_is_omap34xx())
1608 -                       bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
1609 +                       base = OMAP34XX_IC_BASE;
1610 +
1611 +               /* Static mapping, never released */
1612 +               bank->base_reg = ioremap(base, SZ_4K);
1613 +               if (!bank->base_reg) {
1614 +                       printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
1615 +                       continue;
1616 +               }
1617
1618                 omap_irq_bank_init_one(bank);
1619
1620 diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
1621 index 48ee295..a1b618c 100644
1622 --- a/arch/arm/mach-omap2/omap-smp.c
1623 +++ b/arch/arm/mach-omap2/omap-smp.c
1624 @@ -26,11 +26,11 @@
1625  #include <mach/hardware.h>
1626
1627  /* Registers used for communicating startup information */
1628 -#define OMAP4_AUXCOREBOOT_REG0         (OMAP44XX_VA_WKUPGEN_BASE + 0x800)
1629 -#define OMAP4_AUXCOREBOOT_REG1         (OMAP44XX_VA_WKUPGEN_BASE + 0x804)
1630 +static void __iomem *omap4_auxcoreboot_reg0;
1631 +static void __iomem *omap4_auxcoreboot_reg1;
1632
1633  /* SCU base address */
1634 -static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE;
1635 +static void __iomem *scu_base;
1636
1637  /*
1638   * Use SCU config register to count number of cores
1639 @@ -46,6 +46,8 @@ static DEFINE_SPINLOCK(boot_lock);
1640
1641  void __cpuinit platform_secondary_init(unsigned int cpu)
1642  {
1643 +       void __iomem *gic_cpu_base;
1644 +
1645         trace_hardirqs_off();
1646
1647         /*
1648 @@ -54,7 +56,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
1649          * for us: do so
1650          */
1651
1652 -       gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
1653 +       /* Static mapping, never released */
1654 +       gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
1655 +       BUG_ON(!gic_cpu_base);
1656 +       gic_cpu_init(0, gic_cpu_base);
1657
1658         /*
1659          * Synchronise with the boot thread.
1660 @@ -79,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
1661          * the AuxCoreBoot1 register is updated with cpu state
1662          * A barrier is added to ensure that write buffer is drained
1663          */
1664 -       __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1);
1665 +       __raw_writel(cpu, omap4_auxcoreboot_reg1);
1666         smp_wmb();
1667
1668         timeout = jiffies + (1 * HZ);
1669 @@ -104,7 +109,7 @@ static void __init wakeup_secondary(void)
1670          * A barrier is added to ensure that write buffer is drained
1671          */
1672         __raw_writel(virt_to_phys(omap_secondary_startup),         \
1673 -                                       OMAP4_AUXCOREBOOT_REG0);
1674 +                                       omap4_auxcoreboot_reg0);
1675         smp_wmb();
1676
1677         /*
1678 @@ -130,6 +135,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
1679  {
1680         unsigned int ncores = get_core_count();
1681         unsigned int cpu = smp_processor_id();
1682 +       void __iomem *omap4_wkupgen_base;
1683         int i;
1684
1685         /* sanity check */
1686 @@ -161,6 +167,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
1687         for (i = 0; i < max_cpus; i++)
1688                 set_cpu_present(i, true);
1689
1690 +       /* Never released */
1691 +       omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
1692 +       BUG_ON(!omap4_wkupgen_base);
1693 +       omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
1694 +       omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x804;
1695 +
1696 +       /* Never released */
1697 +       scu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_256);
1698 +       BUG_ON(!scu_base);
1699 +
1700         if (max_cpus > 1) {
1701                 /*
1702                  * Enable the local timer or broadcast device for the
1703 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
1704 index d2e0f1c..8ac8798 100644
1705 --- a/arch/arm/mach-omap2/omap_hwmod.c
1706 +++ b/arch/arm/mach-omap2/omap_hwmod.c
1707 @@ -496,6 +496,7 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
1708         struct omap_hwmod_addr_space *mem;
1709         int i;
1710         int found = 0;
1711 +       void __iomem *va_start;
1712
1713         if (!oh || oh->slaves_cnt == 0)
1714                 return NULL;
1715 @@ -509,16 +510,20 @@ static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
1716                 }
1717         }
1718
1719 -       /* XXX use ioremap() instead? */
1720 -
1721 -       if (found)
1722 +       if (found) {
1723 +               va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
1724 +               if (!va_start) {
1725 +                       pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
1726 +                       return NULL;
1727 +               }
1728                 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
1729 -                        oh->name, OMAP2_IO_ADDRESS(mem->pa_start));
1730 -       else
1731 +                        oh->name, va_start);
1732 +       } else {
1733                 pr_debug("omap_hwmod: %s: no MPU register target found\n",
1734                          oh->name);
1735 +       }
1736
1737 -       return (found) ? OMAP2_IO_ADDRESS(mem->pa_start) : NULL;
1738 +       return (found) ? va_start : NULL;
1739  }
1740
1741  /**
1742 @@ -1148,6 +1153,7 @@ int omap_hwmod_unregister(struct omap_hwmod *oh)
1743         pr_debug("omap_hwmod: %s: unregistering\n", oh->name);
1744
1745         mutex_lock(&omap_hwmod_mutex);
1746 +       iounmap(oh->_rt_va);
1747         list_del(&oh->node);
1748         mutex_unlock(&omap_hwmod_mutex);
1749
1750 diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
1751 index 2fc4d6a..deed1dd 100644
1752 --- a/arch/arm/mach-omap2/pm-debug.c
1753 +++ b/arch/arm/mach-omap2/pm-debug.c
1754 @@ -51,7 +51,8 @@ int omap2_pm_debug;
1755         regs[reg_count++].val = __raw_readl(reg)
1756  #define DUMP_INTC_REG(reg, off) \
1757         regs[reg_count].name = #reg; \
1758 -       regs[reg_count++].val = __raw_readl(OMAP2_IO_ADDRESS(0x480fe000 + (off)))
1759 +       regs[reg_count++].val = \
1760 +                        __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
1761
1762  static int __init pm_dbg_init(void);
1763
1764 diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
1765 index 03c467c..a117f85 100644
1766 --- a/arch/arm/mach-omap2/prm.h
1767 +++ b/arch/arm/mach-omap2/prm.h
1768 @@ -17,11 +17,11 @@
1769  #include "prcm-common.h"
1770
1771  #define OMAP2420_PRM_REGADDR(module, reg)                              \
1772 -                       OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
1773 +               OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
1774  #define OMAP2430_PRM_REGADDR(module, reg)                              \
1775 -                       OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
1776 +               OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
1777  #define OMAP34XX_PRM_REGADDR(module, reg)                              \
1778 -                       OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
1779 +               OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
1780
1781  /*
1782   * Architecture-specific global PRM registers
1783 diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
1784 index 0837eda..345183d 100644
1785 --- a/arch/arm/mach-omap2/sdrc.h
1786 +++ b/arch/arm/mach-omap2/sdrc.h
1787 @@ -48,9 +48,12 @@ static inline u32 sms_read_reg(u16 reg)
1788         return __raw_readl(OMAP_SMS_REGADDR(reg));
1789  }
1790  #else
1791 -#define OMAP242X_SDRC_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
1792 -#define OMAP243X_SDRC_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
1793 -#define OMAP34XX_SDRC_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
1794 +#define OMAP242X_SDRC_REGADDR(reg)                                     \
1795 +                       OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg))
1796 +#define OMAP243X_SDRC_REGADDR(reg)                                     \
1797 +                       OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg))
1798 +#define OMAP34XX_SDRC_REGADDR(reg)                                     \
1799 +                       OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg))
1800  #endif /* __ASSEMBLER__ */
1801
1802  #endif
1803 diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
1804 index ae21868..7f722a7 100644
1805 --- a/arch/arm/mach-omap2/serial.c
1806 +++ b/arch/arm/mach-omap2/serial.c
1807 @@ -73,7 +73,6 @@ static LIST_HEAD(uart_list);
1808
1809  static struct plat_serial8250_port serial_platform_data0[] = {
1810         {
1811 -               .membase        = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
1812                 .mapbase        = OMAP_UART1_BASE,
1813                 .irq            = 72,
1814                 .flags          = UPF_BOOT_AUTOCONF,
1815 @@ -87,7 +86,6 @@ static struct plat_serial8250_port serial_platform_data0[] = {
1816
1817  static struct plat_serial8250_port serial_platform_data1[] = {
1818         {
1819 -               .membase        = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
1820                 .mapbase        = OMAP_UART2_BASE,
1821                 .irq            = 73,
1822                 .flags          = UPF_BOOT_AUTOCONF,
1823 @@ -101,7 +99,6 @@ static struct plat_serial8250_port serial_platform_data1[] = {
1824
1825  static struct plat_serial8250_port serial_platform_data2[] = {
1826         {
1827 -               .membase        = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
1828                 .mapbase        = OMAP_UART3_BASE,
1829                 .irq            = 74,
1830                 .flags          = UPF_BOOT_AUTOCONF,
1831 @@ -110,7 +107,6 @@ static struct plat_serial8250_port serial_platform_data2[] = {
1832                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
1833         }, {
1834  #ifdef CONFIG_ARCH_OMAP4
1835 -               .membase        = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
1836                 .mapbase        = OMAP_UART4_BASE,
1837                 .irq            = 70,
1838                 .flags          = UPF_BOOT_AUTOCONF,
1839 @@ -126,7 +122,6 @@ static struct plat_serial8250_port serial_platform_data2[] = {
1840  #ifdef CONFIG_ARCH_OMAP4
1841  static struct plat_serial8250_port serial_platform_data3[] = {
1842         {
1843 -               .membase        = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
1844                 .mapbase        = OMAP_UART4_BASE,
1845                 .irq            = 70,
1846                 .flags          = UPF_BOOT_AUTOCONF,
1847 @@ -549,7 +544,7 @@ static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
1848  #define DEV_CREATE_FILE(dev, attr)
1849  #endif /* CONFIG_PM */
1850
1851 -static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
1852 +static struct omap_uart_state omap_uart[] = {
1853         {
1854                 .pdev = {
1855                         .name                   = "serial8250",
1856 @@ -599,12 +594,22 @@ void __init omap_serial_early_init(void)
1857          * if not needed.
1858          */
1859
1860 -       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
1861 +       for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
1862                 struct omap_uart_state *uart = &omap_uart[i];
1863                 struct platform_device *pdev = &uart->pdev;
1864                 struct device *dev = &pdev->dev;
1865                 struct plat_serial8250_port *p = dev->platform_data;
1866
1867 +               /*
1868 +                * Module 4KB + L4 interconnect 4KB
1869 +                * Static mapping, never released
1870 +                */
1871 +               p->membase = ioremap(p->mapbase, SZ_8K);
1872 +               if (!p->membase) {
1873 +                       printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
1874 +                       continue;
1875 +               }
1876 +
1877                 sprintf(name, "uart%d_ick", i+1);
1878                 uart->ick = clk_get(NULL, name);
1879                 if (IS_ERR(uart->ick)) {
1880 @@ -641,7 +646,7 @@ void __init omap_serial_init(void)
1881  {
1882         int i;
1883
1884 -       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
1885 +       for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
1886                 struct omap_uart_state *uart = &omap_uart[i];
1887                 struct platform_device *pdev = &uart->pdev;
1888                 struct device *dev = &pdev->dev;
1889 diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
1890 index 9b62208..92e6e1a 100644
1891 --- a/arch/arm/mach-omap2/sram242x.S
1892 +++ b/arch/arm/mach-omap2/sram242x.S
1893 @@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
1894  prcm_mask_val:
1895         .word 0xFFFF3FFC
1896  omap242x_sdi_timer_32ksynct_cr:
1897 -       .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1898 +       .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1899  ENTRY(omap242x_sram_ddr_init_sz)
1900         .word   . - omap242x_sram_ddr_init
1901
1902 @@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
1903  ddr_prcm_mask_val:
1904         .word 0xFFFF3FFC
1905  omap242x_srs_timer_32ksynct:
1906 -       .word OMAP2_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1907 +       .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
1908
1909  ENTRY(omap242x_sram_reprogram_sdrc_sz)
1910         .word   . - omap242x_sram_reprogram_sdrc
1911 diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
1912 index df2cd92..ab49736 100644
1913 --- a/arch/arm/mach-omap2/sram243x.S
1914 +++ b/arch/arm/mach-omap2/sram243x.S
1915 @@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
1916  prcm_mask_val:
1917         .word 0xFFFF3FFC
1918  omap243x_sdi_timer_32ksynct_cr:
1919 -       .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1920 +       .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1921  ENTRY(omap243x_sram_ddr_init_sz)
1922         .word   . - omap243x_sram_ddr_init
1923
1924 @@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
1925  ddr_prcm_mask_val:
1926         .word 0xFFFF3FFC
1927  omap243x_srs_timer_32ksynct:
1928 -       .word OMAP2_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1929 +       .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
1930
1931  ENTRY(omap243x_sram_reprogram_sdrc_sz)
1932         .word   . - omap243x_sram_reprogram_sdrc
1933 diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
1934 index e2338c0..cd72970 100644
1935 --- a/arch/arm/mach-omap2/timer-gp.c
1936 +++ b/arch/arm/mach-omap2/timer-gp.c
1937 @@ -231,7 +231,8 @@ static void __init omap2_gp_clocksource_init(void)
1938  static void __init omap2_gp_timer_init(void)
1939  {
1940  #ifdef CONFIG_LOCAL_TIMERS
1941 -       twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE);
1942 +       twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
1943 +       BUG_ON(!twd_base);
1944  #endif
1945         omap_dm_timer_init();
1946
1947 diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
1948 new file mode 100644
1949 index 0000000..a29c8ca
1950 --- /dev/null
1951 +++ b/arch/arm/mach-omap2/usb-ehci.c
1952 @@ -0,0 +1,192 @@
1953 +/*
1954 + * linux/arch/arm/mach-omap2/usb-ehci.c
1955 + *
1956 + * This file will contain the board specific details for the
1957 + * Synopsys EHCI host controller on OMAP3430
1958 + *
1959 + * Copyright (C) 2007 Texas Instruments
1960 + * Author: Vikram Pandita <vikram.pandita@ti.com>
1961 + *
1962 + * Generalization by:
1963 + * Felipe Balbi <felipe.balbi@nokia.com>
1964 + *
1965 + * This program is free software; you can redistribute it and/or modify
1966 + * it under the terms of the GNU General Public License version 2 as
1967 + * published by the Free Software Foundation.
1968 + */
1969 +
1970 +#include <linux/types.h>
1971 +#include <linux/errno.h>
1972 +#include <linux/delay.h>
1973 +#include <linux/platform_device.h>
1974 +#include <linux/clk.h>
1975 +#include <asm/io.h>
1976 +#include <mach/mux.h>
1977 +
1978 +#include <mach/hardware.h>
1979 +#include <mach/irqs.h>
1980 +#include <mach/usb.h>
1981 +
1982 +#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
1983 +
1984 +static struct resource ehci_resources[] = {
1985 +       {
1986 +               .start  = OMAP34XX_EHCI_BASE,
1987 +               .end    = OMAP34XX_EHCI_BASE + SZ_1K - 1,
1988 +               .flags  = IORESOURCE_MEM,
1989 +       },
1990 +       {
1991 +               .start  = OMAP34XX_UHH_CONFIG_BASE,
1992 +               .end    = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1,
1993 +               .flags  = IORESOURCE_MEM,
1994 +       },
1995 +       {
1996 +               .start  = OMAP34XX_USBTLL_BASE,
1997 +               .end    = OMAP34XX_USBTLL_BASE + SZ_4K - 1,
1998 +               .flags  = IORESOURCE_MEM,
1999 +       },
2000 +       {         /* general IRQ */
2001 +               .start   = INT_34XX_EHCI_IRQ,
2002 +               .flags   = IORESOURCE_IRQ,
2003 +       }
2004 +};
2005 +
2006 +static u64 ehci_dmamask = ~(u32)0;
2007 +static struct platform_device ehci_device = {
2008 +       .name           = "ehci-omap",
2009 +       .id             = 0,
2010 +       .dev = {
2011 +               .dma_mask               = &ehci_dmamask,
2012 +               .coherent_dma_mask      = 0xffffffff,
2013 +               .platform_data          = NULL,
2014 +       },
2015 +       .num_resources  = ARRAY_SIZE(ehci_resources),
2016 +       .resource       = ehci_resources,
2017 +};
2018 +
2019 +/* MUX settings for EHCI pins */
2020 +/*
2021 + * setup_ehci_io_mux - initialize IO pad mux for USBHOST
2022 + */
2023 +static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
2024 +{
2025 +       switch (port_mode[0]) {
2026 +       case EHCI_HCD_OMAP_MODE_PHY:
2027 +               omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
2028 +               omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
2029 +               omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
2030 +               omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
2031 +               omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
2032 +               omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
2033 +               omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
2034 +               omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
2035 +               omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
2036 +               omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
2037 +               omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
2038 +               omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
2039 +               break;
2040 +       case EHCI_HCD_OMAP_MODE_TLL:
2041 +               omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
2042 +               omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
2043 +               omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
2044 +               omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
2045 +               omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
2046 +               omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
2047 +               omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
2048 +               omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
2049 +               omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
2050 +               omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
2051 +               omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
2052 +               omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
2053 +               break;
2054 +       case EHCI_HCD_OMAP_MODE_UNKNOWN:
2055 +               /* FALLTHROUGH */
2056 +       default:
2057 +               break;
2058 +       }
2059 +
2060 +       switch (port_mode[1]) {
2061 +       case EHCI_HCD_OMAP_MODE_PHY:
2062 +               omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
2063 +               omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
2064 +               omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
2065 +               omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
2066 +               omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
2067 +               omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
2068 +               omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
2069 +               omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
2070 +               omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
2071 +               omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
2072 +               omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
2073 +               omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
2074 +               break;
2075 +       case EHCI_HCD_OMAP_MODE_TLL:
2076 +               omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
2077 +               omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
2078 +               omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
2079 +               omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
2080 +               omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
2081 +               omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
2082 +               omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
2083 +               omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
2084 +               omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
2085 +               omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
2086 +               omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
2087 +               omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
2088 +               break;
2089 +       case EHCI_HCD_OMAP_MODE_UNKNOWN:
2090 +               /* FALLTHROUGH */
2091 +       default:
2092 +               break;
2093 +       }
2094 +
2095 +       switch (port_mode[2]) {
2096 +       case EHCI_HCD_OMAP_MODE_PHY:
2097 +               printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
2098 +               break;
2099 +       case EHCI_HCD_OMAP_MODE_TLL:
2100 +               omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
2101 +               omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
2102 +               omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
2103 +               omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
2104 +               omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
2105 +               omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
2106 +               omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
2107 +               omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
2108 +               omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
2109 +               omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
2110 +               omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
2111 +               omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
2112 +               break;
2113 +       case EHCI_HCD_OMAP_MODE_UNKNOWN:
2114 +               /* FALLTHROUGH */
2115 +       default:
2116 +               break;
2117 +       }
2118 +
2119 +       return;
2120 +}
2121 +
2122 +void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
2123 +{
2124 +       platform_device_add_data(&ehci_device, pdata, sizeof(*pdata));
2125 +
2126 +       /* Setup Pin IO MUX for EHCI */
2127 +       if (cpu_is_omap34xx())
2128 +               setup_ehci_io_mux(pdata->port_mode);
2129 +
2130 +       if (platform_device_register(&ehci_device) < 0) {
2131 +               printk(KERN_ERR "Unable to register HS-USB (EHCI) device\n");
2132 +               return;
2133 +       }
2134 +}
2135 +
2136 +#else
2137 +
2138 +void __init usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata)
2139 +
2140 +{
2141 +}
2142 +
2143 +#endif /* CONFIG_USB_EHCI_HCD */
2144 +
2145 diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
2146 index 3a4768d..1aa58d2 100644
2147 --- a/arch/arm/plat-omap/common.c
2148 +++ b/arch/arm/plat-omap/common.c
2149 @@ -224,12 +224,12 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
2150
2151  static struct omap_globals omap242x_globals = {
2152         .class  = OMAP242X_CLASS,
2153 -       .tap    = OMAP2_IO_ADDRESS(0x48014000),
2154 -       .sdrc   = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
2155 -       .sms    = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
2156 -       .ctrl   = OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
2157 -       .prm    = OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
2158 -       .cm     = OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
2159 +       .tap    = OMAP2_L4_IO_ADDRESS(0x48014000),
2160 +       .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
2161 +       .sms    = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
2162 +       .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE),
2163 +       .prm    = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
2164 +       .cm     = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
2165  };
2166
2167  void __init omap2_set_globals_242x(void)
2168 @@ -242,12 +242,12 @@ void __init omap2_set_globals_242x(void)
2169
2170  static struct omap_globals omap243x_globals = {
2171         .class  = OMAP243X_CLASS,
2172 -       .tap    = OMAP2_IO_ADDRESS(0x4900a000),
2173 -       .sdrc   = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
2174 -       .sms    = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
2175 -       .ctrl   = OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
2176 -       .prm    = OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
2177 -       .cm     = OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
2178 +       .tap    = OMAP2_L4_IO_ADDRESS(0x4900a000),
2179 +       .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
2180 +       .sms    = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
2181 +       .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
2182 +       .prm    = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
2183 +       .cm     = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
2184  };
2185
2186  void __init omap2_set_globals_243x(void)
2187 @@ -260,12 +260,12 @@ void __init omap2_set_globals_243x(void)
2188
2189  static struct omap_globals omap343x_globals = {
2190         .class  = OMAP343X_CLASS,
2191 -       .tap    = OMAP2_IO_ADDRESS(0x4830A000),
2192 -       .sdrc   = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
2193 -       .sms    = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
2194 -       .ctrl   = OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
2195 -       .prm    = OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
2196 -       .cm     = OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
2197 +       .tap    = OMAP2_L4_IO_ADDRESS(0x4830A000),
2198 +       .sdrc   = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
2199 +       .sms    = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
2200 +       .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
2201 +       .prm    = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
2202 +       .cm     = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
2203  };
2204
2205  void __init omap2_set_globals_343x(void)
2206 @@ -277,10 +277,10 @@ void __init omap2_set_globals_343x(void)
2207  #if defined(CONFIG_ARCH_OMAP4)
2208  static struct omap_globals omap4_globals = {
2209         .class  = OMAP443X_CLASS,
2210 -       .tap    = OMAP2_IO_ADDRESS(0x4830a000),
2211 -       .ctrl   = OMAP2_IO_ADDRESS(OMAP443X_CTRL_BASE),
2212 -       .prm    = OMAP2_IO_ADDRESS(OMAP4430_PRM_BASE),
2213 -       .cm     = OMAP2_IO_ADDRESS(OMAP4430_CM_BASE),
2214 +       .tap    = OMAP2_L4_IO_ADDRESS(0x4830a000),
2215 +       .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
2216 +       .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
2217 +       .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
2218  };
2219
2220  void __init omap2_set_globals_443x(void)
2221 diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
2222 index a64b692..d2f5475 100644
2223 --- a/arch/arm/plat-omap/devices.c
2224 +++ b/arch/arm/plat-omap/devices.c
2225 @@ -113,17 +113,17 @@ static void omap_init_kp(void)
2226                 omap_cfg_reg(E19_1610_KBR4);
2227                 omap_cfg_reg(N19_1610_KBR5);
2228         } else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
2229 -               omap_cfg_reg(E2_730_KBR0);
2230 -               omap_cfg_reg(J7_730_KBR1);
2231 -               omap_cfg_reg(E1_730_KBR2);
2232 -               omap_cfg_reg(F3_730_KBR3);
2233 -               omap_cfg_reg(D2_730_KBR4);
2234 -
2235 -               omap_cfg_reg(C2_730_KBC0);
2236 -               omap_cfg_reg(D3_730_KBC1);
2237 -               omap_cfg_reg(E4_730_KBC2);
2238 -               omap_cfg_reg(F4_730_KBC3);
2239 -               omap_cfg_reg(E3_730_KBC4);
2240 +               omap_cfg_reg(E2_7XX_KBR0);
2241 +               omap_cfg_reg(J7_7XX_KBR1);
2242 +               omap_cfg_reg(E1_7XX_KBR2);
2243 +               omap_cfg_reg(F3_7XX_KBR3);
2244 +               omap_cfg_reg(D2_7XX_KBR4);
2245 +
2246 +               omap_cfg_reg(C2_7XX_KBC0);
2247 +               omap_cfg_reg(D3_7XX_KBC1);
2248 +               omap_cfg_reg(E4_7XX_KBC2);
2249 +               omap_cfg_reg(F4_7XX_KBC3);
2250 +               omap_cfg_reg(E3_7XX_KBC4);
2251         } else if (machine_is_omap_h4()) {
2252                 omap_cfg_reg(T19_24XX_KBR0);
2253                 omap_cfg_reg(R19_24XX_KBR1);
2254 diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
2255 index 0eb676d..034686d 100644
2256 --- a/arch/arm/plat-omap/dma.c
2257 +++ b/arch/arm/plat-omap/dma.c
2258 @@ -2347,40 +2347,46 @@ EXPORT_SYMBOL(omap_stop_lcd_dma);
2259
2260  static int __init omap_init_dma(void)
2261  {
2262 +       unsigned long base;
2263         int ch, r;
2264
2265         if (cpu_class_is_omap1()) {
2266 -               omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
2267 +               base = OMAP1_DMA_BASE;
2268                 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2269         } else if (cpu_is_omap24xx()) {
2270 -               omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
2271 +               base = OMAP24XX_DMA4_BASE;
2272                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2273         } else if (cpu_is_omap34xx()) {
2274 -               omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
2275 +               base = OMAP34XX_DMA4_BASE;
2276                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2277         } else if (cpu_is_omap44xx()) {
2278 -               omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
2279 +               base = OMAP44XX_DMA4_BASE;
2280                 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2281         } else {
2282                 pr_err("DMA init failed for unsupported omap\n");
2283                 return -ENODEV;
2284         }
2285
2286 +       omap_dma_base = ioremap(base, SZ_4K);
2287 +       BUG_ON(!omap_dma_base);
2288 +
2289         if (cpu_class_is_omap2() && omap_dma_reserve_channels
2290                         && (omap_dma_reserve_channels <= dma_lch_count))
2291                 dma_lch_count = omap_dma_reserve_channels;
2292
2293         dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2294                                 GFP_KERNEL);
2295 -       if (!dma_chan)
2296 -               return -ENOMEM;
2297 +       if (!dma_chan) {
2298 +               r = -ENOMEM;
2299 +               goto out_unmap;
2300 +       }
2301
2302         if (cpu_class_is_omap2()) {
2303                 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2304                                                 dma_lch_count, GFP_KERNEL);
2305                 if (!dma_linked_lch) {
2306 -                       kfree(dma_chan);
2307 -                       return -ENOMEM;
2308 +                       r = -ENOMEM;
2309 +                       goto out_free;
2310                 }
2311         }
2312
2313 @@ -2454,7 +2460,7 @@ static int __init omap_init_dma(void)
2314                                 for (i = 0; i < ch; i++)
2315                                         free_irq(omap1_dma_irq[i],
2316                                                  (void *) (i + 1));
2317 -                               return r;
2318 +                               goto out_free;
2319                         }
2320                 }
2321         }
2322 @@ -2496,11 +2502,19 @@ static int __init omap_init_dma(void)
2323                                "(error %d)\n", r);
2324                         for (i = 0; i < dma_chan_count; i++)
2325                                 free_irq(omap1_dma_irq[i], (void *) (i + 1));
2326 -                       return r;
2327 +                       goto out_free;
2328                 }
2329         }
2330
2331         return 0;
2332 +
2333 +out_free:
2334 +       kfree(dma_chan);
2335 +
2336 +out_unmap:
2337 +       iounmap(omap_dma_base);
2338 +
2339 +       return r;
2340  }
2341
2342  arch_initcall(omap_init_dma);
2343 diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
2344 index d325b54..e4e848e 100644
2345 --- a/arch/arm/plat-omap/dmtimer.c
2346 +++ b/arch/arm/plat-omap/dmtimer.c
2347 @@ -742,16 +742,17 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
2348  int __init omap_dm_timer_init(void)
2349  {
2350         struct omap_dm_timer *timer;
2351 -       int i;
2352 +       int i, map_size = SZ_8K;        /* Module 4KB + L4 4KB except on omap1 */
2353
2354         if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
2355                 return -ENODEV;
2356
2357         spin_lock_init(&dm_timer_lock);
2358
2359 -       if (cpu_class_is_omap1())
2360 +       if (cpu_class_is_omap1()) {
2361                 dm_timers = omap1_dm_timers;
2362 -       else if (cpu_is_omap24xx()) {
2363 +               map_size = SZ_2K;
2364 +       } else if (cpu_is_omap24xx()) {
2365                 dm_timers = omap2_dm_timers;
2366                 dm_source_names = omap2_dm_source_names;
2367                 dm_source_clocks = omap2_dm_source_clocks;
2368 @@ -774,10 +775,11 @@ int __init omap_dm_timer_init(void)
2369
2370         for (i = 0; i < dm_timer_count; i++) {
2371                 timer = &dm_timers[i];
2372 -               if (cpu_class_is_omap1())
2373 -                       timer->io_base = OMAP1_IO_ADDRESS(timer->phys_base);
2374 -               else
2375 -                       timer->io_base = OMAP2_IO_ADDRESS(timer->phys_base);
2376 +
2377 +               /* Static mapping, never released */
2378 +               timer->io_base = ioremap(timer->phys_base, map_size);
2379 +               BUG_ON(!timer->io_base);
2380 +
2381  #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
2382                                         defined(CONFIG_ARCH_OMAP4)
2383                 if (cpu_class_is_omap2()) {
2384 diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
2385 index 71ebd7f..14c3506 100644
2386 --- a/arch/arm/plat-omap/gpio.c
2387 +++ b/arch/arm/plat-omap/gpio.c
2388 @@ -31,7 +31,7 @@
2389  /*
2390   * OMAP1510 GPIO registers
2391   */
2392 -#define OMAP1510_GPIO_BASE             OMAP1_IO_ADDRESS(0xfffce000)
2393 +#define OMAP1510_GPIO_BASE             0xfffce000
2394  #define OMAP1510_GPIO_DATA_INPUT       0x00
2395  #define OMAP1510_GPIO_DATA_OUTPUT      0x04
2396  #define OMAP1510_GPIO_DIR_CONTROL      0x08
2397 @@ -45,10 +45,10 @@
2398  /*
2399   * OMAP1610 specific GPIO registers
2400   */
2401 -#define OMAP1610_GPIO1_BASE            OMAP1_IO_ADDRESS(0xfffbe400)
2402 -#define OMAP1610_GPIO2_BASE            OMAP1_IO_ADDRESS(0xfffbec00)
2403 -#define OMAP1610_GPIO3_BASE            OMAP1_IO_ADDRESS(0xfffbb400)
2404 -#define OMAP1610_GPIO4_BASE            OMAP1_IO_ADDRESS(0xfffbbc00)
2405 +#define OMAP1610_GPIO1_BASE            0xfffbe400
2406 +#define OMAP1610_GPIO2_BASE            0xfffbec00
2407 +#define OMAP1610_GPIO3_BASE            0xfffbb400
2408 +#define OMAP1610_GPIO4_BASE            0xfffbbc00
2409  #define OMAP1610_GPIO_REVISION         0x0000
2410  #define OMAP1610_GPIO_SYSCONFIG                0x0010
2411  #define OMAP1610_GPIO_SYSSTATUS                0x0014
2412 @@ -68,52 +68,36 @@
2413  #define OMAP1610_GPIO_SET_DATAOUT      0x00f0
2414
2415  /*
2416 - * OMAP730 specific GPIO registers
2417 + * OMAP7XX specific GPIO registers
2418   */
2419 -#define OMAP730_GPIO1_BASE             OMAP1_IO_ADDRESS(0xfffbc000)
2420 -#define OMAP730_GPIO2_BASE             OMAP1_IO_ADDRESS(0xfffbc800)
2421 -#define OMAP730_GPIO3_BASE             OMAP1_IO_ADDRESS(0xfffbd000)
2422 -#define OMAP730_GPIO4_BASE             OMAP1_IO_ADDRESS(0xfffbd800)
2423 -#define OMAP730_GPIO5_BASE             OMAP1_IO_ADDRESS(0xfffbe000)
2424 -#define OMAP730_GPIO6_BASE             OMAP1_IO_ADDRESS(0xfffbe800)
2425 -#define OMAP730_GPIO_DATA_INPUT                0x00
2426 -#define OMAP730_GPIO_DATA_OUTPUT       0x04
2427 -#define OMAP730_GPIO_DIR_CONTROL       0x08
2428 -#define OMAP730_GPIO_INT_CONTROL       0x0c
2429 -#define OMAP730_GPIO_INT_MASK          0x10
2430 -#define OMAP730_GPIO_INT_STATUS                0x14
2431 -
2432 -/*
2433 - * OMAP850 specific GPIO registers
2434 - */
2435 -#define OMAP850_GPIO1_BASE             OMAP1_IO_ADDRESS(0xfffbc000)
2436 -#define OMAP850_GPIO2_BASE             OMAP1_IO_ADDRESS(0xfffbc800)
2437 -#define OMAP850_GPIO3_BASE             OMAP1_IO_ADDRESS(0xfffbd000)
2438 -#define OMAP850_GPIO4_BASE             OMAP1_IO_ADDRESS(0xfffbd800)
2439 -#define OMAP850_GPIO5_BASE             OMAP1_IO_ADDRESS(0xfffbe000)
2440 -#define OMAP850_GPIO6_BASE             OMAP1_IO_ADDRESS(0xfffbe800)
2441 -#define OMAP850_GPIO_DATA_INPUT                0x00
2442 -#define OMAP850_GPIO_DATA_OUTPUT       0x04
2443 -#define OMAP850_GPIO_DIR_CONTROL       0x08
2444 -#define OMAP850_GPIO_INT_CONTROL       0x0c
2445 -#define OMAP850_GPIO_INT_MASK          0x10
2446 -#define OMAP850_GPIO_INT_STATUS                0x14
2447 -
2448 -#define OMAP1_MPUIO_VBASE              OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
2449 +#define OMAP7XX_GPIO1_BASE             0xfffbc000
2450 +#define OMAP7XX_GPIO2_BASE             0xfffbc800
2451 +#define OMAP7XX_GPIO3_BASE             0xfffbd000
2452 +#define OMAP7XX_GPIO4_BASE             0xfffbd800
2453 +#define OMAP7XX_GPIO5_BASE             0xfffbe000
2454 +#define OMAP7XX_GPIO6_BASE             0xfffbe800
2455 +#define OMAP7XX_GPIO_DATA_INPUT                0x00
2456 +#define OMAP7XX_GPIO_DATA_OUTPUT       0x04
2457 +#define OMAP7XX_GPIO_DIR_CONTROL       0x08
2458 +#define OMAP7XX_GPIO_INT_CONTROL       0x0c
2459 +#define OMAP7XX_GPIO_INT_MASK          0x10
2460 +#define OMAP7XX_GPIO_INT_STATUS                0x14
2461 +
2462 +#define OMAP1_MPUIO_VBASE              OMAP1_MPUIO_BASE
2463
2464  /*
2465   * omap24xx specific GPIO registers
2466   */
2467 -#define OMAP242X_GPIO1_BASE            OMAP2_IO_ADDRESS(0x48018000)
2468 -#define OMAP242X_GPIO2_BASE            OMAP2_IO_ADDRESS(0x4801a000)
2469 -#define OMAP242X_GPIO3_BASE            OMAP2_IO_ADDRESS(0x4801c000)
2470 -#define OMAP242X_GPIO4_BASE            OMAP2_IO_ADDRESS(0x4801e000)
2471 +#define OMAP242X_GPIO1_BASE            0x48018000
2472 +#define OMAP242X_GPIO2_BASE            0x4801a000
2473 +#define OMAP242X_GPIO3_BASE            0x4801c000
2474 +#define OMAP242X_GPIO4_BASE            0x4801e000
2475
2476 -#define OMAP243X_GPIO1_BASE            OMAP2_IO_ADDRESS(0x4900C000)
2477 -#define OMAP243X_GPIO2_BASE            OMAP2_IO_ADDRESS(0x4900E000)
2478 -#define OMAP243X_GPIO3_BASE            OMAP2_IO_ADDRESS(0x49010000)
2479 -#define OMAP243X_GPIO4_BASE            OMAP2_IO_ADDRESS(0x49012000)
2480 -#define OMAP243X_GPIO5_BASE            OMAP2_IO_ADDRESS(0x480B6000)
2481 +#define OMAP243X_GPIO1_BASE            0x4900C000
2482 +#define OMAP243X_GPIO2_BASE            0x4900E000
2483 +#define OMAP243X_GPIO3_BASE            0x49010000
2484 +#define OMAP243X_GPIO4_BASE            0x49012000
2485 +#define OMAP243X_GPIO5_BASE            0x480B6000
2486
2487  #define OMAP24XX_GPIO_REVISION         0x0000
2488  #define OMAP24XX_GPIO_SYSCONFIG                0x0010
2489 @@ -170,24 +154,25 @@
2490   * omap34xx specific GPIO registers
2491   */
2492
2493 -#define OMAP34XX_GPIO1_BASE            OMAP2_IO_ADDRESS(0x48310000)
2494 -#define OMAP34XX_GPIO2_BASE            OMAP2_IO_ADDRESS(0x49050000)
2495 -#define OMAP34XX_GPIO3_BASE            OMAP2_IO_ADDRESS(0x49052000)
2496 -#define OMAP34XX_GPIO4_BASE            OMAP2_IO_ADDRESS(0x49054000)
2497 -#define OMAP34XX_GPIO5_BASE            OMAP2_IO_ADDRESS(0x49056000)
2498 -#define OMAP34XX_GPIO6_BASE            OMAP2_IO_ADDRESS(0x49058000)
2499 +#define OMAP34XX_GPIO1_BASE            0x48310000
2500 +#define OMAP34XX_GPIO2_BASE            0x49050000
2501 +#define OMAP34XX_GPIO3_BASE            0x49052000
2502 +#define OMAP34XX_GPIO4_BASE            0x49054000
2503 +#define OMAP34XX_GPIO5_BASE            0x49056000
2504 +#define OMAP34XX_GPIO6_BASE            0x49058000
2505
2506  /*
2507   * OMAP44XX  specific GPIO registers
2508   */
2509 -#define OMAP44XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4a310000)
2510 -#define OMAP44XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x48055000)
2511 -#define OMAP44XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x48057000)
2512 -#define OMAP44XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x48059000)
2513 -#define OMAP44XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x4805B000)
2514 -#define OMAP44XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x4805D000)
2515 +#define OMAP44XX_GPIO1_BASE             0x4a310000
2516 +#define OMAP44XX_GPIO2_BASE             0x48055000
2517 +#define OMAP44XX_GPIO3_BASE             0x48057000
2518 +#define OMAP44XX_GPIO4_BASE             0x48059000
2519 +#define OMAP44XX_GPIO5_BASE             0x4805B000
2520 +#define OMAP44XX_GPIO6_BASE             0x4805D000
2521
2522  struct gpio_bank {
2523 +       unsigned long pbase;
2524         void __iomem *base;
2525         u16 irq;
2526         u16 virtual_irq_start;
2527 @@ -215,96 +200,111 @@ struct gpio_bank {
2528  #define METHOD_MPUIO           0
2529  #define METHOD_GPIO_1510       1
2530  #define METHOD_GPIO_1610       2
2531 -#define METHOD_GPIO_730                3
2532 -#define METHOD_GPIO_850                4
2533 +#define METHOD_GPIO_7XX                3
2534  #define METHOD_GPIO_24XX       5
2535
2536  #ifdef CONFIG_ARCH_OMAP16XX
2537  static struct gpio_bank gpio_bank_1610[5] = {
2538 -       { OMAP1_MPUIO_VBASE,    INT_MPUIO,          IH_MPUIO_BASE,     METHOD_MPUIO},
2539 -       { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
2540 -       { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
2541 -       { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
2542 -       { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
2543 +       { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE,
2544 +               METHOD_MPUIO },
2545 +       { OMAP1610_GPIO1_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE,
2546 +               METHOD_GPIO_1610 },
2547 +       { OMAP1610_GPIO2_BASE, 0, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
2548 +               METHOD_GPIO_1610 },
2549 +       { OMAP1610_GPIO3_BASE, 0, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
2550 +               METHOD_GPIO_1610 },
2551 +       { OMAP1610_GPIO4_BASE, 0, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
2552 +               METHOD_GPIO_1610 },
2553  };
2554  #endif
2555
2556  #ifdef CONFIG_ARCH_OMAP15XX
2557  static struct gpio_bank gpio_bank_1510[2] = {
2558 -       { OMAP1_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
2559 -       { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
2560 -};
2561 -#endif
2562 -
2563 -#ifdef CONFIG_ARCH_OMAP730
2564 -static struct gpio_bank gpio_bank_730[7] = {
2565 -       { OMAP1_MPUIO_VBASE,    INT_730_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
2566 -       { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
2567 -       { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
2568 -       { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
2569 -       { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
2570 -       { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
2571 -       { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
2572 +       { OMAP1_MPUIO_VBASE, 0, INT_MPUIO, IH_MPUIO_BASE,
2573 +               METHOD_MPUIO },
2574 +       { OMAP1510_GPIO_BASE, 0, INT_GPIO_BANK1, IH_GPIO_BASE,
2575 +               METHOD_GPIO_1510 }
2576  };
2577  #endif
2578
2579 -#ifdef CONFIG_ARCH_OMAP850
2580 -static struct gpio_bank gpio_bank_850[7] = {
2581 -       { OMAP1_MPUIO_VBASE,     INT_850_MPUIO,     IH_MPUIO_BASE,      METHOD_MPUIO },
2582 -       { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
2583 -       { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
2584 -       { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
2585 -       { OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_850 },
2586 -       { OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
2587 -       { OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
2588 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2589 +static struct gpio_bank gpio_bank_7xx[7] = {
2590 +       { OMAP1_MPUIO_VBASE, 0, INT_7XX_MPUIO, IH_MPUIO_BASE,
2591 +               METHOD_MPUIO },
2592 +       { OMAP7XX_GPIO1_BASE, 0, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
2593 +               METHOD_GPIO_7XX },
2594 +       { OMAP7XX_GPIO2_BASE, 0, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2595 +               METHOD_GPIO_7XX },
2596 +       { OMAP7XX_GPIO3_BASE, 0, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2597 +               METHOD_GPIO_7XX },
2598 +       { OMAP7XX_GPIO4_BASE, 0, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
2599 +               METHOD_GPIO_7XX },
2600 +       { OMAP7XX_GPIO5_BASE, 0, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
2601 +               METHOD_GPIO_7XX },
2602 +       { OMAP7XX_GPIO6_BASE, 0, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
2603 +               METHOD_GPIO_7XX },
2604  };
2605  #endif
2606
2607 -
2608  #ifdef CONFIG_ARCH_OMAP24XX
2609
2610  static struct gpio_bank gpio_bank_242x[4] = {
2611 -       { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
2612 -       { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
2613 -       { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
2614 -       { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
2615 +       { OMAP242X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
2616 +               METHOD_GPIO_24XX },
2617 +       { OMAP242X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2618 +               METHOD_GPIO_24XX },
2619 +       { OMAP242X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2620 +               METHOD_GPIO_24XX },
2621 +       { OMAP242X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2622 +               METHOD_GPIO_24XX },
2623  };
2624
2625  static struct gpio_bank gpio_bank_243x[5] = {
2626 -       { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
2627 -       { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
2628 -       { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
2629 -       { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
2630 -       { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
2631 +       { OMAP243X_GPIO1_BASE, 0, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
2632 +               METHOD_GPIO_24XX },
2633 +       { OMAP243X_GPIO2_BASE, 0, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2634 +               METHOD_GPIO_24XX },
2635 +       { OMAP243X_GPIO3_BASE, 0, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2636 +               METHOD_GPIO_24XX },
2637 +       { OMAP243X_GPIO4_BASE, 0, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2638 +               METHOD_GPIO_24XX },
2639 +       { OMAP243X_GPIO5_BASE, 0, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2640 +               METHOD_GPIO_24XX },
2641  };
2642
2643  #endif
2644
2645  #ifdef CONFIG_ARCH_OMAP34XX
2646  static struct gpio_bank gpio_bank_34xx[6] = {
2647 -       { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
2648 -       { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
2649 -       { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
2650 -       { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
2651 -       { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
2652 -       { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
2653 +       { OMAP34XX_GPIO1_BASE, 0, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
2654 +               METHOD_GPIO_24XX },
2655 +       { OMAP34XX_GPIO2_BASE, 0, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2656 +               METHOD_GPIO_24XX },
2657 +       { OMAP34XX_GPIO3_BASE, 0, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2658 +               METHOD_GPIO_24XX },
2659 +       { OMAP34XX_GPIO4_BASE, 0, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2660 +               METHOD_GPIO_24XX },
2661 +       { OMAP34XX_GPIO5_BASE, 0, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2662 +               METHOD_GPIO_24XX },
2663 +       { OMAP34XX_GPIO6_BASE, 0, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
2664 +               METHOD_GPIO_24XX },
2665  };
2666
2667  #endif
2668
2669  #ifdef CONFIG_ARCH_OMAP4
2670  static struct gpio_bank gpio_bank_44xx[6] = {
2671 -       { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,       \
2672 +       { OMAP44XX_GPIO1_BASE, 0, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
2673                 METHOD_GPIO_24XX },
2674 -       { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,  \
2675 +       { OMAP44XX_GPIO2_BASE, 0, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
2676                 METHOD_GPIO_24XX },
2677 -       { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,  \
2678 +       { OMAP44XX_GPIO3_BASE, 0, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
2679                 METHOD_GPIO_24XX },
2680 -       { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,  \
2681 +       { OMAP44XX_GPIO4_BASE, 0, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
2682                 METHOD_GPIO_24XX },
2683 -       { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
2684 +       { OMAP44XX_GPIO5_BASE, 0, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
2685                 METHOD_GPIO_24XX },
2686 -       { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
2687 +       { OMAP44XX_GPIO6_BASE, 0, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
2688                 METHOD_GPIO_24XX },
2689  };
2690
2691 @@ -373,7 +373,7 @@ static inline int gpio_valid(int gpio)
2692
2693  static int check_gpio(int gpio)
2694  {
2695 -       if (unlikely(gpio_valid(gpio)) < 0) {
2696 +       if (unlikely(gpio_valid(gpio) < 0)) {
2697                 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
2698                 dump_stack();
2699                 return -1;
2700 @@ -402,14 +402,9 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
2701                 reg += OMAP1610_GPIO_DIRECTION;
2702                 break;
2703  #endif
2704 -#ifdef CONFIG_ARCH_OMAP730
2705 -       case METHOD_GPIO_730:
2706 -               reg += OMAP730_GPIO_DIR_CONTROL;
2707 -               break;
2708 -#endif
2709 -#ifdef CONFIG_ARCH_OMAP850
2710 -       case METHOD_GPIO_850:
2711 -               reg += OMAP850_GPIO_DIR_CONTROL;
2712 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2713 +       case METHOD_GPIO_7XX:
2714 +               reg += OMAP7XX_GPIO_DIR_CONTROL;
2715                 break;
2716  #endif
2717  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2718 @@ -469,19 +464,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
2719                 l = 1 << gpio;
2720                 break;
2721  #endif
2722 -#ifdef CONFIG_ARCH_OMAP730
2723 -       case METHOD_GPIO_730:
2724 -               reg += OMAP730_GPIO_DATA_OUTPUT;
2725 -               l = __raw_readl(reg);
2726 -               if (enable)
2727 -                       l |= 1 << gpio;
2728 -               else
2729 -                       l &= ~(1 << gpio);
2730 -               break;
2731 -#endif
2732 -#ifdef CONFIG_ARCH_OMAP850
2733 -       case METHOD_GPIO_850:
2734 -               reg += OMAP850_GPIO_DATA_OUTPUT;
2735 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2736 +       case METHOD_GPIO_7XX:
2737 +               reg += OMAP7XX_GPIO_DATA_OUTPUT;
2738                 l = __raw_readl(reg);
2739                 if (enable)
2740                         l |= 1 << gpio;
2741 @@ -537,14 +522,9 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
2742                 reg += OMAP1610_GPIO_DATAIN;
2743                 break;
2744  #endif
2745 -#ifdef CONFIG_ARCH_OMAP730
2746 -       case METHOD_GPIO_730:
2747 -               reg += OMAP730_GPIO_DATA_INPUT;
2748 -               break;
2749 -#endif
2750 -#ifdef CONFIG_ARCH_OMAP850
2751 -       case METHOD_GPIO_850:
2752 -               reg += OMAP850_GPIO_DATA_INPUT;
2753 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2754 +       case METHOD_GPIO_7XX:
2755 +               reg += OMAP7XX_GPIO_DATA_INPUT;
2756                 break;
2757  #endif
2758  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2759 @@ -588,14 +568,9 @@ static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
2760                 reg += OMAP1610_GPIO_DATAOUT;
2761                 break;
2762  #endif
2763 -#ifdef CONFIG_ARCH_OMAP730
2764 -       case METHOD_GPIO_730:
2765 -               reg += OMAP730_GPIO_DATA_OUTPUT;
2766 -               break;
2767 -#endif
2768 -#ifdef CONFIG_ARCH_OMAP850
2769 -       case METHOD_GPIO_850:
2770 -               reg += OMAP850_GPIO_DATA_OUTPUT;
2771 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2772 +       case METHOD_GPIO_7XX:
2773 +               reg += OMAP7XX_GPIO_DATA_OUTPUT;
2774                 break;
2775  #endif
2776  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
2777 @@ -797,21 +772,9 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
2778                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
2779                 break;
2780  #endif
2781 -#ifdef CONFIG_ARCH_OMAP730
2782 -       case METHOD_GPIO_730:
2783 -               reg += OMAP730_GPIO_INT_CONTROL;
2784 -               l = __raw_readl(reg);
2785 -               if (trigger & IRQ_TYPE_EDGE_RISING)
2786 -                       l |= 1 << gpio;
2787 -               else if (trigger & IRQ_TYPE_EDGE_FALLING)
2788 -                       l &= ~(1 << gpio);
2789 -               else
2790 -                       goto bad;
2791 -               break;
2792 -#endif
2793 -#ifdef CONFIG_ARCH_OMAP850
2794 -       case METHOD_GPIO_850:
2795 -               reg += OMAP850_GPIO_INT_CONTROL;
2796 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2797 +       case METHOD_GPIO_7XX:
2798 +               reg += OMAP7XX_GPIO_INT_CONTROL;
2799                 l = __raw_readl(reg);
2800                 if (trigger & IRQ_TYPE_EDGE_RISING)
2801                         l |= 1 << gpio;
2802 @@ -897,14 +860,9 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
2803                 reg += OMAP1610_GPIO_IRQSTATUS1;
2804                 break;
2805  #endif
2806 -#ifdef CONFIG_ARCH_OMAP730
2807 -       case METHOD_GPIO_730:
2808 -               reg += OMAP730_GPIO_INT_STATUS;
2809 -               break;
2810 -#endif
2811 -#ifdef CONFIG_ARCH_OMAP850
2812 -       case METHOD_GPIO_850:
2813 -               reg += OMAP850_GPIO_INT_STATUS;
2814 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2815 +       case METHOD_GPIO_7XX:
2816 +               reg += OMAP7XX_GPIO_INT_STATUS;
2817                 break;
2818  #endif
2819  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2820 @@ -971,16 +929,9 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
2821                 mask = 0xffff;
2822                 break;
2823  #endif
2824 -#ifdef CONFIG_ARCH_OMAP730
2825 -       case METHOD_GPIO_730:
2826 -               reg += OMAP730_GPIO_INT_MASK;
2827 -               mask = 0xffffffff;
2828 -               inv = 1;
2829 -               break;
2830 -#endif
2831 -#ifdef CONFIG_ARCH_OMAP850
2832 -       case METHOD_GPIO_850:
2833 -               reg += OMAP850_GPIO_INT_MASK;
2834 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2835 +       case METHOD_GPIO_7XX:
2836 +               reg += OMAP7XX_GPIO_INT_MASK;
2837                 mask = 0xffffffff;
2838                 inv = 1;
2839                 break;
2840 @@ -1044,19 +995,9 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
2841                 l = gpio_mask;
2842                 break;
2843  #endif
2844 -#ifdef CONFIG_ARCH_OMAP730
2845 -       case METHOD_GPIO_730:
2846 -               reg += OMAP730_GPIO_INT_MASK;
2847 -               l = __raw_readl(reg);
2848 -               if (enable)
2849 -                       l &= ~(gpio_mask);
2850 -               else
2851 -                       l |= gpio_mask;
2852 -               break;
2853 -#endif
2854 -#ifdef CONFIG_ARCH_OMAP850
2855 -       case METHOD_GPIO_850:
2856 -               reg += OMAP850_GPIO_INT_MASK;
2857 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2858 +       case METHOD_GPIO_7XX:
2859 +               reg += OMAP7XX_GPIO_INT_MASK;
2860                 l = __raw_readl(reg);
2861                 if (enable)
2862                         l &= ~(gpio_mask);
2863 @@ -1249,13 +1190,9 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
2864         if (bank->method == METHOD_GPIO_1610)
2865                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
2866  #endif
2867 -#ifdef CONFIG_ARCH_OMAP730
2868 -       if (bank->method == METHOD_GPIO_730)
2869 -               isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
2870 -#endif
2871 -#ifdef CONFIG_ARCH_OMAP850
2872 -       if (bank->method == METHOD_GPIO_850)
2873 -               isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
2874 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2875 +       if (bank->method == METHOD_GPIO_7XX)
2876 +               isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
2877  #endif
2878  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2879         if (bank->method == METHOD_GPIO_24XX)
2880 @@ -1524,11 +1461,8 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
2881         case METHOD_GPIO_1610:
2882                 reg += OMAP1610_GPIO_DIRECTION;
2883                 break;
2884 -       case METHOD_GPIO_730:
2885 -               reg += OMAP730_GPIO_DIR_CONTROL;
2886 -               break;
2887 -       case METHOD_GPIO_850:
2888 -               reg += OMAP850_GPIO_DIR_CONTROL;
2889 +       case METHOD_GPIO_7XX:
2890 +               reg += OMAP7XX_GPIO_DIR_CONTROL;
2891                 break;
2892         case METHOD_GPIO_24XX:
2893                 reg += OMAP24XX_GPIO_OE;
2894 @@ -1607,6 +1541,23 @@ static struct clk * gpio5_fck;
2895  static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
2896  #endif
2897
2898 +static void __init omap_gpio_show_rev(void)
2899 +{
2900 +       u32 rev;
2901 +
2902 +       if (cpu_is_omap16xx())
2903 +               rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
2904 +       else if (cpu_is_omap24xx() || cpu_is_omap34xx())
2905 +               rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2906 +       else if (cpu_is_omap44xx())
2907 +               rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
2908 +       else
2909 +               return;
2910 +
2911 +       printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
2912 +               (rev >> 4) & 0x0f, rev & 0x0f);
2913 +}
2914 +
2915  /* This lock class tells lockdep that GPIO irqs are in a different
2916   * category than their parents, so it won't report false recursion.
2917   */
2918 @@ -1617,6 +1568,7 @@ static int __init _omap_gpio_init(void)
2919         int i;
2920         int gpio = 0;
2921         struct gpio_bank *bank;
2922 +       int bank_size = SZ_8K;  /* Module 4KB + L4 4KB except on omap1 */
2923         char clk_name[11];
2924
2925         initialized = 1;
2926 @@ -1679,77 +1631,45 @@ static int __init _omap_gpio_init(void)
2927
2928  #ifdef CONFIG_ARCH_OMAP15XX
2929         if (cpu_is_omap15xx()) {
2930 -               printk(KERN_INFO "OMAP1510 GPIO hardware\n");
2931                 gpio_bank_count = 2;
2932                 gpio_bank = gpio_bank_1510;
2933 +               bank_size = SZ_2K;
2934         }
2935  #endif
2936  #if defined(CONFIG_ARCH_OMAP16XX)
2937         if (cpu_is_omap16xx()) {
2938 -               u32 rev;
2939 -
2940                 gpio_bank_count = 5;
2941                 gpio_bank = gpio_bank_1610;
2942 -               rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
2943 -               printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
2944 -                      (rev >> 4) & 0x0f, rev & 0x0f);
2945 +               bank_size = SZ_2K;
2946         }
2947  #endif
2948 -#ifdef CONFIG_ARCH_OMAP730
2949 -       if (cpu_is_omap730()) {
2950 -               printk(KERN_INFO "OMAP730 GPIO hardware\n");
2951 -               gpio_bank_count = 7;
2952 -               gpio_bank = gpio_bank_730;
2953 -       }
2954 -#endif
2955 -#ifdef CONFIG_ARCH_OMAP850
2956 -       if (cpu_is_omap850()) {
2957 -               printk(KERN_INFO "OMAP850 GPIO hardware\n");
2958 +#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
2959 +       if (cpu_is_omap7xx()) {
2960                 gpio_bank_count = 7;
2961 -               gpio_bank = gpio_bank_850;
2962 +               gpio_bank = gpio_bank_7xx;
2963 +               bank_size = SZ_2K;
2964         }
2965  #endif
2966 -
2967  #ifdef CONFIG_ARCH_OMAP24XX
2968         if (cpu_is_omap242x()) {
2969 -               int rev;
2970 -
2971                 gpio_bank_count = 4;
2972                 gpio_bank = gpio_bank_242x;
2973 -               rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2974 -               printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
2975 -                       (rev >> 4) & 0x0f, rev & 0x0f);
2976         }
2977         if (cpu_is_omap243x()) {
2978 -               int rev;
2979 -
2980                 gpio_bank_count = 5;
2981                 gpio_bank = gpio_bank_243x;
2982 -               rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2983 -               printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
2984 -                       (rev >> 4) & 0x0f, rev & 0x0f);
2985         }
2986  #endif
2987  #ifdef CONFIG_ARCH_OMAP34XX
2988         if (cpu_is_omap34xx()) {
2989 -               int rev;
2990 -
2991                 gpio_bank_count = OMAP34XX_NR_GPIOS;
2992                 gpio_bank = gpio_bank_34xx;
2993 -               rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
2994 -               printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
2995 -                       (rev >> 4) & 0x0f, rev & 0x0f);
2996         }
2997  #endif
2998  #ifdef CONFIG_ARCH_OMAP4
2999         if (cpu_is_omap44xx()) {
3000 -               int rev;
3001 -
3002                 gpio_bank_count = OMAP34XX_NR_GPIOS;
3003                 gpio_bank = gpio_bank_44xx;
3004 -               rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
3005 -               printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
3006 -                       (rev >> 4) & 0x0f, rev & 0x0f);
3007         }
3008  #endif
3009         for (i = 0; i < gpio_bank_count; i++) {
3010 @@ -1757,6 +1677,14 @@ static int __init _omap_gpio_init(void)
3011
3012                 bank = &gpio_bank[i];
3013                 spin_lock_init(&bank->lock);
3014 +
3015 +               /* Static mapping, never released */
3016 +               bank->base = ioremap(bank->pbase, bank_size);
3017 +               if (!bank->base) {
3018 +                       printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
3019 +                       continue;
3020 +               }
3021 +
3022                 if (bank_is_mpuio(bank))
3023                         __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
3024                 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
3025 @@ -1768,11 +1696,11 @@ static int __init _omap_gpio_init(void)
3026                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
3027                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
3028                 }
3029 -               if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
3030 -                       __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
3031 -                       __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
3032 +               if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
3033 +                       __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
3034 +                       __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
3035
3036 -                       gpio_count = 32; /* 730 has 32-bit GPIOs */
3037 +                       gpio_count = 32; /* 7xx has 32-bit GPIOs */
3038                 }
3039
3040  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
3041 @@ -1862,6 +1790,8 @@ static int __init _omap_gpio_init(void)
3042         if (cpu_is_omap34xx())
3043                 omap_writel(1 << 0, 0x48306814);
3044
3045 +       omap_gpio_show_rev();
3046 +
3047         return 0;
3048  }
3049
3050 @@ -2160,8 +2090,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
3051
3052                 if (bank_is_mpuio(bank))
3053                         gpio = OMAP_MPUIO(0);
3054 -               else if (cpu_class_is_omap2() || cpu_is_omap730() ||
3055 -                               cpu_is_omap850())
3056 +               else if (cpu_class_is_omap2() || cpu_is_omap7xx())
3057                         bankwidth = 32;
3058
3059                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
3060 diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
3061 index 826d317..fdb6300 100644
3062 --- a/arch/arm/plat-omap/include/mach/control.h
3063 +++ b/arch/arm/plat-omap/include/mach/control.h
3064 @@ -20,15 +20,18 @@
3065
3066  #ifndef __ASSEMBLY__
3067  #define OMAP242X_CTRL_REGADDR(reg)                                     \
3068 -       OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
3069 +               OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
3070  #define OMAP243X_CTRL_REGADDR(reg)                                     \
3071 -       OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
3072 +               OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
3073  #define OMAP343X_CTRL_REGADDR(reg)                                     \
3074 -       OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
3075 +               OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
3076  #else
3077 -#define OMAP242X_CTRL_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
3078 -#define OMAP243X_CTRL_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
3079 -#define OMAP343X_CTRL_REGADDR(reg)     OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
3080 +#define OMAP242X_CTRL_REGADDR(reg)                                     \
3081 +               OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
3082 +#define OMAP243X_CTRL_REGADDR(reg)                                     \
3083 +               OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
3084 +#define OMAP343X_CTRL_REGADDR(reg)                                     \
3085 +               OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
3086  #endif /* __ASSEMBLY__ */
3087
3088  /*
3089 @@ -202,6 +205,40 @@
3090  #define OMAP3_PADCONF_WAKEUPEVENT0     (1 << 15)
3091  #define OMAP3_PADCONF_WAKEUPENABLE0    (1 << 14)
3092
3093 +/*
3094 + * CONTROL OMAP STATUS register to identify OMAP3 features
3095 + */
3096 +#define OMAP3_CONTROL_OMAP_STATUS      0x044c
3097 +
3098 +#define OMAP3_SGX_SHIFT                        13
3099 +#define OMAP3_SGX_MASK                 (3 << OMAP3_SGX_SHIFT)
3100 +#define                FEAT_SGX_FULL           0
3101 +#define                FEAT_SGX_HALF           1
3102 +#define                FEAT_SGX_NONE           2
3103 +
3104 +#define OMAP3_IVA_SHIFT                        12
3105 +#define OMAP3_IVA_MASK                 (1 << OMAP3_SGX_SHIFT)
3106 +#define                FEAT_IVA                0
3107 +#define                FEAT_IVA_NONE           1
3108 +
3109 +#define OMAP3_L2CACHE_SHIFT            10
3110 +#define OMAP3_L2CACHE_MASK             (3 << OMAP3_L2CACHE_SHIFT)
3111 +#define                FEAT_L2CACHE_NONE       0
3112 +#define                FEAT_L2CACHE_64KB       1
3113 +#define                FEAT_L2CACHE_128KB      2
3114 +#define                FEAT_L2CACHE_256KB      3
3115 +
3116 +#define OMAP3_ISP_SHIFT                        5
3117 +#define OMAP3_ISP_MASK                 (1<< OMAP3_ISP_SHIFT)
3118 +#define                FEAT_ISP                0
3119 +#define                FEAT_ISP_NONE           1
3120 +
3121 +#define OMAP3_NEON_SHIFT               4
3122 +#define OMAP3_NEON_MASK                        (1<< OMAP3_NEON_SHIFT)
3123 +#define                FEAT_NEON               0
3124 +#define                FEAT_NEON_NONE          1
3125 +
3126 +
3127  #ifndef __ASSEMBLY__
3128  #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
3129                 defined(CONFIG_ARCH_OMAP4)
3130 diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
3131 index f129efb..7cb0556 100644
3132 --- a/arch/arm/plat-omap/include/mach/cpu.h
3133 +++ b/arch/arm/plat-omap/include/mach/cpu.h
3134 @@ -30,6 +30,8 @@
3135  #ifndef __ASM_ARCH_OMAP_CPU_H
3136  #define __ASM_ARCH_OMAP_CPU_H
3137
3138 +#include <linux/bitops.h>
3139 +
3140  /*
3141   * Omap device type i.e. EMU/HS/TST/GP/BAD
3142   */
3143 @@ -57,6 +59,23 @@ struct omap_chip_id {
3144  unsigned int omap_rev(void);
3145
3146  /*
3147 + * Define CPU revision bits
3148 + *
3149 + * Verbose meaning of the revision bits may be different for a silicon
3150 + * family. This difference can be handled separately.
3151 + */
3152 +#define OMAP_REVBITS_00                0x00
3153 +#define OMAP_REVBITS_10                0x10
3154 +#define OMAP_REVBITS_20                0x20
3155 +#define OMAP_REVBITS_30                0x30
3156 +#define OMAP_REVBITS_40                0x40
3157 +
3158 +/*
3159 + * Get the CPU revision for OMAP devices
3160 + */
3161 +#define GET_OMAP_REVISION()    ((omap_rev() >> 8) & 0xff)
3162 +
3163 +/*
3164   * Test if multicore OMAP support is needed
3165   */
3166  #undef MULTI_OMAP1
3167 @@ -161,6 +180,7 @@ IS_OMAP_CLASS(34xx, 0x34)
3168  IS_OMAP_SUBCLASS(242x, 0x242)
3169  IS_OMAP_SUBCLASS(243x, 0x243)
3170  IS_OMAP_SUBCLASS(343x, 0x343)
3171 +IS_OMAP_SUBCLASS(363x, 0x363)
3172
3173  #define cpu_is_omap7xx()               0
3174  #define cpu_is_omap15xx()              0
3175 @@ -301,7 +321,12 @@ IS_OMAP_TYPE(3430, 0x3430)
3176  #define cpu_is_omap2422()              0
3177  #define cpu_is_omap2423()              0
3178  #define cpu_is_omap2430()              0
3179 +#define cpu_is_omap3503()              0
3180 +#define cpu_is_omap3515()              0
3181 +#define cpu_is_omap3525()              0
3182 +#define cpu_is_omap3530()              0
3183  #define cpu_is_omap3430()              0
3184 +#define cpu_is_omap3630()              0
3185
3186  /*
3187   * Whether we have MULTI_OMAP1 or not, we still need to distinguish
3188 @@ -351,7 +376,23 @@ IS_OMAP_TYPE(3430, 0x3430)
3189
3190  #if defined(CONFIG_ARCH_OMAP34XX)
3191  # undef cpu_is_omap3430
3192 +# undef cpu_is_omap3503
3193 +# undef cpu_is_omap3515
3194 +# undef cpu_is_omap3525
3195 +# undef cpu_is_omap3530
3196  # define cpu_is_omap3430()             is_omap3430()
3197 +# define cpu_is_omap3503               (cpu_is_omap3430() &&           \
3198 +                                               (!omap3_has_iva()) &&   \
3199 +                                               (!omap3_has_sgx()))
3200 +# define cpu_is_omap3515               (cpu_is_omap3430() &&           \
3201 +                                               (omap3_has_iva()) &&    \
3202 +                                               (!omap3_has_sgx()))
3203 +# define cpu_is_omap3525               (cpu_is_omap3430() &&           \
3204 +                                               (omap3_has_sgx()) &&    \
3205 +                                               (!omap3_has_iva()))
3206 +# define cpu_is_omap3530               (cpu_is_omap3430())
3207 +# undef cpu_is_omap3630
3208 +# define cpu_is_omap3630()             is_omap363x()
3209  #endif
3210
3211  # if defined(CONFIG_ARCH_OMAP4)
3212 @@ -382,6 +423,14 @@ IS_OMAP_TYPE(3430, 0x3430)
3213  #define OMAP3430_REV_ES3_0     0x34303034
3214  #define OMAP3430_REV_ES3_1     0x34304034
3215
3216 +#define OMAP3630_REV_ES1_0     0x36300034
3217 +
3218 +#define OMAP35XX_CLASS         0x35000034
3219 +#define OMAP3503_REV(v)                (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
3220 +#define OMAP3515_REV(v)                (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
3221 +#define OMAP3525_REV(v)                (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
3222 +#define OMAP3530_REV(v)                (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
3223 +
3224  #define OMAP443X_CLASS         0x44300034
3225
3226  /*
3227 @@ -423,4 +472,27 @@ IS_OMAP_TYPE(3430, 0x3430)
3228  int omap_chip_is(struct omap_chip_id oci);
3229  void omap2_check_revision(void);
3230
3231 +/*
3232 + * Runtime detection of OMAP3 features
3233 + */
3234 +extern u32 omap3_features;
3235 +
3236 +#define OMAP3_HAS_L2CACHE              BIT(0)
3237 +#define OMAP3_HAS_IVA                  BIT(1)
3238 +#define OMAP3_HAS_SGX                  BIT(2)
3239 +#define OMAP3_HAS_NEON                 BIT(3)
3240 +#define OMAP3_HAS_ISP                  BIT(4)
3241 +
3242 +#define OMAP3_HAS_FEATURE(feat,flag)                   \
3243 +static inline unsigned int omap3_has_ ##feat(void)     \
3244 +{                                                      \
3245 +       return (omap3_features & OMAP3_HAS_ ##flag);    \
3246 +}                                                      \
3247 +
3248 +OMAP3_HAS_FEATURE(l2cache, L2CACHE)
3249 +OMAP3_HAS_FEATURE(sgx, SGX)
3250 +OMAP3_HAS_FEATURE(iva, IVA)
3251 +OMAP3_HAS_FEATURE(neon, NEON)
3252 +OMAP3_HAS_FEATURE(isp, ISP)
3253 +
3254  #endif
3255 diff --git a/arch/arm/plat-omap/include/mach/debug-macro.S b/arch/arm/plat-omap/include/mach/debug-macro.S
3256 index ac24050..63bb06d 100644
3257 --- a/arch/arm/plat-omap/include/mach/debug-macro.S
3258 +++ b/arch/arm/plat-omap/include/mach/debug-macro.S
3259 @@ -27,7 +27,7 @@
3260
3261  #elif  CONFIG_ARCH_OMAP2
3262                 moveq   \rx, #0x48000000        @ physical base address
3263 -               movne   \rx, #0xd8000000        @ virtual base
3264 +               movne   \rx, #0xfa000000        @ virtual base
3265                 orr     \rx, \rx, #0x0006a000
3266  #ifdef CONFIG_OMAP_LL_DEBUG_UART2
3267                 add     \rx, \rx, #0x00002000   @ UART 2
3268 @@ -38,7 +38,7 @@
3269
3270  #elif defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
3271                 moveq   \rx, #0x48000000        @ physical base address
3272 -               movne   \rx, #0xd8000000        @ virtual base
3273 +               movne   \rx, #0xfa000000        @ virtual base
3274                 orr     \rx, \rx, #0x0006a000
3275  #ifdef CONFIG_OMAP_LL_DEBUG_UART2
3276                 add     \rx, \rx, #0x00002000   @ UART 2
3277 diff --git a/arch/arm/plat-omap/include/mach/entry-macro.S b/arch/arm/plat-omap/include/mach/entry-macro.S
3278 index a559299..2aea566 100644
3279 --- a/arch/arm/plat-omap/include/mach/entry-macro.S
3280 +++ b/arch/arm/plat-omap/include/mach/entry-macro.S
3281 @@ -17,11 +17,11 @@
3282
3283  #if defined(CONFIG_ARCH_OMAP1)
3284
3285 -#if defined(CONFIG_ARCH_OMAP730) && \
3286 +#if (defined(CONFIG_ARCH_OMAP730)||defined(CONFIG_ARCH_OMAP850)) && \
3287         (defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX))
3288 -#error "FIXME: OMAP730 doesn't support multiple-OMAP"
3289 -#elif defined(CONFIG_ARCH_OMAP730)
3290 -#define INT_IH2_IRQ            INT_730_IH2_IRQ
3291 +#error "FIXME: OMAP7XX doesn't support multiple-OMAP"
3292 +#elif defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
3293 +#define INT_IH2_IRQ            INT_7XX_IH2_IRQ
3294  #elif defined(CONFIG_ARCH_OMAP15XX)
3295  #define INT_IH2_IRQ            INT_1510_IH2_IRQ
3296  #elif defined(CONFIG_ARCH_OMAP16XX)
3297 @@ -68,9 +68,9 @@
3298
3299  /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */
3300  #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430)
3301 -#define OMAP2_VA_IC_BASE               OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE)
3302 +#define OMAP2_VA_IC_BASE               OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
3303  #elif defined(CONFIG_ARCH_OMAP34XX)
3304 -#define OMAP2_VA_IC_BASE               OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE)
3305 +#define OMAP2_VA_IC_BASE               OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
3306  #endif
3307  #if defined(CONFIG_ARCH_OMAP4)
3308  #include <mach/omap44xx.h>
3309 @@ -104,6 +104,8 @@
3310
3311                 .endm
3312  #else
3313 +#define OMAP44XX_VA_GIC_CPU_BASE       OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
3314 +
3315                 /*
3316                  * The interrupt numbering scheme is defined in the
3317                  * interrupt controller spec.  To wit:
3318 diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
3319 index 26c1fbf..99c4241 100644
3320 --- a/arch/arm/plat-omap/include/mach/hardware.h
3321 +++ b/arch/arm/plat-omap/include/mach/hardware.h
3322 @@ -280,7 +280,7 @@
3323   * ---------------------------------------------------------------------------
3324   */
3325
3326 -#include "omap730.h"
3327 +#include "omap7xx.h"
3328  #include "omap1510.h"
3329  #include "omap16xx.h"
3330  #include "omap24xx.h"
3331 diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
3332 index 8d32df3..7e5319f 100644
3333 --- a/arch/arm/plat-omap/include/mach/io.h
3334 +++ b/arch/arm/plat-omap/include/mach/io.h
3335 @@ -63,8 +63,24 @@
3336  #define OMAP1_IO_OFFSET                0x01000000      /* Virtual IO = 0xfefb0000 */
3337  #define OMAP1_IO_ADDRESS(pa)   IOMEM((pa) - OMAP1_IO_OFFSET)
3338
3339 -#define OMAP2_IO_OFFSET                0x90000000
3340 -#define OMAP2_IO_ADDRESS(pa)   IOMEM((pa) + OMAP2_IO_OFFSET) /* L3 and L4 */
3341 +#define OMAP2_L3_IO_OFFSET     0x90000000
3342 +#define OMAP2_L3_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_L3_IO_OFFSET) /* L3 */
3343 +
3344 +
3345 +#define OMAP2_L4_IO_OFFSET     0xb2000000
3346 +#define OMAP2_L4_IO_ADDRESS(pa)        IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */
3347 +
3348 +#define OMAP4_L3_IO_OFFSET     0xb4000000
3349 +#define OMAP4_L3_IO_ADDRESS(pa)        IOMEM((pa) + OMAP4_L3_IO_OFFSET) /* L3 */
3350 +
3351 +#define OMAP4_L3_PER_IO_OFFSET 0xb1100000
3352 +#define OMAP4_L3_PER_IO_ADDRESS(pa)    IOMEM((pa) + OMAP4_L3_PER_IO_OFFSET)
3353 +
3354 +#define OMAP4_GPMC_IO_OFFSET           0xa9000000
3355 +#define OMAP4_GPMC_IO_ADDRESS(pa)      IOMEM((pa) + OMAP4_GPMC_IO_OFFSET)
3356 +
3357 +#define OMAP2_EMU_IO_OFFSET            0xaa800000      /* Emulation */
3358 +#define OMAP2_EMU_IO_ADDRESS(pa)       IOMEM((pa) + OMAP2_EMU_IO_OFFSET)
3359
3360  /*
3361   * ----------------------------------------------------------------------------
3362 @@ -83,24 +99,27 @@
3363   */
3364
3365  /* We map both L3 and L4 on OMAP2 */
3366 -#define L3_24XX_PHYS   L3_24XX_BASE    /* 0x68000000 */
3367 -#define L3_24XX_VIRT   0xf8000000
3368 +#define L3_24XX_PHYS   L3_24XX_BASE    /* 0x68000000 --> 0xf8000000*/
3369 +#define L3_24XX_VIRT   (L3_24XX_PHYS + OMAP2_L3_IO_OFFSET)
3370  #define L3_24XX_SIZE   SZ_1M           /* 44kB of 128MB used, want 1MB sect */
3371 -#define L4_24XX_PHYS   L4_24XX_BASE    /* 0x48000000 */
3372 -#define L4_24XX_VIRT   0xd8000000
3373 +#define L4_24XX_PHYS   L4_24XX_BASE    /* 0x48000000 --> 0xfa000000 */
3374 +#define L4_24XX_VIRT   (L4_24XX_PHYS + OMAP2_L4_IO_OFFSET)
3375  #define L4_24XX_SIZE   SZ_1M           /* 1MB of 128MB used, want 1MB sect */
3376
3377 -#define L4_WK_243X_PHYS                L4_WK_243X_BASE         /* 0x49000000 */
3378 -#define L4_WK_243X_VIRT                0xd9000000
3379 +#define L4_WK_243X_PHYS                L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
3380 +#define L4_WK_243X_VIRT                (L4_WK_243X_PHYS + OMAP2_L4_IO_OFFSET)
3381  #define L4_WK_243X_SIZE                SZ_1M
3382 -#define OMAP243X_GPMC_PHYS     OMAP243X_GPMC_BASE      /* 0x49000000 */
3383 -#define OMAP243X_GPMC_VIRT     0xFE000000
3384 +#define OMAP243X_GPMC_PHYS     OMAP243X_GPMC_BASE
3385 +#define OMAP243X_GPMC_VIRT     (OMAP243X_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
3386 +                                               /* 0x6e000000 --> 0xfe000000 */
3387  #define OMAP243X_GPMC_SIZE     SZ_1M
3388  #define OMAP243X_SDRC_PHYS     OMAP243X_SDRC_BASE
3389 -#define OMAP243X_SDRC_VIRT     0xFD000000
3390 +                                               /* 0x6D000000 --> 0xfd000000 */
3391 +#define OMAP243X_SDRC_VIRT     (OMAP243X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
3392  #define OMAP243X_SDRC_SIZE     SZ_1M
3393  #define OMAP243X_SMS_PHYS      OMAP243X_SMS_BASE
3394 -#define OMAP243X_SMS_VIRT      0xFC000000
3395 +                                               /* 0x6c000000 --> 0xfc000000 */
3396 +#define OMAP243X_SMS_VIRT      (OMAP243X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
3397  #define OMAP243X_SMS_SIZE      SZ_1M
3398
3399  /* DSP */
3400 @@ -121,12 +140,12 @@
3401   */
3402
3403  /* We map both L3 and L4 on OMAP3 */
3404 -#define L3_34XX_PHYS           L3_34XX_BASE    /* 0x68000000 */
3405 -#define L3_34XX_VIRT           0xf8000000
3406 +#define L3_34XX_PHYS           L3_34XX_BASE    /* 0x68000000 --> 0xf8000000 */
3407 +#define L3_34XX_VIRT           (L3_34XX_PHYS + OMAP2_L3_IO_OFFSET)
3408  #define L3_34XX_SIZE           SZ_1M   /* 44kB of 128MB used, want 1MB sect */
3409
3410 -#define L4_34XX_PHYS           L4_34XX_BASE    /* 0x48000000 */
3411 -#define L4_34XX_VIRT           0xd8000000
3412 +#define L4_34XX_PHYS           L4_34XX_BASE    /* 0x48000000 --> 0xfa000000 */
3413 +#define L4_34XX_VIRT           (L4_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3414  #define L4_34XX_SIZE           SZ_4M   /* 1MB of 128MB used, want 1MB sect */
3415
3416  /*
3417 @@ -134,28 +153,33 @@
3418   * VPOM3430 was not working for Int controller
3419   */
3420
3421 -#define L4_WK_34XX_PHYS                L4_WK_34XX_BASE /* 0x48300000 */
3422 -#define L4_WK_34XX_VIRT                0xd8300000
3423 +#define L4_WK_34XX_PHYS                L4_WK_34XX_BASE /* 0x48300000 --> 0xfa300000 */
3424 +#define L4_WK_34XX_VIRT                (L4_WK_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3425  #define L4_WK_34XX_SIZE                SZ_1M
3426
3427 -#define L4_PER_34XX_PHYS       L4_PER_34XX_BASE /* 0x49000000 */
3428 -#define L4_PER_34XX_VIRT       0xd9000000
3429 +#define L4_PER_34XX_PHYS       L4_PER_34XX_BASE
3430 +                                               /* 0x49000000 --> 0xfb000000 */
3431 +#define L4_PER_34XX_VIRT       (L4_PER_34XX_PHYS + OMAP2_L4_IO_OFFSET)
3432  #define L4_PER_34XX_SIZE       SZ_1M
3433
3434 -#define L4_EMU_34XX_PHYS       L4_EMU_34XX_BASE /* 0x54000000 */
3435 -#define L4_EMU_34XX_VIRT       0xe4000000
3436 -#define L4_EMU_34XX_SIZE       SZ_64M
3437 +#define L4_EMU_34XX_PHYS       L4_EMU_34XX_BASE
3438 +                                               /* 0x54000000 --> 0xfe800000 */
3439 +#define L4_EMU_34XX_VIRT       (L4_EMU_34XX_PHYS + OMAP2_EMU_IO_OFFSET)
3440 +#define L4_EMU_34XX_SIZE       SZ_8M
3441
3442 -#define OMAP34XX_GPMC_PHYS     OMAP34XX_GPMC_BASE /* 0x6E000000 */
3443 -#define OMAP34XX_GPMC_VIRT     0xFE000000
3444 +#define OMAP34XX_GPMC_PHYS     OMAP34XX_GPMC_BASE
3445 +                                               /* 0x6e000000 --> 0xfe000000 */
3446 +#define OMAP34XX_GPMC_VIRT     (OMAP34XX_GPMC_PHYS + OMAP2_L3_IO_OFFSET)
3447  #define OMAP34XX_GPMC_SIZE     SZ_1M
3448
3449 -#define OMAP343X_SMS_PHYS      OMAP343X_SMS_BASE /* 0x6C000000 */
3450 -#define OMAP343X_SMS_VIRT      0xFC000000
3451 +#define OMAP343X_SMS_PHYS      OMAP343X_SMS_BASE
3452 +                                               /* 0x6c000000 --> 0xfc000000 */
3453 +#define OMAP343X_SMS_VIRT      (OMAP343X_SMS_PHYS + OMAP2_L3_IO_OFFSET)
3454  #define OMAP343X_SMS_SIZE      SZ_1M
3455
3456 -#define OMAP343X_SDRC_PHYS     OMAP343X_SDRC_BASE /* 0x6D000000 */
3457 -#define OMAP343X_SDRC_VIRT     0xFD000000
3458 +#define OMAP343X_SDRC_PHYS     OMAP343X_SDRC_BASE
3459 +                                               /* 0x6D000000 --> 0xfd000000 */
3460 +#define OMAP343X_SDRC_VIRT     (OMAP343X_SDRC_PHYS + OMAP2_L3_IO_OFFSET)
3461  #define OMAP343X_SDRC_SIZE     SZ_1M
3462
3463  /* DSP */
3464 @@ -176,32 +200,54 @@
3465   */
3466
3467  /* We map both L3 and L4 on OMAP4 */
3468 -#define L3_44XX_PHYS           L3_44XX_BASE
3469 -#define L3_44XX_VIRT           0xd4000000
3470 +#define L3_44XX_PHYS           L3_44XX_BASE    /* 0x44000000 --> 0xf8000000 */
3471 +#define L3_44XX_VIRT           (L3_44XX_PHYS + OMAP4_L3_IO_OFFSET)
3472  #define L3_44XX_SIZE           SZ_1M
3473
3474 -#define L4_44XX_PHYS           L4_44XX_BASE
3475 -#define L4_44XX_VIRT           0xda000000
3476 +#define L4_44XX_PHYS           L4_44XX_BASE    /* 0x4a000000 --> 0xfc000000 */
3477 +#define L4_44XX_VIRT           (L4_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3478  #define L4_44XX_SIZE           SZ_4M
3479
3480
3481 -#define L4_WK_44XX_PHYS                L4_WK_44XX_BASE
3482 -#define L4_WK_44XX_VIRT                0xda300000
3483 +#define L4_WK_44XX_PHYS                L4_WK_44XX_BASE /* 0x4a300000 --> 0xfc300000 */
3484 +#define L4_WK_44XX_VIRT                (L4_WK_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3485  #define L4_WK_44XX_SIZE                SZ_1M
3486
3487  #define L4_PER_44XX_PHYS       L4_PER_44XX_BASE
3488 -#define L4_PER_44XX_VIRT       0xd8000000
3489 +                                               /* 0x48000000 --> 0xfa000000 */
3490 +#define L4_PER_44XX_VIRT       (L4_PER_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3491  #define L4_PER_44XX_SIZE       SZ_4M
3492
3493 +#define L4_ABE_44XX_PHYS       L4_ABE_44XX_BASE
3494 +                                               /* 0x49000000 --> 0xfb000000 */
3495 +#define L4_ABE_44XX_VIRT       (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
3496 +#define L4_ABE_44XX_SIZE       SZ_1M
3497 +
3498  #define L4_EMU_44XX_PHYS       L4_EMU_44XX_BASE
3499 -#define L4_EMU_44XX_VIRT       0xe4000000
3500 -#define L4_EMU_44XX_SIZE       SZ_64M
3501 +                                               /* 0x54000000 --> 0xfe800000 */
3502 +#define L4_EMU_44XX_VIRT       (L4_EMU_44XX_PHYS + OMAP2_EMU_IO_OFFSET)
3503 +#define L4_EMU_44XX_SIZE       SZ_8M
3504
3505  #define OMAP44XX_GPMC_PHYS     OMAP44XX_GPMC_BASE
3506 -#define OMAP44XX_GPMC_VIRT     0xe0000000
3507 +                                               /* 0x50000000 --> 0xf9000000 */
3508 +#define OMAP44XX_GPMC_VIRT     (OMAP44XX_GPMC_PHYS + OMAP4_GPMC_IO_OFFSET)
3509  #define OMAP44XX_GPMC_SIZE     SZ_1M
3510
3511
3512 +#define OMAP44XX_EMIF1_PHYS    OMAP44XX_EMIF1_BASE
3513 +                                               /* 0x4c000000 --> 0xfd100000 */
3514 +#define OMAP44XX_EMIF1_VIRT    (OMAP44XX_EMIF1_PHYS + OMAP4_L3_PER_IO_OFFSET)
3515 +#define OMAP44XX_EMIF1_SIZE    SZ_1M
3516 +
3517 +#define OMAP44XX_EMIF2_PHYS    OMAP44XX_EMIF2_BASE
3518 +                                               /* 0x4d000000 --> 0xfd200000 */
3519 +#define OMAP44XX_EMIF2_VIRT    (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
3520 +#define OMAP44XX_EMIF2_SIZE    SZ_1M
3521 +
3522 +#define OMAP44XX_DMM_PHYS      OMAP44XX_DMM_BASE
3523 +                                               /* 0x4e000000 --> 0xfd300000 */
3524 +#define OMAP44XX_DMM_VIRT      (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
3525 +#define OMAP44XX_DMM_SIZE      SZ_1M
3526  /*
3527   * ----------------------------------------------------------------------------
3528   * Omap specific register access
3529 diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
3530 index 28a1650..6a6d028 100644
3531 --- a/arch/arm/plat-omap/include/mach/irqs.h
3532 +++ b/arch/arm/plat-omap/include/mach/irqs.h
3533 @@ -86,49 +86,26 @@
3534  #define INT_1610_SSR_FIFO_0    29
3535
3536  /*
3537 - * OMAP-730 specific IRQ numbers for interrupt handler 1
3538 + * OMAP-7xx specific IRQ numbers for interrupt handler 1
3539   */
3540 -#define INT_730_IH2_FIQ                0
3541 -#define INT_730_IH2_IRQ                1
3542 -#define INT_730_USB_NON_ISO    2
3543 -#define INT_730_USB_ISO                3
3544 -#define INT_730_ICR            4
3545 -#define INT_730_EAC            5
3546 -#define INT_730_GPIO_BANK1     6
3547 -#define INT_730_GPIO_BANK2     7
3548 -#define INT_730_GPIO_BANK3     8
3549 -#define INT_730_McBSP2TX       10
3550 -#define INT_730_McBSP2RX       11
3551 -#define INT_730_McBSP2RX_OVF   12
3552 -#define INT_730_LCD_LINE       14
3553 -#define INT_730_GSM_PROTECT    15
3554 -#define INT_730_TIMER3         16
3555 -#define INT_730_GPIO_BANK5     17
3556 -#define INT_730_GPIO_BANK6     18
3557 -#define INT_730_SPGIO_WR       29
3558 -
3559 -/*
3560 - * OMAP-850 specific IRQ numbers for interrupt handler 1
3561 - */
3562 -#define INT_850_IH2_FIQ                0
3563 -#define INT_850_IH2_IRQ                1
3564 -#define INT_850_USB_NON_ISO    2
3565 -#define INT_850_USB_ISO                3
3566 -#define INT_850_ICR            4
3567 -#define INT_850_EAC            5
3568 -#define INT_850_GPIO_BANK1     6
3569 -#define INT_850_GPIO_BANK2     7
3570 -#define INT_850_GPIO_BANK3     8
3571 -#define INT_850_McBSP2TX       10
3572 -#define INT_850_McBSP2RX       11
3573 -#define INT_850_McBSP2RX_OVF   12
3574 -#define INT_850_LCD_LINE       14
3575 -#define INT_850_GSM_PROTECT    15
3576 -#define INT_850_TIMER3         16
3577 -#define INT_850_GPIO_BANK5     17
3578 -#define INT_850_GPIO_BANK6     18
3579 -#define INT_850_SPGIO_WR       29
3580 -
3581 +#define INT_7XX_IH2_FIQ                0
3582 +#define INT_7XX_IH2_IRQ                1
3583 +#define INT_7XX_USB_NON_ISO    2
3584 +#define INT_7XX_USB_ISO                3
3585 +#define INT_7XX_ICR            4
3586 +#define INT_7XX_EAC            5
3587 +#define INT_7XX_GPIO_BANK1     6
3588 +#define INT_7XX_GPIO_BANK2     7
3589 +#define INT_7XX_GPIO_BANK3     8
3590 +#define INT_7XX_McBSP2TX       10
3591 +#define INT_7XX_McBSP2RX       11
3592 +#define INT_7XX_McBSP2RX_OVF   12
3593 +#define INT_7XX_LCD_LINE       14
3594 +#define INT_7XX_GSM_PROTECT    15
3595 +#define INT_7XX_TIMER3         16
3596 +#define INT_7XX_GPIO_BANK5     17
3597 +#define INT_7XX_GPIO_BANK6     18
3598 +#define INT_7XX_SPGIO_WR       29
3599
3600  /*
3601   * IRQ numbers for interrupt handler 2
3602 @@ -206,120 +183,62 @@
3603  #define INT_1610_SHA1MD5       (91 + IH2_BASE)
3604
3605  /*
3606 - * OMAP-730 specific IRQ numbers for interrupt handler 2
3607 - */
3608 -#define INT_730_HW_ERRORS      (0 + IH2_BASE)
3609 -#define INT_730_NFIQ_PWR_FAIL  (1 + IH2_BASE)
3610 -#define INT_730_CFCD           (2 + IH2_BASE)
3611 -#define INT_730_CFIREQ         (3 + IH2_BASE)
3612 -#define INT_730_I2C            (4 + IH2_BASE)
3613 -#define INT_730_PCC            (5 + IH2_BASE)
3614 -#define INT_730_MPU_EXT_NIRQ   (6 + IH2_BASE)
3615 -#define INT_730_SPI_100K_1     (7 + IH2_BASE)
3616 -#define INT_730_SYREN_SPI      (8 + IH2_BASE)
3617 -#define INT_730_VLYNQ          (9 + IH2_BASE)
3618 -#define INT_730_GPIO_BANK4     (10 + IH2_BASE)
3619 -#define INT_730_McBSP1TX       (11 + IH2_BASE)
3620 -#define INT_730_McBSP1RX       (12 + IH2_BASE)
3621 -#define INT_730_McBSP1RX_OF    (13 + IH2_BASE)
3622 -#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3623 -#define INT_730_UART_MODEM_1   (15 + IH2_BASE)
3624 -#define INT_730_MCSI           (16 + IH2_BASE)
3625 -#define INT_730_uWireTX                (17 + IH2_BASE)
3626 -#define INT_730_uWireRX                (18 + IH2_BASE)
3627 -#define INT_730_SMC_CD         (19 + IH2_BASE)
3628 -#define INT_730_SMC_IREQ       (20 + IH2_BASE)
3629 -#define INT_730_HDQ_1WIRE      (21 + IH2_BASE)
3630 -#define INT_730_TIMER32K       (22 + IH2_BASE)
3631 -#define INT_730_MMC_SDIO       (23 + IH2_BASE)
3632 -#define INT_730_UPLD           (24 + IH2_BASE)
3633 -#define INT_730_USB_HHC_1      (27 + IH2_BASE)
3634 -#define INT_730_USB_HHC_2      (28 + IH2_BASE)
3635 -#define INT_730_USB_GENI       (29 + IH2_BASE)
3636 -#define INT_730_USB_OTG                (30 + IH2_BASE)
3637 -#define INT_730_CAMERA_IF      (31 + IH2_BASE)
3638 -#define INT_730_RNG            (32 + IH2_BASE)
3639 -#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
3640 -#define INT_730_DBB_RF_EN      (34 + IH2_BASE)
3641 -#define INT_730_MPUIO_KEYPAD   (35 + IH2_BASE)
3642 -#define INT_730_SHA1_MD5       (36 + IH2_BASE)
3643 -#define INT_730_SPI_100K_2     (37 + IH2_BASE)
3644 -#define INT_730_RNG_IDLE       (38 + IH2_BASE)
3645 -#define INT_730_MPUIO          (39 + IH2_BASE)
3646 -#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF       (40 + IH2_BASE)
3647 -#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
3648 -#define INT_730_LLPC_OE_RISING (42 + IH2_BASE)
3649 -#define INT_730_LLPC_VSYNC     (43 + IH2_BASE)
3650 -#define INT_730_WAKE_UP_REQ    (46 + IH2_BASE)
3651 -#define INT_730_DMA_CH6                (53 + IH2_BASE)
3652 -#define INT_730_DMA_CH7                (54 + IH2_BASE)
3653 -#define INT_730_DMA_CH8                (55 + IH2_BASE)
3654 -#define INT_730_DMA_CH9                (56 + IH2_BASE)
3655 -#define INT_730_DMA_CH10       (57 + IH2_BASE)
3656 -#define INT_730_DMA_CH11       (58 + IH2_BASE)
3657 -#define INT_730_DMA_CH12       (59 + IH2_BASE)
3658 -#define INT_730_DMA_CH13       (60 + IH2_BASE)
3659 -#define INT_730_DMA_CH14       (61 + IH2_BASE)
3660 -#define INT_730_DMA_CH15       (62 + IH2_BASE)
3661 -#define INT_730_NAND           (63 + IH2_BASE)
3662 -
3663 -/*
3664 - * OMAP-850 specific IRQ numbers for interrupt handler 2
3665 + * OMAP-7xx specific IRQ numbers for interrupt handler 2
3666   */
3667 -#define INT_850_HW_ERRORS      (0 + IH2_BASE)
3668 -#define INT_850_NFIQ_PWR_FAIL  (1 + IH2_BASE)
3669 -#define INT_850_CFCD           (2 + IH2_BASE)
3670 -#define INT_850_CFIREQ         (3 + IH2_BASE)
3671 -#define INT_850_I2C            (4 + IH2_BASE)
3672 -#define INT_850_PCC            (5 + IH2_BASE)
3673 -#define INT_850_MPU_EXT_NIRQ   (6 + IH2_BASE)
3674 -#define INT_850_SPI_100K_1     (7 + IH2_BASE)
3675 -#define INT_850_SYREN_SPI      (8 + IH2_BASE)
3676 -#define INT_850_VLYNQ          (9 + IH2_BASE)
3677 -#define INT_850_GPIO_BANK4     (10 + IH2_BASE)
3678 -#define INT_850_McBSP1TX       (11 + IH2_BASE)
3679 -#define INT_850_McBSP1RX       (12 + IH2_BASE)
3680 -#define INT_850_McBSP1RX_OF    (13 + IH2_BASE)
3681 -#define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3682 -#define INT_850_UART_MODEM_1   (15 + IH2_BASE)
3683 -#define INT_850_MCSI           (16 + IH2_BASE)
3684 -#define INT_850_uWireTX                (17 + IH2_BASE)
3685 -#define INT_850_uWireRX                (18 + IH2_BASE)
3686 -#define INT_850_SMC_CD         (19 + IH2_BASE)
3687 -#define INT_850_SMC_IREQ       (20 + IH2_BASE)
3688 -#define INT_850_HDQ_1WIRE      (21 + IH2_BASE)
3689 -#define INT_850_TIMER32K       (22 + IH2_BASE)
3690 -#define INT_850_MMC_SDIO       (23 + IH2_BASE)
3691 -#define INT_850_UPLD           (24 + IH2_BASE)
3692 -#define INT_850_USB_HHC_1      (27 + IH2_BASE)
3693 -#define INT_850_USB_HHC_2      (28 + IH2_BASE)
3694 -#define INT_850_USB_GENI       (29 + IH2_BASE)
3695 -#define INT_850_USB_OTG                (30 + IH2_BASE)
3696 -#define INT_850_CAMERA_IF      (31 + IH2_BASE)
3697 -#define INT_850_RNG            (32 + IH2_BASE)
3698 -#define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE)
3699 -#define INT_850_DBB_RF_EN      (34 + IH2_BASE)
3700 -#define INT_850_MPUIO_KEYPAD   (35 + IH2_BASE)
3701 -#define INT_850_SHA1_MD5       (36 + IH2_BASE)
3702 -#define INT_850_SPI_100K_2     (37 + IH2_BASE)
3703 -#define INT_850_RNG_IDLE       (38 + IH2_BASE)
3704 -#define INT_850_MPUIO          (39 + IH2_BASE)
3705 -#define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF       (40 + IH2_BASE)
3706 -#define INT_850_LLPC_OE_FALLING (41 + IH2_BASE)
3707 -#define INT_850_LLPC_OE_RISING (42 + IH2_BASE)
3708 -#define INT_850_LLPC_VSYNC     (43 + IH2_BASE)
3709 -#define INT_850_WAKE_UP_REQ    (46 + IH2_BASE)
3710 -#define INT_850_DMA_CH6                (53 + IH2_BASE)
3711 -#define INT_850_DMA_CH7                (54 + IH2_BASE)
3712 -#define INT_850_DMA_CH8                (55 + IH2_BASE)
3713 -#define INT_850_DMA_CH9                (56 + IH2_BASE)
3714 -#define INT_850_DMA_CH10       (57 + IH2_BASE)
3715 -#define INT_850_DMA_CH11       (58 + IH2_BASE)
3716 -#define INT_850_DMA_CH12       (59 + IH2_BASE)
3717 -#define INT_850_DMA_CH13       (60 + IH2_BASE)
3718 -#define INT_850_DMA_CH14       (61 + IH2_BASE)
3719 -#define INT_850_DMA_CH15       (62 + IH2_BASE)
3720 -#define INT_850_NAND           (63 + IH2_BASE)
3721 +#define INT_7XX_HW_ERRORS      (0 + IH2_BASE)
3722 +#define INT_7XX_NFIQ_PWR_FAIL  (1 + IH2_BASE)
3723 +#define INT_7XX_CFCD           (2 + IH2_BASE)
3724 +#define INT_7XX_CFIREQ         (3 + IH2_BASE)
3725 +#define INT_7XX_I2C            (4 + IH2_BASE)
3726 +#define INT_7XX_PCC            (5 + IH2_BASE)
3727 +#define INT_7XX_MPU_EXT_NIRQ   (6 + IH2_BASE)
3728 +#define INT_7XX_SPI_100K_1     (7 + IH2_BASE)
3729 +#define INT_7XX_SYREN_SPI      (8 + IH2_BASE)
3730 +#define INT_7XX_VLYNQ          (9 + IH2_BASE)
3731 +#define INT_7XX_GPIO_BANK4     (10 + IH2_BASE)
3732 +#define INT_7XX_McBSP1TX       (11 + IH2_BASE)
3733 +#define INT_7XX_McBSP1RX       (12 + IH2_BASE)
3734 +#define INT_7XX_McBSP1RX_OF    (13 + IH2_BASE)
3735 +#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
3736 +#define INT_7XX_UART_MODEM_1   (15 + IH2_BASE)
3737 +#define INT_7XX_MCSI           (16 + IH2_BASE)
3738 +#define INT_7XX_uWireTX                (17 + IH2_BASE)
3739 +#define INT_7XX_uWireRX                (18 + IH2_BASE)
3740 +#define INT_7XX_SMC_CD         (19 + IH2_BASE)
3741 +#define INT_7XX_SMC_IREQ       (20 + IH2_BASE)
3742 +#define INT_7XX_HDQ_1WIRE      (21 + IH2_BASE)
3743 +#define INT_7XX_TIMER32K       (22 + IH2_BASE)
3744 +#define INT_7XX_MMC_SDIO       (23 + IH2_BASE)
3745 +#define INT_7XX_UPLD           (24 + IH2_BASE)
3746 +#define INT_7XX_USB_HHC_1      (27 + IH2_BASE)
3747 +#define INT_7XX_USB_HHC_2      (28 + IH2_BASE)
3748 +#define INT_7XX_USB_GENI       (29 + IH2_BASE)
3749 +#define INT_7XX_USB_OTG                (30 + IH2_BASE)
3750 +#define INT_7XX_CAMERA_IF      (31 + IH2_BASE)
3751 +#define INT_7XX_RNG            (32 + IH2_BASE)
3752 +#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
3753 +#define INT_7XX_DBB_RF_EN      (34 + IH2_BASE)
3754 +#define INT_7XX_MPUIO_KEYPAD   (35 + IH2_BASE)
3755 +#define INT_7XX_SHA1_MD5       (36 + IH2_BASE)
3756 +#define INT_7XX_SPI_100K_2     (37 + IH2_BASE)
3757 +#define INT_7XX_RNG_IDLE       (38 + IH2_BASE)
3758 +#define INT_7XX_MPUIO          (39 + IH2_BASE)
3759 +#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF       (40 + IH2_BASE)
3760 +#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
3761 +#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
3762 +#define INT_7XX_LLPC_VSYNC     (43 + IH2_BASE)
3763 +#define INT_7XX_WAKE_UP_REQ    (46 + IH2_BASE)
3764 +#define INT_7XX_DMA_CH6                (53 + IH2_BASE)
3765 +#define INT_7XX_DMA_CH7                (54 + IH2_BASE)
3766 +#define INT_7XX_DMA_CH8                (55 + IH2_BASE)
3767 +#define INT_7XX_DMA_CH9                (56 + IH2_BASE)
3768 +#define INT_7XX_DMA_CH10       (57 + IH2_BASE)
3769 +#define INT_7XX_DMA_CH11       (58 + IH2_BASE)
3770 +#define INT_7XX_DMA_CH12       (59 + IH2_BASE)
3771 +#define INT_7XX_DMA_CH13       (60 + IH2_BASE)
3772 +#define INT_7XX_DMA_CH14       (61 + IH2_BASE)
3773 +#define INT_7XX_DMA_CH15       (62 + IH2_BASE)
3774 +#define INT_7XX_NAND           (63 + IH2_BASE)
3775
3776  #define INT_24XX_SYS_NIRQ      7
3777  #define INT_24XX_SDMA_IRQ0     12
3778 diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
3779 index e0d6eca..7e9cae3 100644
3780 --- a/arch/arm/plat-omap/include/mach/mcbsp.h
3781 +++ b/arch/arm/plat-omap/include/mach/mcbsp.h
3782 @@ -30,8 +30,8 @@
3783  #include <mach/hardware.h>
3784  #include <mach/clock.h>
3785
3786 -#define OMAP730_MCBSP1_BASE    0xfffb1000
3787 -#define OMAP730_MCBSP2_BASE    0xfffb1800
3788 +#define OMAP7XX_MCBSP1_BASE    0xfffb1000
3789 +#define OMAP7XX_MCBSP2_BASE    0xfffb1800
3790
3791  #define OMAP1510_MCBSP1_BASE   0xe1011800
3792  #define OMAP1510_MCBSP2_BASE   0xfffb1000
3793 @@ -58,7 +58,7 @@
3794  #define OMAP44XX_MCBSP3_BASE   0x49026000
3795  #define OMAP44XX_MCBSP4_BASE   0x48074000
3796
3797 -#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
3798 +#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
3799
3800  #define OMAP_MCBSP_REG_DRR2    0x00
3801  #define OMAP_MCBSP_REG_DRR1    0x02
3802 diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
3803 index 0f49d2d..f3c1d8a 100644
3804 --- a/arch/arm/plat-omap/include/mach/mux.h
3805 +++ b/arch/arm/plat-omap/include/mach/mux.h
3806 @@ -51,23 +51,13 @@
3807                                         .pu_pd_reg = PU_PD_SEL_##reg, \
3808                                         .pu_pd_val = status,
3809
3810 -#define MUX_REG_730(reg, mode_offset, mode) .mux_reg_name = "OMAP730_IO_CONF_"#reg, \
3811 -                                       .mux_reg = OMAP730_IO_CONF_##reg, \
3812 +#define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
3813 +                                       .mux_reg = OMAP7XX_IO_CONF_##reg, \
3814                                         .mask_offset = mode_offset, \
3815                                         .mask = mode,
3816
3817 -#define PULL_REG_730(reg, bit, status) .pull_name = "OMAP730_IO_CONF_"#reg, \
3818 -                                       .pull_reg = OMAP730_IO_CONF_##reg, \
3819 -                                       .pull_bit = bit, \
3820 -                                       .pull_val = status,
3821 -
3822 -#define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \
3823 -                                       .mux_reg = OMAP850_IO_CONF_##reg, \
3824 -                                       .mask_offset = mode_offset, \
3825 -                                       .mask = mode,
3826 -
3827 -#define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \
3828 -                                       .pull_reg = OMAP850_IO_CONF_##reg, \
3829 +#define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
3830 +                                       .pull_reg = OMAP7XX_IO_CONF_##reg, \
3831                                         .pull_bit = bit, \
3832                                         .pull_val = status,
3833
3834 @@ -84,21 +74,12 @@
3835  #define PU_PD_REG(reg, status)         .pu_pd_reg = PU_PD_SEL_##reg, \
3836                                         .pu_pd_val = status,
3837
3838 -#define MUX_REG_730(reg, mode_offset, mode) \
3839 -                                       .mux_reg = OMAP730_IO_CONF_##reg, \
3840 +#define MUX_REG_7XX(reg, mode_offset, mode) \
3841 +                                       .mux_reg = OMAP7XX_IO_CONF_##reg, \
3842                                         .mask_offset = mode_offset, \
3843                                         .mask = mode,
3844
3845 -#define PULL_REG_730(reg, bit, status) .pull_reg = OMAP730_IO_CONF_##reg, \
3846 -                                       .pull_bit = bit, \
3847 -                                       .pull_val = status,
3848 -
3849 -#define MUX_REG_850(reg, mode_offset, mode) \
3850 -                                       .mux_reg = OMAP850_IO_CONF_##reg, \
3851 -                                       .mask_offset = mode_offset, \
3852 -                                       .mask = mode,
3853 -
3854 -#define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \
3855 +#define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
3856                                         .pull_bit = bit, \
3857                                         .pull_val = status,
3858
3859 @@ -118,32 +99,21 @@
3860
3861  /*
3862   * OMAP730/850 has a slightly different config for the pin mux.
3863 - * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and
3864 + * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
3865   *   not the FUNC_MUX_CTRL_x regs from hardware.h
3866   * - for pull-up/down, only has one enable bit which is is in the same register
3867   *   as mux config
3868   */
3869 -#define MUX_CFG_730(desc, mux_reg, mode_offset, mode,  \
3870 +#define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,  \
3871                    pull_bit, pull_status, debug_status)\
3872  {                                                      \
3873         .name =  desc,                                  \
3874         .debug = debug_status,                          \
3875 -       MUX_REG_730(mux_reg, mode_offset, mode)         \
3876 -       PULL_REG_730(mux_reg, pull_bit, pull_status)    \
3877 +       MUX_REG_7XX(mux_reg, mode_offset, mode)         \
3878 +       PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
3879         PU_PD_REG(NA, 0)                \
3880  },
3881
3882 -#define MUX_CFG_850(desc, mux_reg, mode_offset, mode,  \
3883 -                  pull_bit, pull_status, debug_status)\
3884 -{                                                      \
3885 -       .name =  desc,                                  \
3886 -       .debug = debug_status,                          \
3887 -       MUX_REG_850(mux_reg, mode_offset, mode)         \
3888 -       PULL_REG_850(mux_reg, pull_bit, pull_status)    \
3889 -       PU_PD_REG(NA, 0)                \
3890 -},
3891 -
3892 -
3893  #define MUX_CFG_24XX(desc, reg_offset, mode,                   \
3894                                 pull_en, pull_mode, dbg)        \
3895  {                                                              \
3896 @@ -232,45 +202,25 @@ struct pin_config {
3897
3898  };
3899
3900 -enum omap730_index {
3901 +enum omap7xx_index {
3902         /* OMAP 730 keyboard */
3903 -       E2_730_KBR0,
3904 -       J7_730_KBR1,
3905 -       E1_730_KBR2,
3906 -       F3_730_KBR3,
3907 -       D2_730_KBR4,
3908 -       C2_730_KBC0,
3909 -       D3_730_KBC1,
3910 -       E4_730_KBC2,
3911 -       F4_730_KBC3,
3912 -       E3_730_KBC4,
3913 -
3914 -       /* USB */
3915 -       AA17_730_USB_DM,
3916 -       W16_730_USB_PU_EN,
3917 -       W17_730_USB_VBUSI,
3918 -};
3919 -
3920 -enum omap850_index {
3921 -       /* OMAP 850 keyboard */
3922 -       E2_850_KBR0,
3923 -       J7_850_KBR1,
3924 -       E1_850_KBR2,
3925 -       F3_850_KBR3,
3926 -       D2_850_KBR4,
3927 -       C2_850_KBC0,
3928 -       D3_850_KBC1,
3929 -       E4_850_KBC2,
3930 -       F4_850_KBC3,
3931 -       E3_850_KBC4,
3932 +       E2_7XX_KBR0,
3933 +       J7_7XX_KBR1,
3934 +       E1_7XX_KBR2,
3935 +       F3_7XX_KBR3,
3936 +       D2_7XX_KBR4,
3937 +       C2_7XX_KBC0,
3938 +       D3_7XX_KBC1,
3939 +       E4_7XX_KBC2,
3940 +       F4_7XX_KBC3,
3941 +       E3_7XX_KBC4,
3942
3943         /* USB */
3944 -       AA17_850_USB_DM,
3945 -       W16_850_USB_PU_EN,
3946 -       W17_850_USB_VBUSI,
3947 +       AA17_7XX_USB_DM,
3948 +       W16_7XX_USB_PU_EN,
3949 +       W17_7XX_USB_VBUSI,
3950  };
3951
3952 -
3953  enum omap1xxx_index {
3954         /* UART1 (BT_UART_GATING)*/
3955         UART1_TX = 0,
3956 diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
3957 index f8d186a..4655707 100644
3958 --- a/arch/arm/plat-omap/include/mach/omap34xx.h
3959 +++ b/arch/arm/plat-omap/include/mach/omap34xx.h
3960 @@ -74,8 +74,12 @@
3961
3962  #define OMAP34XX_IVA_INTC_BASE 0x40000000
3963  #define OMAP34XX_HSUSB_OTG_BASE        (L4_34XX_BASE + 0xAB000)
3964 -#define OMAP34XX_HSUSB_HOST_BASE       (L4_34XX_BASE + 0x64000)
3965  #define OMAP34XX_USBTLL_BASE   (L4_34XX_BASE + 0x62000)
3966 +#define OMAP34XX_UHH_CONFIG_BASE       (L4_34XX_BASE + 0x64000)
3967 +#define OMAP34XX_OHCI_BASE     (L4_34XX_BASE + 0x64400)
3968 +#define OMAP34XX_EHCI_BASE     (L4_34XX_BASE + 0x64800)
3969 +#define OMAP34XX_SR1_BASE      0x480C9000
3970 +#define OMAP34XX_SR2_BASE      0x480CB000
3971
3972  #define OMAP34XX_MAILBOX_BASE          (L4_34XX_BASE + 0x94000)
3973
3974 diff --git a/arch/arm/plat-omap/include/mach/omap44xx.h b/arch/arm/plat-omap/include/mach/omap44xx.h
3975 index b3ba5ac..3361897 100644
3976 --- a/arch/arm/plat-omap/include/mach/omap44xx.h
3977 +++ b/arch/arm/plat-omap/include/mach/omap44xx.h
3978 @@ -22,6 +22,9 @@
3979  #define L4_PER_44XX_BASE               0x48000000
3980  #define L4_EMU_44XX_BASE               0x54000000
3981  #define L3_44XX_BASE                   0x44000000
3982 +#define OMAP44XX_EMIF1_BASE            0x4c000000
3983 +#define OMAP44XX_EMIF2_BASE            0x4d000000
3984 +#define OMAP44XX_DMM_BASE              0x4e000000
3985  #define OMAP4430_32KSYNCT_BASE         0x4a304000
3986  #define OMAP4430_CM_BASE               0x4a004000
3987  #define OMAP4430_PRM_BASE              0x48306000
3988 @@ -33,14 +36,9 @@
3989  #define IRQ_SIR_IRQ                    0x0040
3990  #define OMAP44XX_GIC_DIST_BASE         0x48241000
3991  #define OMAP44XX_GIC_CPU_BASE          0x48240100
3992 -#define OMAP44XX_VA_GIC_CPU_BASE       OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
3993  #define OMAP44XX_SCU_BASE              0x48240000
3994 -#define OMAP44XX_VA_SCU_BASE           OMAP2_IO_ADDRESS(OMAP44XX_SCU_BASE)
3995  #define OMAP44XX_LOCAL_TWD_BASE                0x48240600
3996 -#define OMAP44XX_VA_LOCAL_TWD_BASE     OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE)
3997 -#define OMAP44XX_LOCAL_TWD_SIZE                0x00000100
3998  #define OMAP44XX_WKUPGEN_BASE          0x48281000
3999 -#define OMAP44XX_VA_WKUPGEN_BASE       OMAP2_IO_ADDRESS(OMAP44XX_WKUPGEN_BASE)
4000
4001  #endif /* __ASM_ARCH_OMAP44XX_H */
4002
4003 diff --git a/arch/arm/plat-omap/include/mach/omap7xx.h b/arch/arm/plat-omap/include/mach/omap7xx.h
4004 new file mode 100644
4005 index 0000000..53f5241
4006 --- /dev/null
4007 +++ b/arch/arm/plat-omap/include/mach/omap7xx.h
4008 @@ -0,0 +1,104 @@
4009 +/* arch/arm/plat-omap/include/mach/omap7xx.h
4010 + *
4011 + * Hardware definitions for TI OMAP7XX processor.
4012 + *
4013 + * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
4014 + * Adapted for omap850 by Zebediah C. McClure <zmc@lurian.net>
4015 + * Adapted for omap7xx by Alistair Buxton <a.j.buxton@gmail.com>
4016 + *
4017 + * This program is free software; you can redistribute it and/or modify it
4018 + * under the terms of the GNU General Public License as published by the
4019 + * Free Software Foundation; either version 2 of the License, or (at your
4020 + * option) any later version.
4021 + *
4022 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4023 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4024 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4025 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4026 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4027 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4028 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4029 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4030 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4031 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4032 + *
4033 + * You should have received a copy of the  GNU General Public License along
4034 + * with this program; if not, write  to the Free Software Foundation, Inc.,
4035 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4036 + */
4037 +
4038 +#ifndef __ASM_ARCH_OMAP7XX_H
4039 +#define __ASM_ARCH_OMAP7XX_H
4040 +
4041 +/*
4042 + * ----------------------------------------------------------------------------
4043 + * Base addresses
4044 + * ----------------------------------------------------------------------------
4045 + */
4046 +
4047 +/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
4048 +
4049 +#define OMAP7XX_DSP_BASE       0xE0000000
4050 +#define OMAP7XX_DSP_SIZE       0x50000
4051 +#define OMAP7XX_DSP_START      0xE0000000
4052 +
4053 +#define OMAP7XX_DSPREG_BASE    0xE1000000
4054 +#define OMAP7XX_DSPREG_SIZE    SZ_128K
4055 +#define OMAP7XX_DSPREG_START   0xE1000000
4056 +
4057 +/*
4058 + * ----------------------------------------------------------------------------
4059 + * OMAP7XX specific configuration registers
4060 + * ----------------------------------------------------------------------------
4061 + */
4062 +#define OMAP7XX_CONFIG_BASE    0xfffe1000
4063 +#define OMAP7XX_IO_CONF_0      0xfffe1070
4064 +#define OMAP7XX_IO_CONF_1      0xfffe1074
4065 +#define OMAP7XX_IO_CONF_2      0xfffe1078
4066 +#define OMAP7XX_IO_CONF_3      0xfffe107c
4067 +#define OMAP7XX_IO_CONF_4      0xfffe1080
4068 +#define OMAP7XX_IO_CONF_5      0xfffe1084
4069 +#define OMAP7XX_IO_CONF_6      0xfffe1088
4070 +#define OMAP7XX_IO_CONF_7      0xfffe108c
4071 +#define OMAP7XX_IO_CONF_8      0xfffe1090
4072 +#define OMAP7XX_IO_CONF_9      0xfffe1094
4073 +#define OMAP7XX_IO_CONF_10     0xfffe1098
4074 +#define OMAP7XX_IO_CONF_11     0xfffe109c
4075 +#define OMAP7XX_IO_CONF_12     0xfffe10a0
4076 +#define OMAP7XX_IO_CONF_13     0xfffe10a4
4077 +
4078 +#define OMAP7XX_MODE_1         0xfffe1010
4079 +#define OMAP7XX_MODE_2         0xfffe1014
4080 +
4081 +/* CSMI specials: in terms of base + offset */
4082 +#define OMAP7XX_MODE2_OFFSET   0x14
4083 +
4084 +/*
4085 + * ----------------------------------------------------------------------------
4086 + * OMAP7XX traffic controller configuration registers
4087 + * ----------------------------------------------------------------------------
4088 + */
4089 +#define OMAP7XX_FLASH_CFG_0    0xfffecc10
4090 +#define OMAP7XX_FLASH_ACFG_0   0xfffecc50
4091 +#define OMAP7XX_FLASH_CFG_1    0xfffecc14
4092 +#define OMAP7XX_FLASH_ACFG_1   0xfffecc54
4093 +
4094 +/*
4095 + * ----------------------------------------------------------------------------
4096 + * OMAP7XX DSP control registers
4097 + * ----------------------------------------------------------------------------
4098 + */
4099 +#define OMAP7XX_ICR_BASE       0xfffbb800
4100 +#define OMAP7XX_DSP_M_CTL      0xfffbb804
4101 +#define OMAP7XX_DSP_MMU_BASE   0xfffed200
4102 +
4103 +/*
4104 + * ----------------------------------------------------------------------------
4105 + * OMAP7XX PCC_UPLD configuration registers
4106 + * ----------------------------------------------------------------------------
4107 + */
4108 +#define OMAP7XX_PCC_UPLD_CTRL_BASE     (0xfffe0900)
4109 +#define OMAP7XX_PCC_UPLD_CTRL          (OMAP7XX_PCC_UPLD_CTRL_BASE + 0x00)
4110 +
4111 +#endif /*  __ASM_ARCH_OMAP7XX_H */
4112 +
4113 diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
4114 index 1c09c78..7b58a5f 100644
4115 --- a/arch/arm/plat-omap/include/mach/sdrc.h
4116 +++ b/arch/arm/plat-omap/include/mach/sdrc.h
4117 @@ -80,11 +80,11 @@
4118   */
4119
4120  #define OMAP242X_SMS_REGADDR(reg)                                      \
4121 -                       (void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
4122 +               (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg)
4123  #define OMAP243X_SMS_REGADDR(reg)                                      \
4124 -                       (void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
4125 +               (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg)
4126  #define OMAP343X_SMS_REGADDR(reg)                                      \
4127 -                       (void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
4128 +               (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg)
4129
4130  /* SMS register offsets - read/write with sms_{read,write}_reg() */
4131
4132 diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
4133 index e249186..9951345 100644
4134 --- a/arch/arm/plat-omap/include/mach/serial.h
4135 +++ b/arch/arm/plat-omap/include/mach/serial.h
4136 @@ -20,26 +20,22 @@
4137  #define OMAP_UART1_BASE                0xfffb0000
4138  #define OMAP_UART2_BASE                0xfffb0800
4139  #define OMAP_UART3_BASE                0xfffb9800
4140 -#define OMAP_MAX_NR_PORTS      3
4141  #elif defined(CONFIG_ARCH_OMAP2)
4142  /* OMAP2 serial ports */
4143  #define OMAP_UART1_BASE                0x4806a000
4144  #define OMAP_UART2_BASE                0x4806c000
4145  #define OMAP_UART3_BASE                0x4806e000
4146 -#define OMAP_MAX_NR_PORTS      3
4147  #elif defined(CONFIG_ARCH_OMAP3)
4148  /* OMAP3 serial ports */
4149  #define OMAP_UART1_BASE                0x4806a000
4150  #define OMAP_UART2_BASE                0x4806c000
4151  #define OMAP_UART3_BASE                0x49020000
4152 -#define OMAP_MAX_NR_PORTS      3
4153  #elif defined(CONFIG_ARCH_OMAP4)
4154  /* OMAP4 serial ports */
4155  #define OMAP_UART1_BASE                0x4806a000
4156  #define OMAP_UART2_BASE                0x4806c000
4157  #define OMAP_UART3_BASE                0x48020000
4158  #define OMAP_UART4_BASE                0x4806e000
4159 -#define OMAP_MAX_NR_PORTS      4
4160  #endif
4161
4162  #define OMAP1510_BASE_BAUD     (12000000/16)
4163 diff --git a/arch/arm/plat-omap/include/mach/uncompress.h b/arch/arm/plat-omap/include/mach/uncompress.h
4164 index 0814c5f..ddf7b88 100644
4165 --- a/arch/arm/plat-omap/include/mach/uncompress.h
4166 +++ b/arch/arm/plat-omap/include/mach/uncompress.h
4167 @@ -25,6 +25,7 @@ unsigned int system_rev;
4168
4169  #define UART_OMAP_MDR1         0x08    /* mode definition register */
4170  #define OMAP_ID_730            0x355F
4171 +#define OMAP_ID_850            0x362C
4172  #define ID_MASK                        0x7fff
4173  #define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
4174  #define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
4175 @@ -53,7 +54,7 @@ static void putc(int c)
4176                 /* MMU is not on, so cpu_is_omapXXXX() won't work here */
4177                 unsigned int omap_id = omap_get_id();
4178
4179 -               if (omap_id == OMAP_ID_730)
4180 +               if (omap_id == OMAP_ID_730 || omap_id == OMAP_ID_850)
4181                         shift = 0;
4182
4183                 if (check_port(uart, shift))
4184 diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h
4185 index f337e17..a4068a4 100644
4186 --- a/arch/arm/plat-omap/include/mach/usb.h
4187 +++ b/arch/arm/plat-omap/include/mach/usb.h
4188 @@ -5,6 +5,21 @@
4189
4190  #include <mach/board.h>
4191
4192 +#define OMAP3_HS_USB_PORTS     3
4193 +enum ehci_hcd_omap_mode {
4194 +       EHCI_HCD_OMAP_MODE_UNKNOWN,
4195 +       EHCI_HCD_OMAP_MODE_PHY,
4196 +       EHCI_HCD_OMAP_MODE_TLL,
4197 +};
4198 +
4199 +struct ehci_hcd_omap_platform_data {
4200 +       enum ehci_hcd_omap_mode         port_mode[OMAP3_HS_USB_PORTS];
4201 +       unsigned                        phy_reset:1;
4202 +
4203 +       /* have to be valid if phy_reset is true and portx is in phy mode */
4204 +       int     reset_gpio_port[OMAP3_HS_USB_PORTS];
4205 +};
4206 +
4207  /*-------------------------------------------------------------------------*/
4208
4209  #define OMAP1_OTG_BASE                 0xfffb0400
4210 @@ -29,6 +44,8 @@
4211
4212  extern void usb_musb_init(void);
4213
4214 +extern void usb_ehci_init(struct ehci_hcd_omap_platform_data *pdata);
4215 +
4216  #endif
4217
4218  void omap_usb_init(struct omap_usb_config *pdata);
4219 diff --git a/arch/arm/plat-omap/include/mach/vmalloc.h b/arch/arm/plat-omap/include/mach/vmalloc.h
4220 index b97dfaf..9eebf62 100644
4221 --- a/arch/arm/plat-omap/include/mach/vmalloc.h
4222 +++ b/arch/arm/plat-omap/include/mach/vmalloc.h
4223 @@ -17,5 +17,5 @@
4224   * along with this program; if not, write to the Free Software
4225   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4226   */
4227 -#define VMALLOC_END      (PAGE_OFFSET + 0x18000000)
4228 +#define VMALLOC_END      (PAGE_OFFSET + 0x38000000)
4229
4230 diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
4231 index b6defa2..93c1d53 100644
4232 --- a/arch/arm/plat-omap/io.c
4233 +++ b/arch/arm/plat-omap/io.c
4234 @@ -13,7 +13,7 @@
4235  #include <linux/io.h>
4236  #include <linux/mm.h>
4237
4238 -#include <mach/omap730.h>
4239 +#include <mach/omap7xx.h>
4240  #include <mach/omap1510.h>
4241  #include <mach/omap16xx.h>
4242  #include <mach/omap24xx.h>
4243 @@ -33,13 +33,13 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
4244                 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
4245                         return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT);
4246         }
4247 -       if (cpu_is_omap730()) {
4248 -               if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE))
4249 -                       return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START);
4250 +       if (cpu_is_omap7xx()) {
4251 +               if (BETWEEN(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_SIZE))
4252 +                       return XLATE(p, OMAP7XX_DSP_BASE, OMAP7XX_DSP_START);
4253
4254 -               if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE))
4255 -                       return XLATE(p, OMAP730_DSPREG_BASE,
4256 -                                       OMAP730_DSPREG_START);
4257 +               if (BETWEEN(p, OMAP7XX_DSPREG_BASE, OMAP7XX_DSPREG_SIZE))
4258 +                       return XLATE(p, OMAP7XX_DSPREG_BASE,
4259 +                                       OMAP7XX_DSPREG_START);
4260         }
4261         if (cpu_is_omap15xx()) {
4262                 if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE))
4263 @@ -114,6 +114,14 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
4264                         return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT);
4265                 if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE))
4266                         return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT);
4267 +               if (BETWEEN(p, OMAP44XX_EMIF1_PHYS, OMAP44XX_EMIF1_SIZE))
4268 +                       return XLATE(p, OMAP44XX_EMIF1_PHYS,            \
4269 +                                                       OMAP44XX_EMIF1_VIRT);
4270 +               if (BETWEEN(p, OMAP44XX_EMIF2_PHYS, OMAP44XX_EMIF2_SIZE))
4271 +                       return XLATE(p, OMAP44XX_EMIF2_PHYS,            \
4272 +                                                       OMAP44XX_EMIF2_VIRT);
4273 +               if (BETWEEN(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_SIZE))
4274 +                       return XLATE(p, OMAP44XX_DMM_PHYS, OMAP44XX_DMM_VIRT);
4275                 if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE))
4276                         return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT);
4277                 if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE))
4278 @@ -142,7 +150,7 @@ u8 omap_readb(u32 pa)
4279         if (cpu_class_is_omap1())
4280                 return __raw_readb(OMAP1_IO_ADDRESS(pa));
4281         else
4282 -               return __raw_readb(OMAP2_IO_ADDRESS(pa));
4283 +               return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
4284  }
4285  EXPORT_SYMBOL(omap_readb);
4286
4287 @@ -151,7 +159,7 @@ u16 omap_readw(u32 pa)
4288         if (cpu_class_is_omap1())
4289                 return __raw_readw(OMAP1_IO_ADDRESS(pa));
4290         else
4291 -               return __raw_readw(OMAP2_IO_ADDRESS(pa));
4292 +               return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
4293  }
4294  EXPORT_SYMBOL(omap_readw);
4295
4296 @@ -160,7 +168,7 @@ u32 omap_readl(u32 pa)
4297         if (cpu_class_is_omap1())
4298                 return __raw_readl(OMAP1_IO_ADDRESS(pa));
4299         else
4300 -               return __raw_readl(OMAP2_IO_ADDRESS(pa));
4301 +               return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
4302  }
4303  EXPORT_SYMBOL(omap_readl);
4304
4305 @@ -169,7 +177,7 @@ void omap_writeb(u8 v, u32 pa)
4306         if (cpu_class_is_omap1())
4307                 __raw_writeb(v, OMAP1_IO_ADDRESS(pa));
4308         else
4309 -               __raw_writeb(v, OMAP2_IO_ADDRESS(pa));
4310 +               __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
4311  }
4312  EXPORT_SYMBOL(omap_writeb);
4313
4314 @@ -178,7 +186,7 @@ void omap_writew(u16 v, u32 pa)
4315         if (cpu_class_is_omap1())
4316                 __raw_writew(v, OMAP1_IO_ADDRESS(pa));
4317         else
4318 -               __raw_writew(v, OMAP2_IO_ADDRESS(pa));
4319 +               __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
4320  }
4321  EXPORT_SYMBOL(omap_writew);
4322
4323 @@ -187,6 +195,6 @@ void omap_writel(u32 v, u32 pa)
4324         if (cpu_class_is_omap1())
4325                 __raw_writel(v, OMAP1_IO_ADDRESS(pa));
4326         else
4327 -               __raw_writel(v, OMAP2_IO_ADDRESS(pa));
4328 +               __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
4329  }
4330  EXPORT_SYMBOL(omap_writel);
4331 diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
4332 index 2c409fc..12513f4 100644
4333 --- a/arch/arm/plat-omap/omap_device.c
4334 +++ b/arch/arm/plat-omap/omap_device.c
4335 @@ -103,21 +103,6 @@
4336  /* Private functions */
4337
4338  /**
4339 - * _read_32ksynct - read the OMAP 32K sync timer
4340 - *
4341 - * Returns the current value of the 32KiHz synchronization counter.
4342 - * XXX this should be generalized to simply read the system clocksource.
4343 - * XXX this should be moved to a separate synctimer32k.c file
4344 - */
4345 -static u32 _read_32ksynct(void)
4346 -{
4347 -       if (!cpu_class_is_omap2())
4348 -               BUG();
4349 -
4350 -       return __raw_readl(OMAP2_IO_ADDRESS(OMAP_32KSYNCT_BASE + 0x010));
4351 -}
4352 -
4353 -/**
4354   * _omap_device_activate - increase device readiness
4355   * @od: struct omap_device *
4356   * @ignore_lat: increase to latency target (0) or full readiness (1)?
4357 @@ -133,13 +118,13 @@ static u32 _read_32ksynct(void)
4358   */
4359  static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
4360  {
4361 -       u32 a, b;
4362 +       struct timespec a, b, c;
4363
4364         pr_debug("omap_device: %s: activating\n", od->pdev.name);
4365
4366         while (od->pm_lat_level > 0) {
4367                 struct omap_device_pm_latency *odpl;
4368 -               int act_lat = 0;
4369 +               unsigned long long act_lat = 0;
4370
4371                 od->pm_lat_level--;
4372
4373 @@ -149,20 +134,22 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
4374                     (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
4375                         break;
4376
4377 -               a = _read_32ksynct();
4378 +               getnstimeofday(&a);
4379
4380                 /* XXX check return code */
4381                 odpl->activate_func(od);
4382
4383 -               b = _read_32ksynct();
4384 +               getnstimeofday(&b);
4385
4386 -               act_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
4387 +               c = timespec_sub(b, a);
4388 +               act_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
4389
4390                 pr_debug("omap_device: %s: pm_lat %d: activate: elapsed time "
4391 -                        "%d usec\n", od->pdev.name, od->pm_lat_level, act_lat);
4392 +                        "%llu usec\n", od->pdev.name, od->pm_lat_level,
4393 +                        act_lat);
4394
4395                 WARN(act_lat > odpl->activate_lat, "omap_device: %s.%d: "
4396 -                    "activate step %d took longer than expected (%d > %d)\n",
4397 +                    "activate step %d took longer than expected (%llu > %d)\n",
4398                      od->pdev.name, od->pdev.id, od->pm_lat_level,
4399                      act_lat, odpl->activate_lat);
4400
4401 @@ -188,13 +175,13 @@ static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
4402   */
4403  static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
4404  {
4405 -       u32 a, b;
4406 +       struct timespec a, b, c;
4407
4408         pr_debug("omap_device: %s: deactivating\n", od->pdev.name);
4409
4410         while (od->pm_lat_level < od->pm_lats_cnt) {
4411                 struct omap_device_pm_latency *odpl;
4412 -               int deact_lat = 0;
4413 +               unsigned long long deact_lat = 0;
4414
4415                 odpl = od->pm_lats + od->pm_lat_level;
4416
4417 @@ -203,23 +190,24 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
4418                      od->_dev_wakeup_lat_limit))
4419                         break;
4420
4421 -               a = _read_32ksynct();
4422 +               getnstimeofday(&a);
4423
4424                 /* XXX check return code */
4425                 odpl->deactivate_func(od);
4426
4427 -               b = _read_32ksynct();
4428 +               getnstimeofday(&b);
4429
4430 -               deact_lat = (b - a) >> 15; /* 32KiHz cycles to microseconds */
4431 +               c = timespec_sub(b, a);
4432 +               deact_lat = timespec_to_ns(&c) * NSEC_PER_USEC;
4433
4434                 pr_debug("omap_device: %s: pm_lat %d: deactivate: elapsed time "
4435 -                        "%d usec\n", od->pdev.name, od->pm_lat_level,
4436 +                        "%llu usec\n", od->pdev.name, od->pm_lat_level,
4437                          deact_lat);
4438
4439                 WARN(deact_lat > odpl->deactivate_lat, "omap_device: %s.%d: "
4440 -                    "deactivate step %d took longer than expected (%d > %d)\n",
4441 -                    od->pdev.name, od->pdev.id, od->pm_lat_level,
4442 -                    deact_lat, odpl->deactivate_lat);
4443 +                    "deactivate step %d took longer than expected "
4444 +                    "(%llu > %d)\n", od->pdev.name, od->pdev.id,
4445 +                    od->pm_lat_level, deact_lat, odpl->deactivate_lat);
4446
4447                 od->dev_wakeup_lat += odpl->activate_lat;
4448
4449 diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
4450 index 75d1f26..4144f81 100644
4451 --- a/arch/arm/plat-omap/sram.c
4452 +++ b/arch/arm/plat-omap/sram.c
4453 @@ -41,14 +41,14 @@
4454  #define OMAP1_SRAM_VA          VMALLOC_END
4455  #define OMAP2_SRAM_PA          0x40200000
4456  #define OMAP2_SRAM_PUB_PA      0x4020f800
4457 -#define OMAP2_SRAM_VA          0xe3000000
4458 +#define OMAP2_SRAM_VA          0xfe400000
4459  #define OMAP2_SRAM_PUB_VA      (OMAP2_SRAM_VA + 0x800)
4460  #define OMAP3_SRAM_PA           0x40200000
4461 -#define OMAP3_SRAM_VA           0xe3000000
4462 +#define OMAP3_SRAM_VA           0xfe400000
4463  #define OMAP3_SRAM_PUB_PA       0x40208000
4464  #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
4465  #define OMAP4_SRAM_PA          0x40200000              /*0x402f0000*/
4466 -#define OMAP4_SRAM_VA          0xd7000000              /*0xd70f0000*/
4467 +#define OMAP4_SRAM_VA          0xfe400000              /*0xfe4f0000*/
4468
4469  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
4470  #define SRAM_BOOTLOADER_SZ     0x00
4471 @@ -56,16 +56,16 @@
4472  #define SRAM_BOOTLOADER_SZ     0x80
4473  #endif
4474
4475 -#define OMAP24XX_VA_REQINFOPERM0       OMAP2_IO_ADDRESS(0x68005048)
4476 -#define OMAP24XX_VA_READPERM0          OMAP2_IO_ADDRESS(0x68005050)
4477 -#define OMAP24XX_VA_WRITEPERM0         OMAP2_IO_ADDRESS(0x68005058)
4478 +#define OMAP24XX_VA_REQINFOPERM0       OMAP2_L3_IO_ADDRESS(0x68005048)
4479 +#define OMAP24XX_VA_READPERM0          OMAP2_L3_IO_ADDRESS(0x68005050)
4480 +#define OMAP24XX_VA_WRITEPERM0         OMAP2_L3_IO_ADDRESS(0x68005058)
4481
4482 -#define OMAP34XX_VA_REQINFOPERM0       OMAP2_IO_ADDRESS(0x68012848)
4483 -#define OMAP34XX_VA_READPERM0          OMAP2_IO_ADDRESS(0x68012850)
4484 -#define OMAP34XX_VA_WRITEPERM0         OMAP2_IO_ADDRESS(0x68012858)
4485 -#define OMAP34XX_VA_ADDR_MATCH2                OMAP2_IO_ADDRESS(0x68012880)
4486 -#define OMAP34XX_VA_SMS_RG_ATT0                OMAP2_IO_ADDRESS(0x6C000048)
4487 -#define OMAP34XX_VA_CONTROL_STAT       OMAP2_IO_ADDRESS(0x480022F0)
4488 +#define OMAP34XX_VA_REQINFOPERM0       OMAP2_L3_IO_ADDRESS(0x68012848)
4489 +#define OMAP34XX_VA_READPERM0          OMAP2_L3_IO_ADDRESS(0x68012850)
4490 +#define OMAP34XX_VA_WRITEPERM0         OMAP2_L3_IO_ADDRESS(0x68012858)
4491 +#define OMAP34XX_VA_ADDR_MATCH2                OMAP2_L3_IO_ADDRESS(0x68012880)
4492 +#define OMAP34XX_VA_SMS_RG_ATT0                OMAP2_L3_IO_ADDRESS(0x6C000048)
4493 +#define OMAP34XX_VA_CONTROL_STAT       OMAP2_L4_IO_ADDRESS(0x480022F0)
4494
4495  #define GP_DEVICE              0x300
4496
4497 diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
4498 index 509f2ed..3c40b85 100644
4499 --- a/arch/arm/plat-omap/usb.c
4500 +++ b/arch/arm/plat-omap/usb.c
4501 @@ -614,8 +614,8 @@ omap_otg_init(struct omap_usb_config *config)
4502         if (config->otg || config->register_host) {
4503                 syscon &= ~HST_IDLE_EN;
4504                 ohci_device.dev.platform_data = config;
4505 -               if (cpu_is_omap730())
4506 -                       ohci_resources[1].start = INT_730_USB_HHC_1;
4507 +               if (cpu_is_omap7xx())
4508 +                       ohci_resources[1].start = INT_7XX_USB_HHC_1;
4509                 status = platform_device_register(&ohci_device);
4510                 if (status)
4511                         pr_debug("can't register OHCI device, %d\n", status);
4512 @@ -626,8 +626,8 @@ omap_otg_init(struct omap_usb_config *config)
4513         if (config->otg) {
4514                 syscon &= ~OTG_IDLE_EN;
4515                 otg_device.dev.platform_data = config;
4516 -               if (cpu_is_omap730())
4517 -                       otg_resources[1].start = INT_730_USB_OTG;
4518 +               if (cpu_is_omap7xx())
4519 +                       otg_resources[1].start = INT_7XX_USB_OTG;
4520                 status = platform_device_register(&otg_device);
4521                 if (status)
4522                         pr_debug("can't register OTG device, %d\n", status);
4523 @@ -731,7 +731,7 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
4524
4525  void __init omap_usb_init(struct omap_usb_config *pdata)
4526  {
4527 -       if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx())
4528 +       if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
4529                 omap_otg_init(pdata);
4530         else if (cpu_is_omap15xx())
4531                 omap_1510_usb_init(pdata);
4532 diff --git a/drivers/Makefile b/drivers/Makefile
4533 index 6ee53c7..086857c 100644
4534 --- a/drivers/Makefile
4535 +++ b/drivers/Makefile
4536 @@ -72,7 +72,7 @@ obj-$(CONFIG_GAMEPORT)                += input/gameport/
4537  obj-$(CONFIG_INPUT)            += input/
4538  obj-$(CONFIG_I2O)              += message/
4539  obj-$(CONFIG_RTC_LIB)          += rtc/
4540 -obj-y                          += i2c/ media/
4541 +obj-y                          += i2c/ media/ cbus/
4542  obj-$(CONFIG_PPS)              += pps/
4543  obj-$(CONFIG_W1)               += w1/
4544  obj-$(CONFIG_POWER_SUPPLY)     += power/
4545 diff --git a/drivers/cbus/Kconfig b/drivers/cbus/Kconfig
4546 new file mode 100644
4547 index 0000000..25f8039
4548 --- /dev/null
4549 +++ b/drivers/cbus/Kconfig
4550 @@ -0,0 +1,89 @@
4551 +#
4552 +# CBUS device configuration
4553 +#
4554 +
4555 +menu "CBUS support"
4556 +
4557 +config CBUS
4558 +       depends on ARCH_OMAP
4559 +       bool "CBUS support on OMAP"
4560 +       ---help---
4561 +         CBUS is a proprietary serial protocol by Nokia.  It is mainly
4562 +         used for accessing Energy Management auxiliary chips.
4563 +
4564 +         If you want CBUS support, you should say Y here.
4565 +
4566 +config CBUS_TAHVO
4567 +       depends on CBUS
4568 +       bool "Support for Tahvo"
4569 +       ---help---
4570 +         Tahvo is a mixed signal ASIC with some system features
4571 +
4572 +         If you want Tahvo support, you should say Y here.
4573 +
4574 +config CBUS_TAHVO_USER
4575 +       depends on CBUS_TAHVO
4576 +       bool "Support for Tahvo user space functions"
4577 +       ---help---
4578 +         If you want support for Tahvo's user space read/write etc. functions,
4579 +         you should say Y here.
4580 +
4581 +config CBUS_TAHVO_USB
4582 +       depends on CBUS_TAHVO && USB
4583 +       tristate "Support for Tahvo USB transceiver"
4584 +       ---help---
4585 +         If you want Tahvo support for USB transceiver, say Y or M here.
4586 +
4587 +config CBUS_TAHVO_USB_HOST_BY_DEFAULT
4588 +       depends on CBUS_TAHVO_USB && USB_OTG
4589 +       boolean "Device in USB host mode by default"
4590 +       ---help---
4591 +         Say Y here, if you want the device to enter USB host mode
4592 +         by default on bootup.
4593 +
4594 +config CBUS_RETU
4595 +       depends on CBUS
4596 +       bool "Support for Retu"
4597 +       ---help---
4598 +         Retu is a mixed signal ASIC with some system features
4599 +
4600 +         If you want Retu support, you should say Y here.
4601 +
4602 +config CBUS_RETU_USER
4603 +       depends on CBUS_RETU
4604 +       bool "Support for Retu user space functions"
4605 +       ---help---
4606 +         If you want support for Retu's user space read/write etc. functions,
4607 +         you should say Y here.
4608 +
4609 +config CBUS_RETU_POWERBUTTON
4610 +       depends on CBUS_RETU
4611 +       bool "Support for Retu power button"
4612 +       ---help---
4613 +         The power button on Nokia 770 is connected to the Retu ASIC.
4614 +
4615 +         If you want support for the Retu power button, you should say Y here.
4616 +
4617 +config CBUS_RETU_RTC
4618 +       depends on CBUS_RETU && SYSFS
4619 +       tristate "Support for Retu pseudo-RTC"
4620 +       ---help---
4621 +         Say Y here if you want support for the device that alleges to be an
4622 +         RTC in Retu. This will expose a sysfs interface for it.
4623 +
4624 +config CBUS_RETU_WDT
4625 +       depends on CBUS_RETU && SYSFS
4626 +       tristate "Support for Retu watchdog timer"
4627 +       ---help---
4628 +         Say Y here if you want support for the watchdog in Retu. This will
4629 +         expose a sysfs interface to grok it.
4630 +
4631 +config CBUS_RETU_HEADSET
4632 +       depends on CBUS_RETU && SYSFS
4633 +       tristate "Support for headset detection with Retu/Vilma"
4634 +       ---help---
4635 +         Say Y here if you want support detecting a headset that's connected
4636 +         to Retu/Vilma. Detection state and events are exposed through
4637 +         sysfs.
4638 +
4639 +endmenu
4640 diff --git a/drivers/cbus/Makefile b/drivers/cbus/Makefile
4641 new file mode 100644
4642 index 0000000..347c2a4
4643 --- /dev/null
4644 +++ b/drivers/cbus/Makefile
4645 @@ -0,0 +1,14 @@
4646 +#
4647 +# Makefile for CBUS.
4648 +#
4649 +
4650 +obj-$(CONFIG_CBUS)             += cbus.o
4651 +obj-$(CONFIG_CBUS_TAHVO)       += tahvo.o
4652 +obj-$(CONFIG_CBUS_RETU)                += retu.o
4653 +obj-$(CONFIG_CBUS_TAHVO_USB)   += tahvo-usb.o
4654 +obj-$(CONFIG_CBUS_RETU_POWERBUTTON) += retu-pwrbutton.o
4655 +obj-$(CONFIG_CBUS_RETU_RTC)    += retu-rtc.o
4656 +obj-$(CONFIG_CBUS_RETU_WDT)    += retu-wdt.o
4657 +obj-$(CONFIG_CBUS_TAHVO_USER)  += tahvo-user.o
4658 +obj-$(CONFIG_CBUS_RETU_USER)   += retu-user.o
4659 +obj-$(CONFIG_CBUS_RETU_HEADSET)        += retu-headset.o
4660 diff --git a/drivers/cbus/cbus.c b/drivers/cbus/cbus.c
4661 new file mode 100644
4662 index 0000000..774acce
4663 --- /dev/null
4664 +++ b/drivers/cbus/cbus.c
4665 @@ -0,0 +1,293 @@
4666 +/*
4667 + * drivers/cbus/cbus.c
4668 + *
4669 + * Support functions for CBUS serial protocol
4670 + *
4671 + * Copyright (C) 2004, 2005 Nokia Corporation
4672 + *
4673 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
4674 + *           David Weinehall <david.weinehall@nokia.com>, and
4675 + *           Mikko Ylinen <mikko.k.ylinen@nokia.com>
4676 + *
4677 + * This file is subject to the terms and conditions of the GNU General
4678 + * Public License. See the file "COPYING" in the main directory of this
4679 + * archive for more details.
4680 + *
4681 + * This program is distributed in the hope that it will be useful,
4682 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4683 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4684 + * GNU General Public License for more details.
4685 + *
4686 + * You should have received a copy of the GNU General Public License
4687 + * along with this program; if not, write to the Free Software
4688 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4689 + */
4690 +
4691 +#include <linux/device.h>
4692 +#include <linux/init.h>
4693 +#include <linux/kernel.h>
4694 +#include <linux/delay.h>
4695 +#include <linux/spinlock.h>
4696 +#include <linux/gpio.h>
4697 +
4698 +#include <mach/board.h>
4699 +#include <mach/board-nokia.h>
4700 +
4701 +#include <asm/io.h>
4702 +
4703 +#include "cbus.h"
4704 +
4705 +struct cbus_host *cbus_host = NULL;
4706 +
4707 +#ifdef CONFIG_ARCH_OMAP1
4708 +/* We use our own MPUIO functions to get closer to 1MHz bus speed */
4709 +
4710 +static inline void cbus_set_gpio_direction(u32 base, int mpuio, int is_input)
4711 +{
4712 +       u16 w;
4713 +
4714 +       mpuio &= 0x0f;
4715 +       w = __raw_readw(base + OMAP_MPUIO_IO_CNTL);
4716 +       if (is_input)
4717 +               w |= 1 << mpuio;
4718 +       else
4719 +               w &= ~(1 << mpuio);
4720 +       __raw_writew(w, base + OMAP_MPUIO_IO_CNTL);
4721 +
4722 +}
4723 +
4724 +static inline void cbus_set_gpio_dataout(u32 base, int mpuio, int enable)
4725 +{
4726 +       u16 w;
4727 +
4728 +       mpuio &= 0x0f;
4729 +       w = __raw_readw(base + OMAP_MPUIO_OUTPUT);
4730 +       if (enable)
4731 +               w |= 1 << mpuio;
4732 +       else
4733 +               w &= ~(1 << mpuio);
4734 +       __raw_writew(w, base + OMAP_MPUIO_OUTPUT);
4735 +}
4736 +
4737 +static inline int cbus_get_gpio_datain(u32 base, int mpuio)
4738 +{
4739 +       mpuio &= 0x0f;
4740 +
4741 +       return (__raw_readw(base + OMAP_MPUIO_INPUT_LATCH) & (1 << mpuio)) != 0;
4742 +}
4743 +
4744 +static void cbus_send_bit(struct cbus_host *host, u32 base, int bit,
4745 +                         int set_to_input)
4746 +{
4747 +       cbus_set_gpio_dataout(base, host->dat_gpio, bit ? 1 : 0);
4748 +       cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4749 +
4750 +       /* The data bit is read on the rising edge of CLK */
4751 +       if (set_to_input)
4752 +               cbus_set_gpio_direction(base, host->dat_gpio, 1);
4753 +
4754 +       cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4755 +}
4756 +
4757 +static u8 cbus_receive_bit(struct cbus_host *host, u32 base)
4758 +{
4759 +       u8 ret;
4760 +
4761 +       cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4762 +       ret = cbus_get_gpio_datain(base, host->dat_gpio);
4763 +       cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4764 +
4765 +       return ret;
4766 +}
4767 +
4768 +#define cbus_output(base, gpio, val)   cbus_set_gpio_direction(base, gpio, 0)
4769 +
4770 +#else
4771 +
4772 +#define cbus_output(base, gpio, val)   gpio_direction_output(gpio, val)
4773 +#define cbus_set_gpio_dataout(base, gpio, enable) gpio_set_value(gpio, enable)
4774 +#define cbus_get_gpio_datain(base, int, gpio) gpio_get_value(gpio)
4775 +
4776 +static void _cbus_send_bit(struct cbus_host *host, int bit, int set_to_input)
4777 +{
4778 +       gpio_set_value(host->dat_gpio, bit ? 1 : 0);
4779 +       gpio_set_value(host->clk_gpio, 1);
4780 +
4781 +       /* The data bit is read on the rising edge of CLK */
4782 +       if (set_to_input)
4783 +               gpio_direction_input(host->dat_gpio);
4784 +
4785 +       gpio_set_value(host->clk_gpio, 0);
4786 +}
4787 +
4788 +static u8 _cbus_receive_bit(struct cbus_host *host)
4789 +{
4790 +       u8 ret;
4791 +
4792 +       gpio_set_value(host->clk_gpio, 1);
4793 +       ret = gpio_get_value(host->dat_gpio);
4794 +       gpio_set_value(host->clk_gpio, 0);
4795 +
4796 +       return ret;
4797 +}
4798 +
4799 +#define cbus_send_bit(host, base, bit, set_to_input) _cbus_send_bit(host, bit, set_to_input)
4800 +#define cbus_receive_bit(host, base) _cbus_receive_bit(host)
4801 +
4802 +#endif
4803 +
4804 +static int cbus_transfer(struct cbus_host *host, int dev, int reg, int data)
4805 +{
4806 +       int i;
4807 +       int is_read = 0;
4808 +       unsigned long flags;
4809 +       u32 base;
4810 +
4811 +#ifdef CONFIG_ARCH_OMAP1
4812 +       base = OMAP1_IO_ADDRESS(OMAP_MPUIO_BASE);
4813 +#else
4814 +       base = 0;
4815 +#endif
4816 +
4817 +       if (data < 0)
4818 +               is_read = 1;
4819 +
4820 +       /* We don't want interrupts disturbing our transfer */
4821 +       spin_lock_irqsave(&host->lock, flags);
4822 +
4823 +       /* Reset state and start of transfer, SEL stays down during transfer */
4824 +       cbus_set_gpio_dataout(base, host->sel_gpio, 0);
4825 +
4826 +       /* Set the DAT pin to output */
4827 +       cbus_output(base, host->dat_gpio, 1);
4828 +
4829 +       /* Send the device address */
4830 +       for (i = 3; i > 0; i--)
4831 +               cbus_send_bit(host, base, dev & (1 << (i - 1)), 0);
4832 +
4833 +       /* Send the rw flag */
4834 +       cbus_send_bit(host, base, is_read, 0);
4835 +
4836 +       /* Send the register address */
4837 +       for (i = 5; i > 0; i--) {
4838 +               int set_to_input = 0;
4839 +
4840 +               if (is_read && i == 1)
4841 +                       set_to_input = 1;
4842 +
4843 +               cbus_send_bit(host, base, reg & (1 << (i - 1)), set_to_input);
4844 +       }
4845 +
4846 +       if (!is_read) {
4847 +               for (i = 16; i > 0; i--)
4848 +                       cbus_send_bit(host, base, data & (1 << (i - 1)), 0);
4849 +       } else {
4850 +               cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4851 +               data = 0;
4852 +
4853 +               for (i = 16; i > 0; i--) {
4854 +                       u8 bit = cbus_receive_bit(host, base);
4855 +
4856 +                       if (bit)
4857 +                               data |= 1 << (i - 1);
4858 +               }
4859 +       }
4860 +
4861 +       /* Indicate end of transfer, SEL goes up until next transfer */
4862 +       cbus_set_gpio_dataout(base, host->sel_gpio, 1);
4863 +       cbus_set_gpio_dataout(base, host->clk_gpio, 1);
4864 +       cbus_set_gpio_dataout(base, host->clk_gpio, 0);
4865 +
4866 +       spin_unlock_irqrestore(&host->lock, flags);
4867 +
4868 +       return is_read ? data : 0;
4869 +}
4870 +
4871 +/*
4872 + * Read a given register from the device
4873 + */
4874 +int cbus_read_reg(struct cbus_host *host, int dev, int reg)
4875 +{
4876 +       return cbus_host ? cbus_transfer(host, dev, reg, -1) : -ENODEV;
4877 +}
4878 +
4879 +/*
4880 + * Write to a given register of the device
4881 + */
4882 +int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val)
4883 +{
4884 +       return cbus_host ? cbus_transfer(host, dev, reg, (int)val) : -ENODEV;
4885 +}
4886 +
4887 +int __init cbus_bus_init(void)
4888 +{
4889 +       const struct omap_cbus_config * cbus_config;
4890 +       struct cbus_host *chost;
4891 +       int ret;
4892 +
4893 +       chost = kmalloc(sizeof (*chost), GFP_KERNEL);
4894 +       if (chost == NULL)
4895 +               return -ENOMEM;
4896 +
4897 +       memset(chost, 0, sizeof (*chost));
4898 +
4899 +       spin_lock_init(&chost->lock);
4900 +
4901 +       cbus_config = omap_get_config(OMAP_TAG_CBUS, struct omap_cbus_config);
4902 +
4903 +       if (cbus_config == NULL) {
4904 +               printk(KERN_ERR "cbus: Unable to retrieve config data\n");
4905 +               return -ENODATA;
4906 +       }
4907 +
4908 +       chost->clk_gpio = cbus_config->clk_gpio;
4909 +       chost->dat_gpio = cbus_config->dat_gpio;
4910 +       chost->sel_gpio = cbus_config->sel_gpio;
4911 +
4912 +#ifdef CONFIG_ARCH_OMAP1
4913 +       if (!OMAP_GPIO_IS_MPUIO(chost->clk_gpio) ||
4914 +           !OMAP_GPIO_IS_MPUIO(chost->dat_gpio) ||
4915 +           !OMAP_GPIO_IS_MPUIO(chost->sel_gpio)) {
4916 +               printk(KERN_ERR "cbus: Only MPUIO pins supported\n");
4917 +               ret = -ENODEV;
4918 +               goto exit1;
4919 +       }
4920 +#endif
4921 +
4922 +       if ((ret = gpio_request(chost->clk_gpio, "CBUS clk")) < 0)
4923 +               goto exit1;
4924 +
4925 +       if ((ret = gpio_request(chost->dat_gpio, "CBUS data")) < 0)
4926 +               goto exit2;
4927 +
4928 +       if ((ret = gpio_request(chost->sel_gpio, "CBUS sel")) < 0)
4929 +               goto exit3;
4930 +
4931 +       gpio_direction_output(chost->clk_gpio, 0);
4932 +       gpio_direction_input(chost->dat_gpio);
4933 +       gpio_direction_output(chost->sel_gpio, 1);
4934 +
4935 +       gpio_set_value(chost->clk_gpio, 1);
4936 +       gpio_set_value(chost->clk_gpio, 0);
4937 +
4938 +       cbus_host = chost;
4939 +
4940 +       return 0;
4941 +exit3:
4942 +       gpio_free(chost->dat_gpio);
4943 +exit2:
4944 +       gpio_free(chost->clk_gpio);
4945 +exit1:
4946 +       kfree(chost);
4947 +       return ret;
4948 +}
4949 +
4950 +subsys_initcall(cbus_bus_init);
4951 +
4952 +EXPORT_SYMBOL(cbus_host);
4953 +EXPORT_SYMBOL(cbus_read_reg);
4954 +EXPORT_SYMBOL(cbus_write_reg);
4955 +
4956 +MODULE_DESCRIPTION("CBUS serial protocol");
4957 +MODULE_LICENSE("GPL");
4958 +MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen");
4959 diff --git a/drivers/cbus/cbus.h b/drivers/cbus/cbus.h
4960 new file mode 100644
4961 index 0000000..957224c
4962 --- /dev/null
4963 +++ b/drivers/cbus/cbus.h
4964 @@ -0,0 +1,36 @@
4965 +/*
4966 + * drivers/cbus/cbus.h
4967 + *
4968 + * Copyright (C) 2004, 2005 Nokia Corporation
4969 + *
4970 + * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
4971 + *           David Weinehall <david.weinehall@nokia.com>
4972 + *
4973 + * This file is subject to the terms and conditions of the GNU General
4974 + * Public License. See the file "COPYING" in the main directory of this
4975 + * archive for more details.
4976 + *
4977 + * This program is distributed in the hope that it will be useful,
4978 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4979 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4980 + * GNU General Public License for more details.
4981 + *
4982 + * You should have received a copy of the GNU General Public License
4983 + * along with this program; if not, write to the Free Software
4984 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
4985 + */
4986 +
4987 +#ifndef __DRIVERS_CBUS_CBUS_H
4988 +#define __DRIVERS_CBUS_CBUS_H
4989 +
4990 +struct cbus_host {
4991 +       int clk_gpio, dat_gpio, sel_gpio;
4992 +        spinlock_t lock;
4993 +};
4994 +
4995 +extern struct cbus_host *cbus_host;
4996 +
4997 +extern int cbus_read_reg(struct cbus_host *host, int dev, int reg);
4998 +extern int cbus_write_reg(struct cbus_host *host, int dev, int reg, u16 val);
4999 +
5000 +#endif /* __DRIVERS_CBUS_CBUS_H */
5001 diff --git a/drivers/cbus/retu-headset.c b/drivers/cbus/retu-headset.c
5002 new file mode 100644
5003 index 0000000..e798bc2
5004 --- /dev/null
5005 +++ b/drivers/cbus/retu-headset.c
5006 @@ -0,0 +1,355 @@
5007 +/**
5008 + * Retu/Vilma headset detection
5009 + *
5010 + * Copyright (C) 2006 Nokia Corporation
5011 + *
5012 + * Written by Juha Yrjölä
5013 + *
5014 + * This file is subject to the terms and conditions of the GNU General
5015 + * Public License. See the file "COPYING" in the main directory of this
5016 + * archive for more details.
5017 + *
5018 + * This program is distributed in the hope that it will be useful,
5019 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5020 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5021 + * GNU General Public License for more details.
5022 + *
5023 + * You should have received a copy of the GNU General Public License
5024 + * along with this program; if not, write to the Free Software
5025 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5026 + */
5027 +
5028 +#include <linux/module.h>
5029 +#include <linux/init.h>
5030 +#include <linux/kernel.h>
5031 +#include <linux/delay.h>
5032 +#include <linux/input.h>
5033 +#include <linux/platform_device.h>
5034 +
5035 +#include "retu.h"
5036 +
5037 +#define RETU_ADC_CHANNEL_HOOKDET       0x05
5038 +
5039 +#define RETU_HEADSET_KEY               KEY_PHONE
5040 +
5041 +struct retu_headset {
5042 +       spinlock_t                      lock;
5043 +       struct mutex                    mutex;
5044 +       struct platform_device          *pdev;
5045 +       struct input_dev                *idev;
5046 +       unsigned                        bias_enabled;
5047 +       unsigned                        detection_enabled;
5048 +       unsigned                        pressed;
5049 +       struct timer_list               enable_timer;
5050 +       struct timer_list               detect_timer;
5051 +};
5052 +
5053 +static void retu_headset_set_bias(int enable)
5054 +{
5055 +       if (enable) {
5056 +               retu_set_clear_reg_bits(RETU_REG_AUDTXR,
5057 +                                       (1 << 0) | (1 << 1), 0);
5058 +               msleep(2);
5059 +               retu_set_clear_reg_bits(RETU_REG_AUDTXR, 1 << 3, 0);
5060 +       } else {
5061 +               retu_set_clear_reg_bits(RETU_REG_AUDTXR, 0,
5062 +                                       (1 << 0) | (1 << 1) | (1 << 3));
5063 +       }
5064 +}
5065 +
5066 +static void retu_headset_enable(struct retu_headset *hs)
5067 +{
5068 +       mutex_lock(&hs->mutex);
5069 +       if (!hs->bias_enabled) {
5070 +               hs->bias_enabled = 1;
5071 +               retu_headset_set_bias(1);
5072 +       }
5073 +       mutex_unlock(&hs->mutex);
5074 +}
5075 +
5076 +static void retu_headset_disable(struct retu_headset *hs)
5077 +{
5078 +       mutex_lock(&hs->mutex);
5079 +       if (hs->bias_enabled) {
5080 +               hs->bias_enabled = 0;
5081 +               retu_headset_set_bias(0);
5082 +       }
5083 +       mutex_unlock(&hs->mutex);
5084 +}
5085 +
5086 +static void retu_headset_det_enable(struct retu_headset *hs)
5087 +{
5088 +       mutex_lock(&hs->mutex);
5089 +       if (!hs->detection_enabled) {
5090 +               hs->detection_enabled = 1;
5091 +               retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0);
5092 +               retu_enable_irq(RETU_INT_HOOK);
5093 +       }
5094 +       mutex_unlock(&hs->mutex);
5095 +}
5096 +
5097 +static void retu_headset_det_disable(struct retu_headset *hs)
5098 +{
5099 +       unsigned long flags;
5100 +
5101 +       mutex_lock(&hs->mutex);
5102 +       if (hs->detection_enabled) {
5103 +               hs->detection_enabled = 0;
5104 +               retu_disable_irq(RETU_INT_HOOK);
5105 +               del_timer_sync(&hs->enable_timer);
5106 +               del_timer_sync(&hs->detect_timer);
5107 +               spin_lock_irqsave(&hs->lock, flags);
5108 +               if (hs->pressed)
5109 +                       input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
5110 +               spin_unlock_irqrestore(&hs->lock, flags);
5111 +               retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8));
5112 +       }
5113 +       mutex_unlock(&hs->mutex);
5114 +}
5115 +
5116 +static ssize_t retu_headset_hookdet_show(struct device *dev,
5117 +                                        struct device_attribute *attr,
5118 +                                        char *buf)
5119 +{
5120 +       int val;
5121 +
5122 +       val = retu_read_adc(RETU_ADC_CHANNEL_HOOKDET);
5123 +       return sprintf(buf, "%d\n", val);
5124 +}
5125 +
5126 +static DEVICE_ATTR(hookdet, S_IRUGO, retu_headset_hookdet_show, NULL);
5127 +
5128 +static ssize_t retu_headset_enable_show(struct device *dev,
5129 +                                       struct device_attribute *attr,
5130 +                                       char *buf)
5131 +{
5132 +       struct retu_headset *hs = dev_get_drvdata(dev);
5133 +
5134 +       return sprintf(buf, "%u\n", hs->bias_enabled);
5135 +}
5136 +
5137 +static ssize_t retu_headset_enable_store(struct device *dev,
5138 +                                        struct device_attribute *attr,
5139 +                                        const char *buf, size_t count)
5140 +{
5141 +       struct retu_headset *hs = dev_get_drvdata(dev);
5142 +       int enable;
5143 +
5144 +       if (sscanf(buf, "%u", &enable) != 1)
5145 +               return -EINVAL;
5146 +       if (enable)
5147 +               retu_headset_enable(hs);
5148 +       else
5149 +               retu_headset_disable(hs);
5150 +       return count;
5151 +}
5152 +
5153 +static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR | S_IWGRP,
5154 +                  retu_headset_enable_show, retu_headset_enable_store);
5155 +
5156 +static ssize_t retu_headset_enable_det_show(struct device *dev,
5157 +                                           struct device_attribute *attr,
5158 +                                           char *buf)
5159 +{
5160 +       struct retu_headset *hs = dev_get_drvdata(dev);
5161 +
5162 +       return sprintf(buf, "%u\n", hs->detection_enabled);
5163 +}
5164 +
5165 +static ssize_t retu_headset_enable_det_store(struct device *dev,
5166 +                                            struct device_attribute *attr,
5167 +                                            const char *buf, size_t count)
5168 +{
5169 +       struct retu_headset *hs = dev_get_drvdata(dev);
5170 +       int enable;
5171 +
5172 +       if (sscanf(buf, "%u", &enable) != 1)
5173 +               return -EINVAL;
5174 +       if (enable)
5175 +               retu_headset_det_enable(hs);
5176 +       else
5177 +               retu_headset_det_disable(hs);
5178 +       return count;
5179 +}
5180 +
5181 +static DEVICE_ATTR(enable_det, S_IRUGO | S_IWUSR | S_IWGRP,
5182 +                  retu_headset_enable_det_show,
5183 +                  retu_headset_enable_det_store);
5184 +
5185 +static void retu_headset_hook_interrupt(unsigned long arg)
5186 +{
5187 +       struct retu_headset *hs = (struct retu_headset *) arg;
5188 +       unsigned long flags;
5189 +
5190 +       retu_ack_irq(RETU_INT_HOOK);
5191 +       spin_lock_irqsave(&hs->lock, flags);
5192 +       if (!hs->pressed) {
5193 +               /* Headset button was just pressed down. */
5194 +               hs->pressed = 1;
5195 +               input_report_key(hs->idev, RETU_HEADSET_KEY, 1);
5196 +       }
5197 +       spin_unlock_irqrestore(&hs->lock, flags);
5198 +       retu_set_clear_reg_bits(RETU_REG_CC1, 0, (1 << 10) | (1 << 8));
5199 +       mod_timer(&hs->enable_timer, jiffies + msecs_to_jiffies(50));
5200 +}
5201 +
5202 +static void retu_headset_enable_timer(unsigned long arg)
5203 +{
5204 +       struct retu_headset *hs = (struct retu_headset *) arg;
5205 +
5206 +       retu_set_clear_reg_bits(RETU_REG_CC1, (1 << 10) | (1 << 8), 0);
5207 +       mod_timer(&hs->detect_timer, jiffies + msecs_to_jiffies(350));
5208 +}
5209 +
5210 +static void retu_headset_detect_timer(unsigned long arg)
5211 +{
5212 +       struct retu_headset *hs = (struct retu_headset *) arg;
5213 +       unsigned long flags;
5214 +
5215 +       spin_lock_irqsave(&hs->lock, flags);
5216 +       if (hs->pressed) {
5217 +               hs->pressed = 0;
5218 +               input_report_key(hs->idev, RETU_HEADSET_KEY, 0);
5219 +       }
5220 +       spin_unlock_irqrestore(&hs->lock, flags);
5221 +}
5222 +
5223 +static int __init retu_headset_probe(struct platform_device *pdev)
5224 +{
5225 +       struct retu_headset *hs;
5226 +       int r;
5227 +
5228 +       hs = kzalloc(sizeof(*hs), GFP_KERNEL);
5229 +       if (hs == NULL)
5230 +               return -ENOMEM;
5231 +
5232 +       hs->pdev = pdev;
5233 +
5234 +       hs->idev = input_allocate_device();
5235 +       if (hs->idev == NULL) {
5236 +               r = -ENOMEM;
5237 +               goto err1;
5238 +       }
5239 +       hs->idev->name = "retu-headset";
5240 +       hs->idev->dev.parent = &pdev->dev;
5241 +       set_bit(EV_KEY, hs->idev->evbit);
5242 +       set_bit(RETU_HEADSET_KEY, hs->idev->keybit);
5243 +       r = input_register_device(hs->idev);
5244 +       if (r < 0)
5245 +               goto err2;
5246 +
5247 +       r = device_create_file(&pdev->dev, &dev_attr_hookdet);
5248 +       if (r < 0)
5249 +               goto err3;
5250 +       r = device_create_file(&pdev->dev, &dev_attr_enable);
5251 +       if (r < 0)
5252 +               goto err4;
5253 +       r = device_create_file(&pdev->dev, &dev_attr_enable_det);
5254 +       if (r < 0)
5255 +               goto err5;
5256 +       platform_set_drvdata(pdev, hs);
5257 +
5258 +       spin_lock_init(&hs->lock);
5259 +       mutex_init(&hs->mutex);
5260 +       setup_timer(&hs->enable_timer, retu_headset_enable_timer,
5261 +                   (unsigned long) hs);
5262 +       setup_timer(&hs->detect_timer, retu_headset_detect_timer,
5263 +                   (unsigned long) hs);
5264 +
5265 +       r = retu_request_irq(RETU_INT_HOOK, retu_headset_hook_interrupt,
5266 +                            (unsigned long) hs, "hookdet");
5267 +       if (r != 0) {
5268 +               dev_err(&pdev->dev, "hookdet IRQ not available\n");
5269 +               goto err6;
5270 +       }
5271 +       retu_disable_irq(RETU_INT_HOOK);
5272 +       return 0;
5273 +err6:
5274 +       device_remove_file(&pdev->dev, &dev_attr_enable_det);
5275 +err5:
5276 +       device_remove_file(&pdev->dev, &dev_attr_enable);
5277 +err4:
5278 +       device_remove_file(&pdev->dev, &dev_attr_hookdet);
5279 +err3:
5280 +       input_unregister_device(hs->idev);
5281 +err2:
5282 +       input_free_device(hs->idev);
5283 +err1:
5284 +       kfree(hs);
5285 +       return r;
5286 +}
5287 +
5288 +static int retu_headset_remove(struct platform_device *pdev)
5289 +{
5290 +       struct retu_headset *hs = platform_get_drvdata(pdev);
5291 +
5292 +       device_remove_file(&pdev->dev, &dev_attr_hookdet);
5293 +       device_remove_file(&pdev->dev, &dev_attr_enable);
5294 +       device_remove_file(&pdev->dev, &dev_attr_enable_det);
5295 +       retu_headset_disable(hs);
5296 +       retu_headset_det_disable(hs);
5297 +       retu_free_irq(RETU_INT_HOOK);
5298 +       input_unregister_device(hs->idev);
5299 +       input_free_device(hs->idev);
5300 +       return 0;
5301 +}
5302 +
5303 +static int retu_headset_suspend(struct platform_device *pdev,
5304 +                               pm_message_t mesg)
5305 +{
5306 +       struct retu_headset *hs = platform_get_drvdata(pdev);
5307 +
5308 +       mutex_lock(&hs->mutex);
5309 +       if (hs->bias_enabled)
5310 +               retu_headset_set_bias(0);
5311 +       mutex_unlock(&hs->mutex);
5312 +
5313 +       return 0;
5314 +}
5315 +
5316 +static int retu_headset_resume(struct platform_device *pdev)
5317 +{
5318 +       struct retu_headset *hs = platform_get_drvdata(pdev);
5319 +
5320 +       mutex_lock(&hs->mutex);
5321 +       if (hs->bias_enabled)
5322 +               retu_headset_set_bias(1);
5323 +       mutex_unlock(&hs->mutex);
5324 +
5325 +       return 0;
5326 +}
5327 +
5328 +static struct platform_driver retu_headset_driver = {
5329 +       .probe          = retu_headset_probe,
5330 +       .remove         = retu_headset_remove,
5331 +       .suspend        = retu_headset_suspend,
5332 +       .resume         = retu_headset_resume,
5333 +       .driver         = {
5334 +               .name   = "retu-headset",
5335 +       },
5336 +};
5337 +
5338 +static int __init retu_headset_init(void)
5339 +{
5340 +       int r;
5341 +
5342 +       printk(KERN_INFO "Retu/Vilma headset driver initializing\n");
5343 +
5344 +       r = platform_driver_register(&retu_headset_driver);
5345 +       if (r < 0)
5346 +               return r;
5347 +
5348 +       return 0;
5349 +}
5350 +
5351 +static void __exit retu_headset_exit(void)
5352 +{
5353 +       platform_driver_unregister(&retu_headset_driver);
5354 +}
5355 +
5356 +module_init(retu_headset_init);
5357 +module_exit(retu_headset_exit);
5358 +
5359 +MODULE_DESCRIPTION("Retu/Vilma headset detection");
5360 +MODULE_LICENSE("GPL");
5361 +MODULE_AUTHOR("Juha Yrjölä");
5362 diff --git a/drivers/cbus/retu-pwrbutton.c b/drivers/cbus/retu-pwrbutton.c
5363 new file mode 100644
5364 index 0000000..38d7aa4
5365 --- /dev/null
5366 +++ b/drivers/cbus/retu-pwrbutton.c
5367 @@ -0,0 +1,118 @@
5368 +/**
5369 + * drivers/cbus/retu-pwrbutton.c
5370 + *
5371 + * Driver for sending retu power button event to input-layer
5372 + *
5373 + * Copyright (C) 2004 Nokia Corporation
5374 + *
5375 + * Written by Ari Saastamoinen <ari.saastamoinen@elektrobit.com>
5376 + *
5377 + * Contact Juha Yrjölä <juha.yrjola@nokia.com>
5378 + *
5379 + * This file is subject to the terms and conditions of the GNU General
5380 + * Public License. See the file "COPYING" in the main directory of this
5381 + * archive for more details.
5382 + *
5383 + * This program is distributed in the hope that it will be useful,
5384 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5385 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5386 + * GNU General Public License for more details.
5387 + *
5388 + * You should have received a copy of the GNU General Public License
5389 + * along with this program; if not, write to the Free Software
5390 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5391 + */
5392 +
5393 +#include <linux/module.h>
5394 +#include <linux/init.h>
5395 +#include <linux/kernel.h>
5396 +#include <linux/errno.h>
5397 +#include <linux/input.h>
5398 +#include <linux/timer.h>
5399 +#include <linux/jiffies.h>
5400 +#include <linux/bitops.h>
5401 +
5402 +#include "retu.h"
5403 +
5404 +#define RETU_STATUS_PWRONX     (1 << 5)
5405 +
5406 +#define PWRBTN_DELAY           20
5407 +#define PWRBTN_UP              0
5408 +#define PWRBTN_PRESSED         1
5409 +
5410 +static int pwrbtn_state;
5411 +static struct input_dev *pwrbtn_dev;
5412 +static struct timer_list pwrbtn_timer;
5413 +
5414 +static void retubutton_timer_func(unsigned long arg)
5415 +{
5416 +       int state;
5417 +
5418 +       if (retu_read_reg(RETU_REG_STATUS) & RETU_STATUS_PWRONX)
5419 +               state = PWRBTN_UP;
5420 +       else
5421 +               state = PWRBTN_PRESSED;
5422 +
5423 +       if (pwrbtn_state != state) {
5424 +               input_report_key(pwrbtn_dev, KEY_POWER, state);
5425 +               pwrbtn_state = state;
5426 +       }
5427 +}
5428 +
5429 +/**
5430 + * Interrupt function is called whenever power button key is pressed
5431 + * or released.
5432 + */
5433 +static void retubutton_irq(unsigned long arg)
5434 +{
5435 +       retu_ack_irq(RETU_INT_PWR);
5436 +       mod_timer(&pwrbtn_timer, jiffies + msecs_to_jiffies(PWRBTN_DELAY));
5437 +}
5438 +
5439 +/**
5440 + * Init function.
5441 + * Allocates interrupt for power button and registers itself to input layer.
5442 + */
5443 +static int __init retubutton_init(void)
5444 +{
5445 +       int irq;
5446 +
5447 +       printk(KERN_INFO "Retu power button driver initialized\n");
5448 +       irq = RETU_INT_PWR;
5449 +
5450 +       init_timer(&pwrbtn_timer);
5451 +       pwrbtn_timer.function = retubutton_timer_func;
5452 +
5453 +       if (retu_request_irq(irq, &retubutton_irq, 0, "PwrOnX") < 0) {
5454 +               printk(KERN_ERR "%s@%s: Cannot allocate irq\n",
5455 +                      __FUNCTION__, __FILE__);
5456 +               return -EBUSY;
5457 +       }
5458 +
5459 +       pwrbtn_dev = input_allocate_device();
5460 +       if (!pwrbtn_dev)
5461 +               return -ENOMEM;
5462 +
5463 +       pwrbtn_dev->evbit[0] = BIT_MASK(EV_KEY);
5464 +       pwrbtn_dev->keybit[BIT_WORD(KEY_POWER)] = BIT_MASK(KEY_POWER);
5465 +       pwrbtn_dev->name = "retu-pwrbutton";
5466 +
5467 +       return input_register_device(pwrbtn_dev);
5468 +}
5469 +
5470 +/**
5471 + * Cleanup function which is called when driver is unloaded
5472 + */
5473 +static void __exit retubutton_exit(void)
5474 +{
5475 +       retu_free_irq(RETU_INT_PWR);
5476 +       del_timer_sync(&pwrbtn_timer);
5477 +       input_unregister_device(pwrbtn_dev);
5478 +}
5479 +
5480 +module_init(retubutton_init);
5481 +module_exit(retubutton_exit);
5482 +
5483 +MODULE_DESCRIPTION("Retu Power Button");
5484 +MODULE_LICENSE("GPL");
5485 +MODULE_AUTHOR("Ari Saastamoinen");
5486 diff --git a/drivers/cbus/retu-rtc.c b/drivers/cbus/retu-rtc.c
5487 new file mode 100644
5488 index 0000000..1ebc33b
5489 --- /dev/null
5490 +++ b/drivers/cbus/retu-rtc.c
5491 @@ -0,0 +1,477 @@
5492 +/**
5493 + * drivers/cbus/retu-rtc.c
5494 + *
5495 + * Support for Retu RTC
5496 + *
5497 + * Copyright (C) 2004, 2005 Nokia Corporation
5498 + *
5499 + * Written by Paul Mundt <paul.mundt@nokia.com> and
5500 + *            Igor Stoppa <igor.stoppa@nokia.com>
5501 + *
5502 + * The Retu RTC is essentially a partial read-only RTC that gives us Retu's
5503 + * idea of what time actually is. It's left as a userspace excercise to map
5504 + * this back to time in the real world and ensure that calibration settings
5505 + * are sane to compensate for any horrible drift (on account of not being able
5506 + * to set the clock to anything).
5507 + *
5508 + * Days are semi-writeable. Namely, Retu will only track 255 days for us
5509 + * consecutively, after which the counter is explicitly stuck at 255 until
5510 + * someone comes along and clears it with a write. In the event that no one
5511 + * comes along and clears it, we no longer have any idea what day it is.
5512 + *
5513 + * This file is subject to the terms and conditions of the GNU General
5514 + * Public License. See the file "COPYING" in the main directory of this
5515 + * archive for more details.
5516 + *
5517 + * This program is distributed in the hope that it will be useful,
5518 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5519 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5520 + * GNU General Public License for more details.
5521 + *
5522 + * You should have received a copy of the GNU General Public License
5523 + * along with this program; if not, write to the Free Software
5524 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5525 + */
5526 +
5527 +#include <linux/device.h>
5528 +#include <linux/init.h>
5529 +#include <linux/kernel.h>
5530 +#include <linux/module.h>
5531 +#include <linux/completion.h>
5532 +#include <linux/platform_device.h>
5533 +#include <linux/mutex.h>
5534 +#include <linux/workqueue.h>
5535 +
5536 +#include "cbus.h"
5537 +#include "retu.h"
5538 +
5539 +static struct mutex retu_rtc_mutex;
5540 +static u16 retu_rtc_alarm_expired;
5541 +static u16 retu_rtc_reset_occurred;
5542 +
5543 +static DECLARE_COMPLETION(retu_rtc_exited);
5544 +static DECLARE_COMPLETION(retu_rtc_sync);
5545 +
5546 +static void retu_rtc_barrier(void);
5547 +
5548 +static void retu_rtc_device_release(struct device *dev)
5549 +{
5550 +       complete(&retu_rtc_exited);
5551 +}
5552 +
5553 +static ssize_t retu_rtc_time_show(struct device *dev, struct device_attribute *attr,
5554 +                                 char *buf)
5555 +{
5556 +       u16 dsr, hmr, dsr2;
5557 +
5558 +       mutex_lock(&retu_rtc_mutex);
5559 +
5560 +       do {
5561 +               u16 dummy;
5562 +
5563 +               /*
5564 +                * Not being in_interrupt() for a retu rtc IRQ, we need to
5565 +                * read twice for consistency..
5566 +                */
5567 +               dummy   = retu_read_reg(RETU_REG_RTCDSR);
5568 +               dsr     = retu_read_reg(RETU_REG_RTCDSR);
5569 +
5570 +               dummy   = retu_read_reg(RETU_REG_RTCHMR);
5571 +               hmr     = retu_read_reg(RETU_REG_RTCHMR);
5572 +
5573 +               dummy   = retu_read_reg(RETU_REG_RTCDSR);
5574 +               dsr2    = retu_read_reg(RETU_REG_RTCDSR);
5575 +       } while ((dsr != dsr2));
5576 +
5577 +       mutex_unlock(&retu_rtc_mutex);
5578 +
5579 +       /*
5580 +        * Format a 32-bit date-string for userspace
5581 +        *
5582 +        * days | hours | minutes | seconds
5583 +        *
5584 +        * 8 bits for each.
5585 +        *
5586 +        * This mostly sucks because days and seconds are tracked in RTCDSR
5587 +        * while hours and minutes are tracked in RTCHMR. And yes, there
5588 +        * really are no words that can describe an 8 bit day register (or
5589 +        * rather, none that will be reprinted here).
5590 +        */
5591 +       return sprintf(buf, "0x%08x\n", (((dsr >> 8) & 0xff) << 24) |
5592 +                                       (((hmr >> 8) & 0x1f) << 16) |
5593 +                                        ((hmr & 0x3f) << 8) | (dsr & 0x3f));
5594 +}
5595 +
5596 +static ssize_t retu_rtc_time_store(struct device *dev, struct device_attribute *attr,
5597 +                                  const char *buf, size_t count)
5598 +{
5599 +       mutex_lock(&retu_rtc_mutex);
5600 +       /*
5601 +        * Writing anything to the day counter forces it to 0
5602 +        * The seconds counter would be cleared by resetting the minutes counter,
5603 +        * however this won't happen, since we are using the hh:mm counters as
5604 +        * a set of free running counters and the day counter as a multiple
5605 +        * overflow holder.
5606 +        */
5607 +
5608 +       /* Reset day counter, but keep Temperature Shutdown state */
5609 +       retu_write_reg(RETU_REG_RTCDSR,
5610 +                      retu_read_reg(RETU_REG_RTCDSR) & (1 << 6));
5611 +
5612 +       mutex_unlock(&retu_rtc_mutex);
5613 +
5614 +       return count;
5615 +}
5616 +
5617 +static DEVICE_ATTR(time, S_IRUGO | S_IWUSR, retu_rtc_time_show,
5618 +                  retu_rtc_time_store);
5619 +
5620 +
5621 +static ssize_t retu_rtc_reset_show(struct device *dev, struct device_attribute *attr, char *buf)
5622 +{
5623 +       /*
5624 +        * Returns the status of the rtc
5625 +        *
5626 +        * 0: no reset has occurred or the status has been cleared
5627 +        * 1: a reset has occurred
5628 +        *
5629 +        * RTC needs to be reset only when both main battery
5630 +        * _AND_ backup battery are discharged
5631 +        */
5632 +       return sprintf(buf, "%u\n", retu_rtc_reset_occurred);
5633 +}
5634 +
5635 +static void retu_rtc_do_reset(void)
5636 +{
5637 +       u16 ccr1;
5638 +
5639 +       ccr1 = retu_read_reg(RETU_REG_CC1);
5640 +       /* RTC in reset */
5641 +       retu_write_reg(RETU_REG_CC1, ccr1 | 0x0001);
5642 +       /* RTC in normal operating mode */
5643 +       retu_write_reg(RETU_REG_CC1, ccr1 & ~0x0001);
5644 +
5645 +       retu_rtc_barrier();
5646 +       /* Disable alarm and RTC WD */
5647 +       retu_write_reg(RETU_REG_RTCHMAR, 0x7f3f);
5648 +       /* Set Calibration register to default value */
5649 +       retu_write_reg(RETU_REG_RTCCALR, 0x00c0);
5650 +
5651 +       retu_rtc_alarm_expired = 0;
5652 +       retu_rtc_reset_occurred = 1;
5653 +}
5654 +
5655 +static ssize_t retu_rtc_reset_store(struct device *dev, struct device_attribute *attr,
5656 +                                   const char *buf, size_t count)
5657 +{
5658 +       unsigned choice;
5659 +
5660 +       if(sscanf(buf, "%u", &choice) != 1)
5661 +               return count;
5662 +       mutex_lock(&retu_rtc_mutex);
5663 +       if (choice == 0)
5664 +               retu_rtc_reset_occurred = 0;
5665 +       else if (choice == 1)
5666 +               retu_rtc_do_reset();
5667 +       mutex_unlock(&retu_rtc_mutex);
5668 +       return count;
5669 +}
5670 +
5671 +static DEVICE_ATTR(reset, S_IRUGO | S_IWUSR, retu_rtc_reset_show,
5672 +                  retu_rtc_reset_store);
5673 +
5674 +static ssize_t retu_rtc_alarm_show(struct device *dev, struct device_attribute *attr,
5675 +                                  char *buf)
5676 +{
5677 +       u16 chmar;
5678 +       ssize_t retval;
5679 +
5680 +       mutex_lock(&retu_rtc_mutex);
5681 +       /*
5682 +        * Format a 16-bit date-string for userspace
5683 +        *
5684 +        * hours | minutes
5685 +        * 8 bits for each.
5686 +        */
5687 +       chmar = retu_read_reg(RETU_REG_RTCHMAR);
5688 +       /* No shifting needed, only masking unrelated bits */
5689 +       retval = sprintf(buf, "0x%04x\n", chmar & 0x1f3f);
5690 +       mutex_unlock(&retu_rtc_mutex);
5691 +
5692 +       return retval;
5693 +}
5694 +
5695 +static ssize_t retu_rtc_alarm_store(struct device *dev, struct device_attribute *attr,
5696 +                                   const char *buf, size_t count)
5697 +{
5698 +       u16 chmar;
5699 +       unsigned alrm;
5700 +       unsigned hours;
5701 +       unsigned minutes;
5702 +
5703 +       mutex_lock(&retu_rtc_mutex);
5704 +
5705 +       if(sscanf(buf, "%x", &alrm) != 1)
5706 +               return count;
5707 +       hours = (alrm >> 8) & 0x001f;
5708 +       minutes = (alrm >> 0) & 0x003f;
5709 +       if ((hours < 24 && minutes < 60) || (hours == 24 && minutes == 60)) {
5710 +               /*
5711 +                * OK, the time format for the alarm is valid (including the
5712 +                * disabling values)
5713 +                */
5714 +               /* Keeps the RTC watchdog status */
5715 +               chmar = retu_read_reg(RETU_REG_RTCHMAR) & 0x6000;
5716 +               chmar |= alrm & 0x1f3f; /* Stores the requested alarm */
5717 +               retu_rtc_barrier();
5718 +               retu_write_reg(RETU_REG_RTCHMAR, chmar);
5719 +               /* If the alarm is being disabled */
5720 +               if (hours == 24 && minutes == 60) {
5721 +                       /* disable the interrupt */
5722 +                       retu_disable_irq(RETU_INT_RTCA);
5723 +                       retu_rtc_alarm_expired = 0;
5724 +               } else
5725 +                       /* enable the interrupt */
5726 +                       retu_enable_irq(RETU_INT_RTCA);
5727 +       }
5728 +       mutex_unlock(&retu_rtc_mutex);
5729 +
5730 +       return count;
5731 +}
5732 +
5733 +static DEVICE_ATTR(alarm, S_IRUGO | S_IWUSR, retu_rtc_alarm_show,
5734 +                  retu_rtc_alarm_store);
5735 +
5736 +static ssize_t retu_rtc_alarm_expired_show(struct device *dev, struct device_attribute *attr,
5737 +                                          char *buf)
5738 +{
5739 +       ssize_t retval;
5740 +
5741 +       retval = sprintf(buf, "%u\n", retu_rtc_alarm_expired);
5742 +
5743 +       return retval;
5744 +}
5745 +
5746 +static ssize_t retu_rtc_alarm_expired_store(struct device *dev, struct device_attribute *attr,
5747 +                                           const char *buf, size_t count)
5748 +{
5749 +       retu_rtc_alarm_expired = 0;
5750 +
5751 +       return count;
5752 +}
5753 +
5754 +static DEVICE_ATTR(alarm_expired, S_IRUGO | S_IWUSR, retu_rtc_alarm_expired_show,
5755 +                  retu_rtc_alarm_expired_store);
5756 +
5757 +
5758 +static ssize_t retu_rtc_cal_show(struct device *dev, struct device_attribute *attr,
5759 +                                char *buf)
5760 +{
5761 +       u16 rtccalr1;
5762 +
5763 +       mutex_lock(&retu_rtc_mutex);
5764 +       rtccalr1 = retu_read_reg(RETU_REG_RTCCALR);
5765 +       mutex_unlock(&retu_rtc_mutex);
5766 +
5767 +       /*
5768 +        * Shows the status of the Calibration Register.
5769 +        *
5770 +        * Default, after power loss: 0x0000
5771 +        * Default, for R&D: 0x00C0
5772 +        * Default, for factory: 0x00??
5773 +        *
5774 +        */
5775 +       return sprintf(buf, "0x%04x\n", rtccalr1 & 0x00ff);
5776 +}
5777 +
5778 +static ssize_t retu_rtc_cal_store(struct device *dev, struct device_attribute *attr,
5779 +                                 const char *buf, size_t count)
5780 +{
5781 +       unsigned calibration_value;
5782 +
5783 +       if (sscanf(buf, "%x", &calibration_value) != 1)
5784 +               return count;
5785 +
5786 +       mutex_lock(&retu_rtc_mutex);
5787 +       retu_rtc_barrier();
5788 +       retu_write_reg(RETU_REG_RTCCALR, calibration_value & 0x00ff);
5789 +       mutex_unlock(&retu_rtc_mutex);
5790 +
5791 +       return count;
5792 +}
5793 +
5794 +static DEVICE_ATTR(cal, S_IRUGO | S_IWUSR, retu_rtc_cal_show,
5795 +                  retu_rtc_cal_store);
5796 +
5797 +static struct platform_device retu_rtc_device;
5798 +
5799 +static void retu_rtca_disable(void)
5800 +{
5801 +       retu_disable_irq(RETU_INT_RTCA);
5802 +       retu_rtc_alarm_expired = 1;
5803 +       retu_rtc_barrier();
5804 +       retu_write_reg(RETU_REG_RTCHMAR, (24 << 8) | 60);
5805 +}
5806 +
5807 +static void retu_rtca_expired(struct work_struct *unused)
5808 +{
5809 +       retu_rtca_disable();
5810 +       sysfs_notify(&retu_rtc_device.dev.kobj, NULL, "alarm_expired");
5811 +}
5812 +
5813 +DECLARE_WORK(retu_rtca_work, retu_rtca_expired);
5814 +
5815 +/*
5816 + * RTCHMR RTCHMAR RTCCAL must be accessed within 0.9 s since the seconds
5817 + * interrupt has been signaled in the IDR register
5818 + */
5819 +static void retu_rtcs_interrupt(unsigned long unused)
5820 +{
5821 +       retu_ack_irq(RETU_INT_RTCS);
5822 +       complete_all(&retu_rtc_sync);
5823 +}
5824 +
5825 +static void retu_rtca_interrupt(unsigned long unused)
5826 +{
5827 +       retu_ack_irq(RETU_INT_RTCA);
5828 +       schedule_work(&retu_rtca_work);
5829 +}
5830 +
5831 +static int retu_rtc_init_irq(void)
5832 +{
5833 +       int ret;
5834 +
5835 +       ret = retu_request_irq(RETU_INT_RTCS, retu_rtcs_interrupt, 0, "RTCS");
5836 +       if (ret != 0)
5837 +               return ret;
5838 +       /*
5839 +        * We will take care of enabling and disabling the interrupt
5840 +        * elsewhere, so leave it off by default..
5841 +        */
5842 +       retu_disable_irq(RETU_INT_RTCS);
5843 +
5844 +       ret = retu_request_irq(RETU_INT_RTCA, retu_rtca_interrupt, 0, "RTCA");
5845 +       if (ret != 0) {
5846 +               retu_free_irq(RETU_INT_RTCS);
5847 +               return ret;
5848 +       }
5849 +       retu_disable_irq(RETU_INT_RTCA);
5850 +
5851 +       return 0;
5852 +}
5853 +
5854 +
5855 +static int __devinit retu_rtc_probe(struct device *dev)
5856 +{
5857 +       int r;
5858 +
5859 +       retu_rtc_alarm_expired = retu_read_reg(RETU_REG_IDR) &
5860 +                                              (0x1 << RETU_INT_RTCA);
5861 +
5862 +       if ((r = retu_rtc_init_irq()) != 0)
5863 +               return r;
5864 +
5865 +       mutex_init(&retu_rtc_mutex);
5866 +
5867 +       /* If the calibration register is zero, we've probably lost
5868 +        * power */
5869 +       if (retu_read_reg(RETU_REG_RTCCALR) & 0x00ff)
5870 +               retu_rtc_reset_occurred = 0;
5871 +       else
5872 +               retu_rtc_do_reset();
5873 +
5874 +       if ((r = device_create_file(dev, &dev_attr_time)) != 0)
5875 +               return r;
5876 +       else if ((r = device_create_file(dev, &dev_attr_reset)) != 0)
5877 +               goto err_unregister_time;
5878 +       else if ((r = device_create_file(dev, &dev_attr_alarm)) != 0)
5879 +               goto err_unregister_reset;
5880 +       else if ((r = device_create_file(dev, &dev_attr_alarm_expired)) != 0)
5881 +               goto err_unregister_alarm;
5882 +       else if ((r = device_create_file(dev, &dev_attr_cal)) != 0)
5883 +               goto err_unregister_alarm_expired;
5884 +       else
5885 +               return r;
5886 +
5887 +err_unregister_alarm_expired:
5888 +       device_remove_file(dev, &dev_attr_alarm_expired);
5889 +err_unregister_alarm:
5890 +       device_remove_file(dev, &dev_attr_alarm);
5891 +err_unregister_reset:
5892 +       device_remove_file(dev, &dev_attr_reset);
5893 +err_unregister_time:
5894 +       device_remove_file(dev, &dev_attr_time);
5895 +       return r;
5896 +}
5897 +
5898 +static int __devexit retu_rtc_remove(struct device *dev)
5899 +{
5900 +       retu_disable_irq(RETU_INT_RTCS);
5901 +       retu_free_irq(RETU_INT_RTCS);
5902 +       retu_free_irq(RETU_INT_RTCA);
5903 +       device_remove_file(dev, &dev_attr_cal);
5904 +       device_remove_file(dev, &dev_attr_alarm_expired);
5905 +       device_remove_file(dev, &dev_attr_alarm);
5906 +       device_remove_file(dev, &dev_attr_reset);
5907 +       device_remove_file(dev, &dev_attr_time);
5908 +       return 0;
5909 +}
5910 +
5911 +static struct device_driver retu_rtc_driver = {
5912 +       .name           = "retu-rtc",
5913 +       .bus            = &platform_bus_type,
5914 +       .probe          = retu_rtc_probe,
5915 +       .remove         = __devexit_p(retu_rtc_remove),
5916 +};
5917 +
5918 +static struct platform_device retu_rtc_device = {
5919 +       .name           = "retu-rtc",
5920 +       .id             = -1,
5921 +       .dev            = {
5922 +               .release        = retu_rtc_device_release,
5923 +       },
5924 +};
5925 +
5926 +/* This function provides syncronization with the RTCS interrupt handler */
5927 +static void retu_rtc_barrier(void)
5928 +{
5929 +       INIT_COMPLETION(retu_rtc_sync);
5930 +       retu_ack_irq(RETU_INT_RTCS);
5931 +       retu_enable_irq(RETU_INT_RTCS);
5932 +       wait_for_completion(&retu_rtc_sync);
5933 +       retu_disable_irq(RETU_INT_RTCS);
5934 +}
5935 +
5936 +static int __init retu_rtc_init(void)
5937 +{
5938 +       int ret;
5939 +
5940 +       init_completion(&retu_rtc_exited);
5941 +
5942 +       if ((ret = driver_register(&retu_rtc_driver)) != 0)
5943 +               return ret;
5944 +
5945 +       if ((ret = platform_device_register(&retu_rtc_device)) != 0)
5946 +               goto err_unregister_driver;
5947 +
5948 +       return 0;
5949 +
5950 +err_unregister_driver:
5951 +       driver_unregister(&retu_rtc_driver);
5952 +       return ret;
5953 +}
5954 +
5955 +static void __exit retu_rtc_exit(void)
5956 +{
5957 +       platform_device_unregister(&retu_rtc_device);
5958 +       driver_unregister(&retu_rtc_driver);
5959 +
5960 +       wait_for_completion(&retu_rtc_exited);
5961 +}
5962 +
5963 +module_init(retu_rtc_init);
5964 +module_exit(retu_rtc_exit);
5965 +
5966 +MODULE_DESCRIPTION("Retu RTC");
5967 +MODULE_LICENSE("GPL");
5968 +MODULE_AUTHOR("Paul Mundt and Igor Stoppa");
5969 diff --git a/drivers/cbus/retu-user.c b/drivers/cbus/retu-user.c
5970 new file mode 100644
5971 index 0000000..74a7d61
5972 --- /dev/null
5973 +++ b/drivers/cbus/retu-user.c
5974 @@ -0,0 +1,423 @@
5975 +/**
5976 + * drivers/cbus/retu-user.c
5977 + *
5978 + * Retu user space interface functions
5979 + *
5980 + * Copyright (C) 2004, 2005 Nokia Corporation
5981 + *
5982 + * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
5983 + *
5984 + * This file is subject to the terms and conditions of the GNU General
5985 + * Public License. See the file "COPYING" in the main directory of this
5986 + * archive for more details.
5987 + *
5988 + * This program is distributed in the hope that it will be useful,
5989 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5990 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5991 + * GNU General Public License for more details.
5992 + *
5993 + * You should have received a copy of the GNU General Public License
5994 + * along with this program; if not, write to the Free Software
5995 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5996 + */
5997 +
5998 +#include <linux/types.h>
5999 +#include <linux/kernel.h>
6000 +#include <linux/interrupt.h>
6001 +#include <linux/module.h>
6002 +#include <linux/init.h>
6003 +#include <linux/fs.h>
6004 +#include <linux/miscdevice.h>
6005 +#include <linux/poll.h>
6006 +#include <linux/list.h>
6007 +#include <linux/spinlock.h>
6008 +#include <linux/mutex.h>
6009 +
6010 +#include <asm/uaccess.h>
6011 +
6012 +#include "retu.h"
6013 +
6014 +#include "user_retu_tahvo.h"
6015 +
6016 +/* Maximum size of IRQ node buffer/pool */
6017 +#define RETU_MAX_IRQ_BUF_LEN   16
6018 +
6019 +#define PFX                    "retu-user: "
6020 +
6021 +/* Bitmap for marking the interrupt sources as having the handlers */
6022 +static u32 retu_irq_bits;
6023 +
6024 +/* For allowing only one user process to subscribe to the retu interrupts */
6025 +static struct file *retu_irq_subscr = NULL;
6026 +
6027 +/* For poll and IRQ passing */
6028 +struct retu_irq {
6029 +       u32 id;
6030 +       struct list_head node;
6031 +};
6032 +
6033 +static spinlock_t retu_irqs_lock;
6034 +static struct retu_irq *retu_irq_block;
6035 +static LIST_HEAD(retu_irqs);
6036 +static LIST_HEAD(retu_irqs_reserve);
6037 +
6038 +/* Wait queue - used when user wants to read the device */
6039 +DECLARE_WAIT_QUEUE_HEAD(retu_user_waitqueue);
6040 +
6041 +/* Semaphore to protect irq subscription sequence */
6042 +static struct mutex retu_mutex;
6043 +
6044 +/* This array specifies RETU register types (read/write/toggle) */
6045 +static const u8 retu_access_bits[] = {
6046 +       1,
6047 +       4,
6048 +       3,
6049 +       3,
6050 +       1,
6051 +       3,
6052 +       3,
6053 +       0,
6054 +       3,
6055 +       3,
6056 +       3,
6057 +       3,
6058 +       3,
6059 +       3,
6060 +       3,
6061 +       4,
6062 +       4,
6063 +       3,
6064 +       0,
6065 +       0,
6066 +       0,
6067 +       0,
6068 +       1,
6069 +       3,
6070 +       3,
6071 +       3,
6072 +       3,
6073 +       3,
6074 +       3,
6075 +       3,
6076 +       3,
6077 +       3
6078 +};
6079 +
6080 +/*
6081 + * The handler for all RETU interrupts.
6082 + *
6083 + * arg is the interrupt source in RETU.
6084 + */
6085 +static void retu_user_irq_handler(unsigned long arg)
6086 +{
6087 +       struct retu_irq *irq;
6088 +
6089 +       retu_ack_irq(arg);
6090 +
6091 +       spin_lock(&retu_irqs_lock);
6092 +       if (list_empty(&retu_irqs_reserve)) {
6093 +               spin_unlock(&retu_irqs_lock);
6094 +               return;
6095 +       }
6096 +       irq = list_entry((&retu_irqs_reserve)->next, struct retu_irq, node);
6097 +       irq->id = arg;
6098 +       list_move_tail(&irq->node, &retu_irqs);
6099 +       spin_unlock(&retu_irqs_lock);
6100 +
6101 +       /* wake up waiting thread */
6102 +       wake_up(&retu_user_waitqueue);
6103 +}
6104 +
6105 +/*
6106 + * This routine sets up the interrupt handler and marks an interrupt source
6107 + * in RETU as a candidate for signal delivery to the user process.
6108 + */
6109 +static int retu_user_subscribe_to_irq(int id, struct file *filp)
6110 +{
6111 +       int ret;
6112 +
6113 +       mutex_lock(&retu_mutex);
6114 +       if ((retu_irq_subscr != NULL) && (retu_irq_subscr != filp)) {
6115 +               mutex_unlock(&retu_mutex);
6116 +               return -EBUSY;
6117 +       }
6118 +       /* Store the file pointer of the first user process registering IRQs */
6119 +       retu_irq_subscr = filp;
6120 +       mutex_unlock(&retu_mutex);
6121 +
6122 +       if (retu_irq_bits & (1 << id))
6123 +               return 0;
6124 +
6125 +       ret = retu_request_irq(id, retu_user_irq_handler, id, "");
6126 +       if (ret < 0)
6127 +               return ret;
6128 +
6129 +       /* Mark that this interrupt has a handler */
6130 +       retu_irq_bits |= 1 << id;
6131 +
6132 +       return 0;
6133 +}
6134 +
6135 +/*
6136 + * Unregisters all RETU interrupt handlers.
6137 + */
6138 +static void retu_unreg_irq_handlers(void)
6139 +{
6140 +       int id;
6141 +
6142 +       if (!retu_irq_bits)
6143 +               return;
6144 +
6145 +       for (id = 0; id < MAX_RETU_IRQ_HANDLERS; id++)
6146 +               if (retu_irq_bits & (1 << id))
6147 +                       retu_free_irq(id);
6148 +
6149 +       retu_irq_bits = 0;
6150 +}
6151 +
6152 +/*
6153 + * Write to RETU register.
6154 + * Returns 0 upon success, a negative error value otherwise.
6155 + */
6156 +static int retu_user_write_with_mask(u32 field, u16 value)
6157 +{
6158 +       u32 mask;
6159 +       u32 reg;
6160 +       u_short tmp;
6161 +       unsigned long flags;
6162 +
6163 +       mask = MASK(field);
6164 +       reg = REG(field);
6165 +
6166 +       /* Detect bad mask and reg */
6167 +       if (mask == 0 || reg > RETU_REG_MAX ||
6168 +           retu_access_bits[reg] == READ_ONLY) {
6169 +               printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
6170 +                      reg, mask);
6171 +               return -EINVAL;
6172 +       }
6173 +
6174 +       /* Justify value according to mask */
6175 +       while (!(mask & 1)) {
6176 +               value = value << 1;
6177 +               mask = mask >> 1;
6178 +       }
6179 +
6180 +       spin_lock_irqsave(&retu_lock, flags);
6181 +       if (retu_access_bits[reg] == TOGGLE) {
6182 +               /* No need to detect previous content of register */
6183 +               tmp = 0;
6184 +       } else {
6185 +               /* Read current value of register */
6186 +               tmp = retu_read_reg(reg);
6187 +       }
6188 +
6189 +       /* Generate new value */
6190 +       tmp = (tmp & ~MASK(field)) | (value & MASK(field));
6191 +       /* Write data to RETU */
6192 +       retu_write_reg(reg, tmp);
6193 +       spin_unlock_irqrestore(&retu_lock, flags);
6194 +
6195 +       return 0;
6196 +}
6197 +
6198 +/*
6199 + * Read RETU register.
6200 + */
6201 +static u32 retu_user_read_with_mask(u32 field)
6202 +{
6203 +       u_short value;
6204 +       u32 mask, reg;
6205 +
6206 +       mask = MASK(field);
6207 +       reg = REG(field);
6208 +
6209 +       /* Detect bad mask and reg */
6210 +       if (mask == 0 || reg > RETU_REG_MAX) {
6211 +               printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
6212 +                      reg, mask);
6213 +               return -EINVAL;
6214 +       }
6215 +
6216 +       /* Read the register */
6217 +       value = retu_read_reg(reg) & mask;
6218 +
6219 +       /* Right justify value */
6220 +       while (!(mask & 1)) {
6221 +               value = value >> 1;
6222 +               mask = mask >> 1;
6223 +       }
6224 +
6225 +       return value;
6226 +}
6227 +
6228 +/*
6229 + * Close device
6230 + */
6231 +static int retu_close(struct inode *inode, struct file *filp)
6232 +{
6233 +       /* Unregister all interrupts that have been registered */
6234 +       if (retu_irq_subscr == filp) {
6235 +               retu_unreg_irq_handlers();
6236 +               retu_irq_subscr = NULL;
6237 +       }
6238 +
6239 +       return 0;
6240 +}
6241 +
6242 +/*
6243 + * Device control (ioctl)
6244 + */
6245 +static int retu_ioctl(struct inode *inode, struct file *filp,
6246 +                     unsigned int cmd, unsigned long arg)
6247 +{
6248 +       struct retu_tahvo_write_parms par;
6249 +       int ret;
6250 +
6251 +       switch (cmd) {
6252 +       case URT_IOCT_IRQ_SUBSCR:
6253 +               return retu_user_subscribe_to_irq(arg, filp);
6254 +       case RETU_IOCH_READ:
6255 +               return retu_user_read_with_mask(arg);
6256 +       case RETU_IOCX_WRITE:
6257 +               ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
6258 +               if (ret)
6259 +                       printk(KERN_ERR "copy_from_user failed: %d\n", ret);
6260 +               par.result = retu_user_write_with_mask(par.field, par.value);
6261 +               ret = copy_to_user((void __user *) arg, &par, sizeof(par));
6262 +               if (ret)
6263 +                       printk(KERN_ERR "copy_to_user failed: %d\n", ret);
6264 +               break;
6265 +       case RETU_IOCH_ADC_READ:
6266 +               return retu_read_adc(arg);
6267 +       default:
6268 +               return -ENOIOCTLCMD;
6269 +       }
6270 +       return 0;
6271 +}
6272 +
6273 +/*
6274 + * Read from device
6275 + */
6276 +static ssize_t retu_read(struct file *filp, char *buf, size_t count,
6277 +                        loff_t * offp)
6278 +{
6279 +       struct retu_irq *irq;
6280 +
6281 +       u32 nr, i;
6282 +
6283 +       /* read not permitted if neither filp nor anyone has registered IRQs */
6284 +       if (retu_irq_subscr != filp)
6285 +               return -EPERM;
6286 +
6287 +       if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0))
6288 +               return -EINVAL;
6289 +
6290 +       nr = count / sizeof(u32);
6291 +
6292 +       for (i = 0; i < nr; i++) {
6293 +               unsigned long flags;
6294 +               u32 irq_id;
6295 +               int ret;
6296 +
6297 +               ret = wait_event_interruptible(retu_user_waitqueue,
6298 +                                              !list_empty(&retu_irqs));
6299 +               if (ret < 0)
6300 +                       return ret;
6301 +
6302 +               spin_lock_irqsave(&retu_irqs_lock, flags);
6303 +               irq = list_entry((&retu_irqs)->next, struct retu_irq, node);
6304 +               irq_id = irq->id;
6305 +               list_move(&irq->node, &retu_irqs_reserve);
6306 +               spin_unlock_irqrestore(&retu_irqs_lock, flags);
6307 +
6308 +               ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
6309 +                                  sizeof(irq_id));
6310 +               if (ret)
6311 +                       printk(KERN_ERR "copy_to_user failed: %d\n", ret);
6312 +       }
6313 +
6314 +       return count;
6315 +}
6316 +
6317 +/*
6318 + * Poll method
6319 + */
6320 +static unsigned retu_poll(struct file *filp, struct poll_table_struct *pt)
6321 +{
6322 +       if (!list_empty(&retu_irqs))
6323 +               return POLLIN;
6324 +
6325 +       poll_wait(filp, &retu_user_waitqueue, pt);
6326 +
6327 +       if (!list_empty(&retu_irqs))
6328 +               return POLLIN;
6329 +       else
6330 +               return 0;
6331 +}
6332 +
6333 +static struct file_operations retu_user_fileops = {
6334 +       .owner = THIS_MODULE,
6335 +       .ioctl = retu_ioctl,
6336 +       .read = retu_read,
6337 +       .release = retu_close,
6338 +       .poll = retu_poll
6339 +};
6340 +
6341 +static struct miscdevice retu_device = {
6342 +       .minor = MISC_DYNAMIC_MINOR,
6343 +       .name = "retu",
6344 +       .fops = &retu_user_fileops
6345 +};
6346 +
6347 +/*
6348 + * Initialization
6349 + *
6350 + * @return 0 if successful, error value otherwise.
6351 + */
6352 +int retu_user_init(void)
6353 +{
6354 +       struct retu_irq *irq;
6355 +       int res, i;
6356 +
6357 +       irq = kmalloc(sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN, GFP_KERNEL);
6358 +       if (irq == NULL) {
6359 +               printk(KERN_ERR PFX "kmalloc failed\n");
6360 +               return -ENOMEM;
6361 +       }
6362 +       memset(irq, 0, sizeof(*irq) * RETU_MAX_IRQ_BUF_LEN);
6363 +       for (i = 0; i < RETU_MAX_IRQ_BUF_LEN; i++)
6364 +               list_add(&irq[i].node, &retu_irqs_reserve);
6365 +
6366 +       retu_irq_block = irq;
6367 +
6368 +       spin_lock_init(&retu_irqs_lock);
6369 +       mutex_init(&retu_mutex);
6370 +
6371 +       /* Request a misc device */
6372 +       res = misc_register(&retu_device);
6373 +       if (res < 0) {
6374 +               printk(KERN_ERR PFX "unable to register misc device for %s\n",
6375 +                      retu_device.name);
6376 +               kfree(irq);
6377 +               return res;
6378 +       }
6379 +
6380 +       return 0;
6381 +}
6382 +
6383 +/*
6384 + * Cleanup.
6385 + */
6386 +void retu_user_cleanup(void)
6387 +{
6388 +       /* Unregister our misc device */
6389 +       misc_deregister(&retu_device);
6390 +       /* Unregister and disable all RETU interrupts used by this module */
6391 +       retu_unreg_irq_handlers();
6392 +       kfree(retu_irq_block);
6393 +}
6394 +
6395 +MODULE_DESCRIPTION("Retu ASIC user space functions");
6396 +MODULE_LICENSE("GPL");
6397 +MODULE_AUTHOR("Mikko Ylinen");
6398 diff --git a/drivers/cbus/retu-wdt.c b/drivers/cbus/retu-wdt.c
6399 new file mode 100644
6400 index 0000000..b7b20b7
6401 --- /dev/null
6402 +++ b/drivers/cbus/retu-wdt.c
6403 @@ -0,0 +1,202 @@
6404 +/**
6405 + * drivers/cbus/retu-wdt.c
6406 + *
6407 + * Driver for Retu watchdog
6408 + *
6409 + * Copyright (C) 2004, 2005 Nokia Corporation
6410 + *
6411 + * Written by Amit Kucheria <amit.kucheria@nokia.com>
6412 + *
6413 + * This file is subject to the terms and conditions of the GNU General
6414 + * Public License. See the file "COPYING" in the main directory of this
6415 + * archive for more details.
6416 + *
6417 + * This program is distributed in the hope that it will be useful,
6418 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6419 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6420 + * GNU General Public License for more details.
6421 + *
6422 + * You should have received a copy of the GNU General Public License
6423 + * along with this program; if not, write to the Free Software
6424 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6425 + */
6426 +
6427 +#include <linux/kernel.h>
6428 +#include <linux/module.h>
6429 +#include <linux/device.h>
6430 +#include <linux/init.h>
6431 +
6432 +#include <linux/completion.h>
6433 +#include <linux/errno.h>
6434 +#include <linux/moduleparam.h>
6435 +#include <linux/platform_device.h>
6436 +
6437 +#include "cbus.h"
6438 +#include "retu.h"
6439 +
6440 +/* Watchdog timeout in seconds */
6441 +#define RETU_WDT_MIN_TIMER 0
6442 +#define RETU_WDT_DEFAULT_TIMER 32
6443 +#define RETU_WDT_MAX_TIMER 63
6444 +
6445 +static struct completion retu_wdt_completion;
6446 +static DEFINE_MUTEX(retu_wdt_mutex);
6447 +
6448 +/* Current period of watchdog */
6449 +static unsigned int period_val = RETU_WDT_DEFAULT_TIMER;
6450 +static int counter_param = RETU_WDT_MAX_TIMER;
6451 +
6452 +static int retu_modify_counter(unsigned int new)
6453 +{
6454 +       int ret = 0;
6455 +
6456 +       if (new < RETU_WDT_MIN_TIMER || new > RETU_WDT_MAX_TIMER)
6457 +               return -EINVAL;
6458 +
6459 +       mutex_lock(&retu_wdt_mutex);
6460 +
6461 +       period_val = new;
6462 +       retu_write_reg(RETU_REG_WATCHDOG, (u16)period_val);
6463 +
6464 +       mutex_unlock(&retu_wdt_mutex);
6465 +       return ret;
6466 +}
6467 +
6468 +static ssize_t retu_wdt_period_show(struct device *dev,
6469 +                               struct device_attribute *attr, char *buf)
6470 +{
6471 +       /* Show current max counter */
6472 +       return sprintf(buf, "%u\n", (u16)period_val);
6473 +}
6474 +
6475 +static ssize_t retu_wdt_period_store(struct device *dev,
6476 +                               struct device_attribute *attr,
6477 +                               const char *buf, size_t count)
6478 +{
6479 +       unsigned int new_period;
6480 +       int ret;
6481 +
6482 +       if (sscanf(buf, "%u", &new_period) != 1) {
6483 +               printk(KERN_ALERT "retu_wdt_period_store: Invalid input\n");
6484 +               return -EINVAL;
6485 +       }
6486 +
6487 +       ret = retu_modify_counter(new_period);
6488 +       if (ret < 0)
6489 +               return ret;
6490 +
6491 +       return strnlen(buf, count);
6492 +}
6493 +
6494 +static ssize_t retu_wdt_counter_show(struct device *dev,
6495 +                               struct device_attribute *attr, char *buf)
6496 +{
6497 +       u16 counter;
6498 +
6499 +       /* Show current value in watchdog counter */
6500 +       counter = retu_read_reg(RETU_REG_WATCHDOG);
6501 +
6502 +       /* Only the 5 LSB are important */
6503 +       return snprintf(buf, PAGE_SIZE, "%u\n", (counter & 0x3F));
6504 +}
6505 +
6506 +static DEVICE_ATTR(period, S_IRUGO | S_IWUSR, retu_wdt_period_show, \
6507 +                       retu_wdt_period_store);
6508 +static DEVICE_ATTR(counter, S_IRUGO, retu_wdt_counter_show, NULL);
6509 +
6510 +static int __devinit retu_wdt_probe(struct device *dev)
6511 +{
6512 +       int ret;
6513 +
6514 +       ret = device_create_file(dev, &dev_attr_period);
6515 +       if (ret) {
6516 +               printk(KERN_ERR "retu_wdt_probe: Error creating "
6517 +                                       "sys device file: period\n");
6518 +               return ret;
6519 +       }
6520 +
6521 +       ret = device_create_file(dev, &dev_attr_counter);
6522 +       if (ret) {
6523 +               device_remove_file(dev, &dev_attr_period);
6524 +               printk(KERN_ERR "retu_wdt_probe: Error creating "
6525 +                                       "sys device file: counter\n");
6526 +       }
6527 +
6528 +       return ret;
6529 +}
6530 +
6531 +static int __devexit retu_wdt_remove(struct device *dev)
6532 +{
6533 +       device_remove_file(dev, &dev_attr_period);
6534 +       device_remove_file(dev, &dev_attr_counter);
6535 +       return 0;
6536 +}
6537 +
6538 +static void retu_wdt_device_release(struct device *dev)
6539 +{
6540 +       complete(&retu_wdt_completion);
6541 +}
6542 +
6543 +static struct platform_device retu_wdt_device = {
6544 +       .name = "retu-watchdog",
6545 +       .id = -1,
6546 +       .dev = {
6547 +               .release = retu_wdt_device_release,
6548 +       },
6549 +};
6550 +
6551 +static struct device_driver retu_wdt_driver = {
6552 +       .name = "retu-watchdog",
6553 +       .bus = &platform_bus_type,
6554 +       .probe = retu_wdt_probe,
6555 +       .remove = __devexit_p(retu_wdt_remove),
6556 +};
6557 +
6558 +static int __init retu_wdt_init(void)
6559 +{
6560 +       int ret;
6561 +
6562 +       init_completion(&retu_wdt_completion);
6563 +
6564 +       ret = driver_register(&retu_wdt_driver);
6565 +       if (ret)
6566 +               return ret;
6567 +
6568 +       ret = platform_device_register(&retu_wdt_device);
6569 +       if (ret)
6570 +               goto exit1;
6571 +
6572 +       /* passed as module parameter? */
6573 +       ret = retu_modify_counter(counter_param);
6574 +       if (ret == -EINVAL) {
6575 +               ret = retu_modify_counter(RETU_WDT_DEFAULT_TIMER);
6576 +               printk(KERN_INFO
6577 +                      "retu_wdt_init: Intializing to default value\n");
6578 +       }
6579 +
6580 +       printk(KERN_INFO "Retu watchdog driver initialized\n");
6581 +       return ret;
6582 +
6583 +exit1:
6584 +       driver_unregister(&retu_wdt_driver);
6585 +       wait_for_completion(&retu_wdt_completion);
6586 +
6587 +       return ret;
6588 +}
6589 +
6590 +static void __exit retu_wdt_exit(void)
6591 +{
6592 +       platform_device_unregister(&retu_wdt_device);
6593 +       driver_unregister(&retu_wdt_driver);
6594 +
6595 +       wait_for_completion(&retu_wdt_completion);
6596 +}
6597 +
6598 +module_init(retu_wdt_init);
6599 +module_exit(retu_wdt_exit);
6600 +module_param(counter_param, int, 0);
6601 +
6602 +MODULE_DESCRIPTION("Retu WatchDog");
6603 +MODULE_AUTHOR("Amit Kucheria");
6604 +MODULE_LICENSE("GPL");
6605 +
6606 diff --git a/drivers/cbus/retu.c b/drivers/cbus/retu.c
6607 new file mode 100644
6608 index 0000000..84d7840
6609 --- /dev/null
6610 +++ b/drivers/cbus/retu.c
6611 @@ -0,0 +1,467 @@
6612 +/**
6613 + * drivers/cbus/retu.c
6614 + *
6615 + * Support functions for Retu ASIC
6616 + *
6617 + * Copyright (C) 2004, 2005 Nokia Corporation
6618 + *
6619 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
6620 + *           David Weinehall <david.weinehall@nokia.com>, and
6621 + *           Mikko Ylinen <mikko.k.ylinen@nokia.com>
6622 + *
6623 + * This file is subject to the terms and conditions of the GNU General
6624 + * Public License. See the file "COPYING" in the main directory of this
6625 + * archive for more details.
6626 + *
6627 + * This program is distributed in the hope that it will be useful,
6628 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6629 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6630 + * GNU General Public License for more details.
6631 + *
6632 + * You should have received a copy of the GNU General Public License
6633 + * along with this program; if not, write to the Free Software
6634 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6635 + */
6636 +
6637 +#include <linux/module.h>
6638 +#include <linux/init.h>
6639 +
6640 +#include <linux/kernel.h>
6641 +#include <linux/errno.h>
6642 +#include <linux/device.h>
6643 +#include <linux/miscdevice.h>
6644 +#include <linux/poll.h>
6645 +#include <linux/fs.h>
6646 +#include <linux/irq.h>
6647 +#include <linux/interrupt.h>
6648 +#include <linux/platform_device.h>
6649 +#include <linux/gpio.h>
6650 +
6651 +#include <asm/uaccess.h>
6652 +
6653 +#include <mach/mux.h>
6654 +#include <mach/board.h>
6655 +#include <mach/board-nokia.h>
6656 +
6657 +#include "cbus.h"
6658 +#include "retu.h"
6659 +
6660 +#define RETU_ID                        0x01
6661 +#define PFX                    "retu: "
6662 +
6663 +static int retu_initialized;
6664 +static int retu_irq_pin;
6665 +static int retu_is_vilma;
6666 +
6667 +static struct tasklet_struct retu_tasklet;
6668 +spinlock_t retu_lock = SPIN_LOCK_UNLOCKED;
6669 +
6670 +static struct completion device_release;
6671 +
6672 +struct retu_irq_handler_desc {
6673 +       int (*func)(unsigned long);
6674 +       unsigned long arg;
6675 +       char name[8];
6676 +};
6677 +
6678 +static struct retu_irq_handler_desc retu_irq_handlers[MAX_RETU_IRQ_HANDLERS];
6679 +
6680 +/**
6681 + * retu_read_reg - Read a value from a register in Retu
6682 + * @reg: the register to read from
6683 + *
6684 + * This function returns the contents of the specified register
6685 + */
6686 +int retu_read_reg(int reg)
6687 +{
6688 +       BUG_ON(!retu_initialized);
6689 +       return cbus_read_reg(cbus_host, RETU_ID, reg);
6690 +}
6691 +
6692 +/**
6693 + * retu_write_reg - Write a value to a register in Retu
6694 + * @reg: the register to write to
6695 + * @reg: the value to write to the register
6696 + *
6697 + * This function writes a value to the specified register
6698 + */
6699 +void retu_write_reg(int reg, u16 val)
6700 +{
6701 +       BUG_ON(!retu_initialized);
6702 +       cbus_write_reg(cbus_host, RETU_ID, reg, val);
6703 +}
6704 +
6705 +void retu_set_clear_reg_bits(int reg, u16 set, u16 clear)
6706 +{
6707 +       unsigned long flags;
6708 +       u16 w;
6709 +
6710 +       spin_lock_irqsave(&retu_lock, flags);
6711 +       w = retu_read_reg(reg);
6712 +       w &= ~clear;
6713 +       w |= set;
6714 +       retu_write_reg(reg, w);
6715 +       spin_unlock_irqrestore(&retu_lock, flags);
6716 +}
6717 +
6718 +#define ADC_MAX_CHAN_NUMBER    13
6719 +
6720 +int retu_read_adc(int channel)
6721 +{
6722 +       unsigned long flags;
6723 +       int res;
6724 +
6725 +       if (channel < 0 || channel > ADC_MAX_CHAN_NUMBER)
6726 +               return -EINVAL;
6727 +
6728 +       spin_lock_irqsave(&retu_lock, flags);
6729 +
6730 +       if ((channel == 8) && retu_is_vilma) {
6731 +               int scr = retu_read_reg(RETU_REG_ADCSCR);
6732 +               int ch = (retu_read_reg(RETU_REG_ADCR) >> 10) & 0xf;
6733 +               if (((scr & 0xff) != 0) && (ch != 8))
6734 +                       retu_write_reg (RETU_REG_ADCSCR, (scr & ~0xff));
6735 +       }
6736 +
6737 +       /* Select the channel and read result */
6738 +       retu_write_reg(RETU_REG_ADCR, channel << 10);
6739 +       res = retu_read_reg(RETU_REG_ADCR) & 0x3ff;
6740 +
6741 +       if (retu_is_vilma)
6742 +               retu_write_reg(RETU_REG_ADCR, (1 << 13));
6743 +
6744 +       /* Unlock retu */
6745 +       spin_unlock_irqrestore(&retu_lock, flags);
6746 +
6747 +       return res;
6748 +}
6749 +
6750 +
6751 +static u16 retu_disable_bogus_irqs(u16 mask)
6752 +{
6753 +       int i;
6754 +
6755 +       for (i = 0; i < MAX_RETU_IRQ_HANDLERS; i++) {
6756 +               if (mask & (1 << i))
6757 +                       continue;
6758 +               if (retu_irq_handlers[i].func != NULL)
6759 +                       continue;
6760 +               /* an IRQ was enabled but we don't have a handler for it */
6761 +               printk(KERN_INFO PFX "disabling bogus IRQ %d\n", i);
6762 +               mask |= (1 << i);
6763 +       }
6764 +       return mask;
6765 +}
6766 +
6767 +/*
6768 + * Disable given RETU interrupt
6769 + */
6770 +void retu_disable_irq(int id)
6771 +{
6772 +       unsigned long flags;
6773 +       u16 mask;
6774 +
6775 +       spin_lock_irqsave(&retu_lock, flags);
6776 +       mask = retu_read_reg(RETU_REG_IMR);
6777 +       mask |= 1 << id;
6778 +       mask = retu_disable_bogus_irqs(mask);
6779 +       retu_write_reg(RETU_REG_IMR, mask);
6780 +       spin_unlock_irqrestore(&retu_lock, flags);
6781 +}
6782 +
6783 +/*
6784 + * Enable given RETU interrupt
6785 + */
6786 +void retu_enable_irq(int id)
6787 +{
6788 +       unsigned long flags;
6789 +       u16 mask;
6790 +
6791 +       if (id == 3) {
6792 +               printk("Enabling Retu IRQ %d\n", id);
6793 +               dump_stack();
6794 +       }
6795 +       spin_lock_irqsave(&retu_lock, flags);
6796 +       mask = retu_read_reg(RETU_REG_IMR);
6797 +       mask &= ~(1 << id);
6798 +       mask = retu_disable_bogus_irqs(mask);
6799 +       retu_write_reg(RETU_REG_IMR, mask);
6800 +       spin_unlock_irqrestore(&retu_lock, flags);
6801 +}
6802 +
6803 +/*
6804 + * Acknowledge given RETU interrupt
6805 + */
6806 +void retu_ack_irq(int id)
6807 +{
6808 +       retu_write_reg(RETU_REG_IDR, 1 << id);
6809 +}
6810 +
6811 +/*
6812 + * RETU interrupt handler. Only schedules the tasklet.
6813 + */
6814 +static irqreturn_t retu_irq_handler(int irq, void *dev_id)
6815 +{
6816 +       tasklet_schedule(&retu_tasklet);
6817 +       return IRQ_HANDLED;
6818 +}
6819 +
6820 +/*
6821 + * Tasklet handler
6822 + */
6823 +static void retu_tasklet_handler(unsigned long data)
6824 +{
6825 +       struct retu_irq_handler_desc *hnd;
6826 +       u16 id;
6827 +       u16 im;
6828 +       int i;
6829 +
6830 +       for (;;) {
6831 +               id = retu_read_reg(RETU_REG_IDR);
6832 +               im = ~retu_read_reg(RETU_REG_IMR);
6833 +               id &= im;
6834 +
6835 +               if (!id)
6836 +                       break;
6837 +
6838 +               for (i = 0; id != 0; i++, id >>= 1) {
6839 +                       if (!(id & 1))
6840 +                               continue;
6841 +                       hnd = &retu_irq_handlers[i];
6842 +                       if (hnd->func == NULL) {
6843 +                               /* Spurious retu interrupt - disable and ack it */
6844 +                               printk(KERN_INFO "Spurious Retu interrupt "
6845 +                                                "(id %d)\n", i);
6846 +                               retu_disable_irq(i);
6847 +                               retu_ack_irq(i);
6848 +                               continue;
6849 +                       }
6850 +                       hnd->func(hnd->arg);
6851 +                       /*
6852 +                        * Don't acknowledge the interrupt here
6853 +                        * It must be done explicitly
6854 +                        */
6855 +               }
6856 +       }
6857 +}
6858 +
6859 +/*
6860 + * Register the handler for a given RETU interrupt source.
6861 + */
6862 +int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name)
6863 +{
6864 +       struct retu_irq_handler_desc *hnd;
6865 +
6866 +       if (irq_handler == NULL || id >= MAX_RETU_IRQ_HANDLERS ||
6867 +           name == NULL) {
6868 +               printk(KERN_ERR PFX "Invalid arguments to %s\n",
6869 +                      __FUNCTION__);
6870 +               return -EINVAL;
6871 +       }
6872 +       hnd = &retu_irq_handlers[id];
6873 +       if (hnd->func != NULL) {
6874 +               printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
6875 +               return -EBUSY;
6876 +       }
6877 +       printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
6878 +              id, name);
6879 +       hnd->func = irq_handler;
6880 +       hnd->arg = arg;
6881 +       strlcpy(hnd->name, name, sizeof(hnd->name));
6882 +
6883 +       retu_ack_irq(id);
6884 +       retu_enable_irq(id);
6885 +
6886 +       return 0;
6887 +}
6888 +
6889 +/*
6890 + * Unregister the handler for a given RETU interrupt source.
6891 + */
6892 +void retu_free_irq(int id)
6893 +{
6894 +       struct retu_irq_handler_desc *hnd;
6895 +
6896 +       if (id >= MAX_RETU_IRQ_HANDLERS) {
6897 +               printk(KERN_ERR PFX "Invalid argument to %s\n",
6898 +                      __FUNCTION__);
6899 +               return;
6900 +       }
6901 +       hnd = &retu_irq_handlers[id];
6902 +       if (hnd->func == NULL) {
6903 +               printk(KERN_ERR PFX "IRQ %d already freed\n", id);
6904 +               return;
6905 +       }
6906 +
6907 +       retu_disable_irq(id);
6908 +       hnd->func = NULL;
6909 +}
6910 +
6911 +/**
6912 + * retu_power_off - Shut down power to system
6913 + *
6914 + * This function puts the system in power off state
6915 + */
6916 +static void retu_power_off(void)
6917 +{
6918 +       /* Ignore power button state */
6919 +       retu_write_reg(RETU_REG_CC1, retu_read_reg(RETU_REG_CC1) | 2);
6920 +       /* Expire watchdog immediately */
6921 +       retu_write_reg(RETU_REG_WATCHDOG, 0);
6922 +       /* Wait for poweroff*/
6923 +       for (;;);
6924 +}
6925 +
6926 +/**
6927 + * retu_probe - Probe for Retu ASIC
6928 + * @dev: the Retu device
6929 + *
6930 + * Probe for the Retu ASIC and allocate memory
6931 + * for its device-struct if found
6932 + */
6933 +static int __devinit retu_probe(struct device *dev)
6934 +{
6935 +       const struct omap_em_asic_bb5_config * em_asic_config;
6936 +       int rev, ret;
6937 +
6938 +       /* Prepare tasklet */
6939 +       tasklet_init(&retu_tasklet, retu_tasklet_handler, 0);
6940 +
6941 +       em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5,
6942 +                                        struct omap_em_asic_bb5_config);
6943 +       if (em_asic_config == NULL) {
6944 +               printk(KERN_ERR PFX "Unable to retrieve config data\n");
6945 +               return -ENODATA;
6946 +       }
6947 +
6948 +       retu_irq_pin = em_asic_config->retu_irq_gpio;
6949 +
6950 +       if ((ret = gpio_request(retu_irq_pin, "RETU irq")) < 0) {
6951 +               printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
6952 +               return ret;
6953 +       }
6954 +
6955 +       /* Set the pin as input */
6956 +       gpio_direction_input(retu_irq_pin);
6957 +
6958 +       /* Rising edge triggers the IRQ */
6959 +       set_irq_type(gpio_to_irq(retu_irq_pin), IRQ_TYPE_EDGE_RISING);
6960 +
6961 +       retu_initialized = 1;
6962 +
6963 +       rev = retu_read_reg(RETU_REG_ASICR) & 0xff;
6964 +       if (rev & (1 << 7))
6965 +               retu_is_vilma = 1;
6966 +
6967 +       printk(KERN_INFO "%s v%d.%d found\n", retu_is_vilma ? "Vilma" : "Retu",
6968 +              (rev >> 4) & 0x07, rev & 0x0f);
6969 +
6970 +       /* Mask all RETU interrupts */
6971 +       retu_write_reg(RETU_REG_IMR, 0xffff);
6972 +
6973 +       ret = request_irq(gpio_to_irq(retu_irq_pin), retu_irq_handler, 0,
6974 +                         "retu", 0);
6975 +       if (ret < 0) {
6976 +               printk(KERN_ERR PFX "Unable to register IRQ handler\n");
6977 +               gpio_free(retu_irq_pin);
6978 +               return ret;
6979 +       }
6980 +       set_irq_wake(gpio_to_irq(retu_irq_pin), 1);
6981 +
6982 +       /* Register power off function */
6983 +       pm_power_off = retu_power_off;
6984 +
6985 +#ifdef CONFIG_CBUS_RETU_USER
6986 +       /* Initialize user-space interface */
6987 +       if (retu_user_init() < 0) {
6988 +               printk(KERN_ERR "Unable to initialize driver\n");
6989 +               free_irq(gpio_to_irq(retu_irq_pin), 0);
6990 +               gpio_free(retu_irq_pin);
6991 +               return ret;
6992 +       }
6993 +#endif
6994 +
6995 +       return 0;
6996 +}
6997 +
6998 +static int retu_remove(struct device *dev)
6999 +{
7000 +#ifdef CONFIG_CBUS_RETU_USER
7001 +       retu_user_cleanup();
7002 +#endif
7003 +       /* Mask all RETU interrupts */
7004 +       retu_write_reg(RETU_REG_IMR, 0xffff);
7005 +       free_irq(gpio_to_irq(retu_irq_pin), 0);
7006 +       gpio_free(retu_irq_pin);
7007 +       tasklet_kill(&retu_tasklet);
7008 +
7009 +       return 0;
7010 +}
7011 +
7012 +static void retu_device_release(struct device *dev)
7013 +{
7014 +       complete(&device_release);
7015 +}
7016 +
7017 +static struct device_driver retu_driver = {
7018 +       .name           = "retu",
7019 +       .bus            = &platform_bus_type,
7020 +       .probe          = retu_probe,
7021 +       .remove         = retu_remove,
7022 +};
7023 +
7024 +static struct platform_device retu_device = {
7025 +       .name           = "retu",
7026 +       .id             = -1,
7027 +       .dev = {
7028 +               .release = retu_device_release,
7029 +       }
7030 +};
7031 +
7032 +/**
7033 + * retu_init - initialise Retu driver
7034 + *
7035 + * Initialise the Retu driver and return 0 if everything worked ok
7036 + */
7037 +static int __init retu_init(void)
7038 +{
7039 +       int ret = 0;
7040 +
7041 +       printk(KERN_INFO "Retu/Vilma driver initialising\n");
7042 +
7043 +       init_completion(&device_release);
7044 +
7045 +       if ((ret = driver_register(&retu_driver)) < 0)
7046 +               return ret;
7047 +
7048 +       if ((ret = platform_device_register(&retu_device)) < 0) {
7049 +               driver_unregister(&retu_driver);
7050 +               return ret;
7051 +       }
7052 +       return 0;
7053 +}
7054 +
7055 +/*
7056 + * Cleanup
7057 + */
7058 +static void __exit retu_exit(void)
7059 +{
7060 +       platform_device_unregister(&retu_device);
7061 +       driver_unregister(&retu_driver);
7062 +       wait_for_completion(&device_release);
7063 +}
7064 +
7065 +EXPORT_SYMBOL(retu_request_irq);
7066 +EXPORT_SYMBOL(retu_free_irq);
7067 +EXPORT_SYMBOL(retu_enable_irq);
7068 +EXPORT_SYMBOL(retu_disable_irq);
7069 +EXPORT_SYMBOL(retu_ack_irq);
7070 +EXPORT_SYMBOL(retu_read_reg);
7071 +EXPORT_SYMBOL(retu_write_reg);
7072 +
7073 +subsys_initcall(retu_init);
7074 +module_exit(retu_exit);
7075 +
7076 +MODULE_DESCRIPTION("Retu ASIC control");
7077 +MODULE_LICENSE("GPL");
7078 +MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen");
7079 diff --git a/drivers/cbus/retu.h b/drivers/cbus/retu.h
7080 new file mode 100644
7081 index 0000000..c9e044c
7082 --- /dev/null
7083 +++ b/drivers/cbus/retu.h
7084 @@ -0,0 +1,77 @@
7085 +/**
7086 + * drivers/cbus/retu.h
7087 + *
7088 + * Copyright (C) 2004, 2005 Nokia Corporation
7089 + *
7090 + * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
7091 + *           David Weinehall <david.weinehall@nokia.com>
7092 + *
7093 + * This file is subject to the terms and conditions of the GNU General
7094 + * Public License. See the file "COPYING" in the main directory of this
7095 + * archive for more details.
7096 + *
7097 + * This program is distributed in the hope that it will be useful,
7098 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7099 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7100 + * GNU General Public License for more details.
7101 +
7102 + * You should have received a copy of the GNU General Public License
7103 + * along with this program; if not, write to the Free Software
7104 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7105 + */
7106 +
7107 +#ifndef __DRIVERS_CBUS_RETU_H
7108 +#define __DRIVERS_CBUS_RETU_H
7109 +
7110 +#include <linux/types.h>
7111 +
7112 +/* Registers */
7113 +#define RETU_REG_ASICR         0x00    /* ASIC ID & revision */
7114 +#define RETU_REG_IDR           0x01    /* Interrupt ID */
7115 +#define RETU_REG_IMR           0x02    /* Interrupt mask */
7116 +#define RETU_REG_RTCDSR                0x03    /* RTC seconds register */
7117 +#define RETU_REG_RTCHMR                0x04    /* RTC hours and minutes register */
7118 +#define RETU_REG_RTCHMAR       0x05    /* RTC hours and minutes alarm and time set register */
7119 +#define RETU_REG_RTCCALR       0x06    /* RTC calibration register */
7120 +#define RETU_REG_ADCR          0x08    /* ADC result */
7121 +#define RETU_REG_ADCSCR                0x09    /* ADC sample ctrl */
7122 +#define RETU_REG_CC1           0x0d    /* Common control register 1 */
7123 +#define RETU_REG_CC2           0x0e    /* Common control register 2 */
7124 +#define RETU_REG_CTRL_CLR      0x0f    /* Regulator clear register */
7125 +#define RETU_REG_CTRL_SET      0x10    /* Regulator set register */
7126 +#define RETU_REG_STATUS                0x16    /* Status register */
7127 +#define RETU_REG_WATCHDOG      0x17    /* Watchdog register */
7128 +#define RETU_REG_AUDTXR                0x18    /* Audio Codec Tx register */
7129 +#define RETU_REG_MAX           0x1f
7130 +
7131 +/* Interrupt sources */
7132 +#define RETU_INT_PWR           0
7133 +#define RETU_INT_CHAR          1
7134 +#define RETU_INT_RTCS          2
7135 +#define RETU_INT_RTCM          3
7136 +#define RETU_INT_RTCD          4
7137 +#define RETU_INT_RTCA          5
7138 +#define RETU_INT_HOOK          6
7139 +#define RETU_INT_HEAD          7
7140 +#define RETU_INT_ADCS          8
7141 +
7142 +#define        MAX_RETU_IRQ_HANDLERS   16
7143 +
7144 +int retu_read_reg(int reg);
7145 +void retu_write_reg(int reg, u16 val);
7146 +void retu_set_clear_reg_bits(int reg, u16 set, u16 clear);
7147 +int retu_read_adc(int channel);
7148 +int retu_request_irq(int id, void *irq_handler, unsigned long arg, char *name);
7149 +void retu_free_irq(int id);
7150 +void retu_enable_irq(int id);
7151 +void retu_disable_irq(int id);
7152 +void retu_ack_irq(int id);
7153 +
7154 +#ifdef CONFIG_CBUS_RETU_USER
7155 +int retu_user_init(void);
7156 +void retu_user_cleanup(void);
7157 +#endif
7158 +
7159 +extern spinlock_t retu_lock;
7160 +
7161 +#endif /* __DRIVERS_CBUS_RETU_H */
7162 diff --git a/drivers/cbus/tahvo-usb.c b/drivers/cbus/tahvo-usb.c
7163 new file mode 100644
7164 index 0000000..d8ad836
7165 --- /dev/null
7166 +++ b/drivers/cbus/tahvo-usb.c
7167 @@ -0,0 +1,777 @@
7168 +/**
7169 + * drivers/cbus/tahvo-usb.c
7170 + *
7171 + * Tahvo USB transeiver
7172 + *
7173 + * Copyright (C) 2005-2006 Nokia Corporation
7174 + *
7175 + * Parts copied from drivers/i2c/chips/isp1301_omap.c
7176 + * Copyright (C) 2004 Texas Instruments
7177 + * Copyright (C) 2004 David Brownell
7178 + *
7179 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
7180 + *           Tony Lindgren <tony@atomide.com>, and
7181 + *           Timo Teräs <timo.teras@nokia.com>
7182 + *
7183 + * This file is subject to the terms and conditions of the GNU General
7184 + * Public License. See the file "COPYING" in the main directory of this
7185 + * archive for more details.
7186 + *
7187 + * This program is distributed in the hope that it will be useful,
7188 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7189 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7190 + * GNU General Public License for more details.
7191 + *
7192 + * You should have received a copy of the GNU General Public License
7193 + * along with this program; if not, write to the Free Software
7194 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7195 + */
7196 +
7197 +#include <linux/kernel.h>
7198 +#include <linux/module.h>
7199 +#include <linux/init.h>
7200 +#include <linux/slab.h>
7201 +#include <linux/io.h>
7202 +#include <linux/interrupt.h>
7203 +#include <linux/platform_device.h>
7204 +#include <linux/usb/ch9.h>
7205 +#include <linux/usb/gadget.h>
7206 +#include <linux/usb.h>
7207 +#include <linux/usb/otg.h>
7208 +#include <linux/i2c.h>
7209 +#include <linux/workqueue.h>
7210 +#include <linux/kobject.h>
7211 +#include <linux/clk.h>
7212 +#include <linux/mutex.h>
7213 +
7214 +#include <asm/irq.h>
7215 +#include <mach/usb.h>
7216 +
7217 +#include "cbus.h"
7218 +#include "tahvo.h"
7219 +
7220 +#define DRIVER_NAME     "tahvo-usb"
7221 +
7222 +#define USBR_SLAVE_CONTROL     (1 << 8)
7223 +#define USBR_VPPVIO_SW         (1 << 7)
7224 +#define USBR_SPEED             (1 << 6)
7225 +#define USBR_REGOUT            (1 << 5)
7226 +#define USBR_MASTER_SW2                (1 << 4)
7227 +#define USBR_MASTER_SW1                (1 << 3)
7228 +#define USBR_SLAVE_SW          (1 << 2)
7229 +#define USBR_NSUSPEND          (1 << 1)
7230 +#define USBR_SEMODE            (1 << 0)
7231 +
7232 +/* bits in OTG_CTRL */
7233 +
7234 +/* Bits that are controlled by OMAP OTG and are read-only */
7235 +#define OTG_CTRL_OMAP_MASK     (OTG_PULLDOWN|OTG_PULLUP|OTG_DRV_VBUS|\
7236 +                               OTG_PD_VBUS|OTG_PU_VBUS|OTG_PU_ID)
7237 +/* Bits that are controlled by transceiver */
7238 +#define OTG_CTRL_XCVR_MASK     (OTG_ASESSVLD|OTG_BSESSEND|\
7239 +                               OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID)
7240 +/* Bits that are controlled by system */
7241 +#define OTG_CTRL_SYS_MASK      (OTG_A_BUSREQ|OTG_A_SETB_HNPEN|OTG_B_BUSREQ|\
7242 +                               OTG_B_HNPEN|OTG_BUSDROP)
7243 +
7244 +#if defined(CONFIG_USB_OHCI_HCD) && !defined(CONFIG_USB_OTG)
7245 +#error tahvo-otg.c does not work with OCHI yet!
7246 +#endif
7247 +
7248 +#define TAHVO_MODE_HOST                0
7249 +#define TAHVO_MODE_PERIPHERAL  1
7250 +
7251 +#ifdef CONFIG_USB_OTG
7252 +#define TAHVO_MODE(tu)         (tu)->tahvo_mode
7253 +#elif defined(CONFIG_USB_GADGET_OMAP)
7254 +#define TAHVO_MODE(tu)         TAHVO_MODE_PERIPHERAL
7255 +#else
7256 +#define TAHVO_MODE(tu)         TAHVO_MODE_HOST
7257 +#endif
7258 +
7259 +struct tahvo_usb {
7260 +       struct platform_device *pt_dev;
7261 +       struct otg_transceiver otg;
7262 +       int vbus_state;
7263 +       struct work_struct irq_work;
7264 +       struct mutex serialize;
7265 +#ifdef CONFIG_USB_OTG
7266 +       int tahvo_mode;
7267 +#endif
7268 +};
7269 +static struct platform_device tahvo_usb_device;
7270 +
7271 +/*
7272 + * ---------------------------------------------------------------------------
7273 + * OTG related functions
7274 + *
7275 + * These shoud be separated into omap-otg.c driver module, as they are used
7276 + * by various transceivers. These functions are needed in the UDC-only case
7277 + * as well. These functions are copied from GPL isp1301_omap.c
7278 + * ---------------------------------------------------------------------------
7279 + */
7280 +static struct platform_device *tahvo_otg_dev;
7281 +
7282 +static irqreturn_t omap_otg_irq(int irq, void *arg)
7283 +{
7284 +       struct platform_device *otg_dev = (struct platform_device *) arg;
7285 +       struct tahvo_usb *tu = (struct tahvo_usb *) otg_dev->dev.driver_data;
7286 +       u16 otg_irq;
7287 +
7288 +       otg_irq = omap_readw(OTG_IRQ_SRC);
7289 +       if (otg_irq & OPRT_CHG) {
7290 +               omap_writew(OPRT_CHG, OTG_IRQ_SRC);
7291 +       } else if (otg_irq & B_SRP_TMROUT) {
7292 +               omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
7293 +       } else if (otg_irq & B_HNP_FAIL) {
7294 +               omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
7295 +       } else if (otg_irq & A_SRP_DETECT) {
7296 +               omap_writew(A_SRP_DETECT, OTG_IRQ_SRC);
7297 +       } else if (otg_irq & A_REQ_TMROUT) {
7298 +               omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
7299 +       } else if (otg_irq & A_VBUS_ERR) {
7300 +               omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
7301 +       } else if (otg_irq & DRIVER_SWITCH) {
7302 +               if ((!(omap_readl(OTG_CTRL) & OTG_DRIVER_SEL)) &&
7303 +                  tu->otg.host && tu->otg.state == OTG_STATE_A_HOST) {
7304 +                       /* role is host */
7305 +                       usb_bus_start_enum(tu->otg.host,
7306 +                                          tu->otg.host->otg_port);
7307 +               }
7308 +               omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC);
7309 +       } else
7310 +               return IRQ_NONE;
7311 +
7312 +       return IRQ_HANDLED;
7313 +
7314 +}
7315 +
7316 +static int omap_otg_init(void)
7317 +{
7318 +       u32 l;
7319 +
7320 +#ifdef CONFIG_USB_OTG
7321 +       if (!tahvo_otg_dev) {
7322 +               printk("tahvo-usb: no tahvo_otg_dev\n");
7323 +               return -ENODEV;
7324 +       }
7325 +#endif
7326 +
7327 +       l = omap_readl(OTG_SYSCON_1);
7328 +       l &= ~OTG_IDLE_EN;
7329 +       omap_writel(l, OTG_SYSCON_1);
7330 +       udelay(100);
7331 +
7332 +       /* some of these values are board-specific... */
7333 +       l = omap_readl(OTG_SYSCON_2);
7334 +       l |= OTG_EN
7335 +               /* for B-device: */
7336 +               | SRP_GPDATA            /* 9msec Bdev D+ pulse */
7337 +               | SRP_GPDVBUS           /* discharge after VBUS pulse */
7338 +               // | (3 << 24)          /* 2msec VBUS pulse */
7339 +               /* for A-device: */
7340 +               | (0 << 20)             /* 200ms nominal A_WAIT_VRISE timer */
7341 +               | SRP_DPW               /* detect 167+ns SRP pulses */
7342 +               | SRP_DATA | SRP_VBUS;  /* accept both kinds of SRP pulse */
7343 +       omap_writel(l, OTG_SYSCON_2);
7344 +
7345 +       omap_writew(DRIVER_SWITCH | OPRT_CHG
7346 +                       | B_SRP_TMROUT | B_HNP_FAIL
7347 +                                 | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT,
7348 +                                       OTG_IRQ_EN);
7349 +       l = omap_readl(OTG_SYSCON_2);
7350 +       l |= OTG_EN;
7351 +       omap_writel(l, OTG_SYSCON_2);
7352 +
7353 +       return 0;
7354 +}
7355 +
7356 +static int omap_otg_probe(struct device *dev)
7357 +{
7358 +       int ret;
7359 +
7360 +       tahvo_otg_dev = to_platform_device(dev);
7361 +       ret = omap_otg_init();
7362 +       if (ret != 0) {
7363 +               printk(KERN_ERR "tahvo-usb: omap_otg_init failed\n");
7364 +               return ret;
7365 +       }
7366 +
7367 +       return request_irq(tahvo_otg_dev->resource[1].start,
7368 +                          omap_otg_irq, IRQF_DISABLED, DRIVER_NAME,
7369 +                          &tahvo_usb_device);
7370 +}
7371 +
7372 +static int omap_otg_remove(struct device *dev)
7373 +{
7374 +       free_irq(tahvo_otg_dev->resource[1].start, &tahvo_usb_device);
7375 +       tahvo_otg_dev = NULL;
7376 +
7377 +       return 0;
7378 +}
7379 +
7380 +struct device_driver omap_otg_driver = {
7381 +       .name           = "omap_otg",
7382 +       .bus            = &platform_bus_type,
7383 +       .probe          = omap_otg_probe,
7384 +       .remove         = omap_otg_remove,
7385 +};
7386 +
7387 +/*
7388 + * ---------------------------------------------------------------------------
7389 + * Tahvo related functions
7390 + * These are Nokia proprietary code, except for the OTG register settings,
7391 + * which are copied from isp1301.c
7392 + * ---------------------------------------------------------------------------
7393 + */
7394 +static ssize_t vbus_state_show(struct device *device,
7395 +                              struct device_attribute *attr, char *buf)
7396 +{
7397 +       struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data;
7398 +       return sprintf(buf, "%d\n", tu->vbus_state);
7399 +}
7400 +static DEVICE_ATTR(vbus_state, 0444, vbus_state_show, NULL);
7401 +
7402 +int vbus_active = 0;
7403 +
7404 +#if 0
7405 +
7406 +static int host_suspend(struct tahvo_usb *tu)
7407 +{
7408 +       struct device   *dev;
7409 +
7410 +       if (!tu->otg.host)
7411 +               return -ENODEV;
7412 +
7413 +       /* Currently ASSUMES only the OTG port matters;
7414 +        * other ports could be active...
7415 +        */
7416 +       dev = tu->otg.host->controller;
7417 +       return dev->driver->suspend(dev, PMSG_SUSPEND);
7418 +}
7419 +
7420 +static int host_resume(struct tahvo_usb *tu)
7421 +{
7422 +       struct device   *dev;
7423 +
7424 +       if (!tu->otg.host)
7425 +               return -ENODEV;
7426 +
7427 +       dev = tu->otg.host->controller;
7428 +       return dev->driver->resume(dev);
7429 +}
7430 +
7431 +#else
7432 +
7433 +static int host_suspend(struct tahvo_usb *tu)
7434 +{
7435 +       return 0;
7436 +}
7437 +
7438 +static int host_resume(struct tahvo_usb *tu)
7439 +{
7440 +       return 0;
7441 +}
7442 +
7443 +#endif
7444 +
7445 +static void check_vbus_state(struct tahvo_usb *tu)
7446 +{
7447 +       int reg, prev_state;
7448 +
7449 +       reg = tahvo_read_reg(TAHVO_REG_IDSR);
7450 +       if (reg & 0x01) {
7451 +               u32 l;
7452 +
7453 +               vbus_active = 1;
7454 +               switch (tu->otg.state) {
7455 +               case OTG_STATE_B_IDLE:
7456 +                       /* Enable the gadget driver */
7457 +                       if (tu->otg.gadget)
7458 +                               usb_gadget_vbus_connect(tu->otg.gadget);
7459 +                       /* Set B-session valid and not B-sessio ended to indicate
7460 +                        * Vbus to be ok. */
7461 +                       l = omap_readl(OTG_CTRL);
7462 +                       l &= ~OTG_BSESSEND;
7463 +                       l |= OTG_BSESSVLD;
7464 +                       omap_writel(l, OTG_CTRL);
7465 +
7466 +                       tu->otg.state = OTG_STATE_B_PERIPHERAL;
7467 +                       break;
7468 +               case OTG_STATE_A_IDLE:
7469 +                       /* Session is now valid assuming the USB hub is driving Vbus */
7470 +                       tu->otg.state = OTG_STATE_A_HOST;
7471 +                       host_resume(tu);
7472 +                       break;
7473 +               default:
7474 +                       break;
7475 +               }
7476 +               printk("USB cable connected\n");
7477 +       } else {
7478 +               switch (tu->otg.state) {
7479 +               case OTG_STATE_B_PERIPHERAL:
7480 +                       if (tu->otg.gadget)
7481 +                               usb_gadget_vbus_disconnect(tu->otg.gadget);
7482 +                       tu->otg.state = OTG_STATE_B_IDLE;
7483 +                       break;
7484 +               case OTG_STATE_A_HOST:
7485 +                       tu->otg.state = OTG_STATE_A_IDLE;
7486 +                       break;
7487 +               default:
7488 +                       break;
7489 +               }
7490 +               printk("USB cable disconnected\n");
7491 +               vbus_active = 0;
7492 +       }
7493 +
7494 +       prev_state = tu->vbus_state;
7495 +       tu->vbus_state = reg & 0x01;
7496 +       if (prev_state != tu->vbus_state)
7497 +               sysfs_notify(&tu->pt_dev->dev.kobj, NULL, "vbus_state");
7498 +}
7499 +
7500 +static void tahvo_usb_become_host(struct tahvo_usb *tu)
7501 +{
7502 +       u32 l;
7503 +
7504 +       /* Clear system and transceiver controlled bits
7505 +        * also mark the A-session is always valid */
7506 +       omap_otg_init();
7507 +
7508 +       l = omap_readl(OTG_CTRL);
7509 +       l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK);
7510 +       l |= OTG_ASESSVLD;
7511 +       omap_writel(l, OTG_CTRL);
7512 +
7513 +       /* Power up the transceiver in USB host mode */
7514 +       tahvo_write_reg(TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND |
7515 +                       USBR_MASTER_SW2 | USBR_MASTER_SW1);
7516 +       tu->otg.state = OTG_STATE_A_IDLE;
7517 +
7518 +       check_vbus_state(tu);
7519 +}
7520 +
7521 +static void tahvo_usb_stop_host(struct tahvo_usb *tu)
7522 +{
7523 +       host_suspend(tu);
7524 +       tu->otg.state = OTG_STATE_A_IDLE;
7525 +}
7526 +
7527 +static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
7528 +{
7529 +       u32 l;
7530 +
7531 +       /* Clear system and transceiver controlled bits
7532 +        * and enable ID to mark peripheral mode and
7533 +        * BSESSEND to mark no Vbus */
7534 +       omap_otg_init();
7535 +       l = omap_readl(OTG_CTRL);
7536 +       l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
7537 +       l |= OTG_ID | OTG_BSESSEND;
7538 +       omap_writel(l, OTG_CTRL);
7539 +
7540 +       /* Power up transceiver and set it in USB perhiperal mode */
7541 +       tahvo_write_reg(TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT | USBR_NSUSPEND | USBR_SLAVE_SW);
7542 +       tu->otg.state = OTG_STATE_B_IDLE;
7543 +
7544 +       check_vbus_state(tu);
7545 +}
7546 +
7547 +static void tahvo_usb_stop_peripheral(struct tahvo_usb *tu)
7548 +{
7549 +       u32 l;
7550 +
7551 +       l = omap_readl(OTG_CTRL);
7552 +       l &= ~OTG_BSESSVLD;
7553 +       l |= OTG_BSESSEND;
7554 +       omap_writel(l, OTG_CTRL);
7555 +
7556 +       if (tu->otg.gadget)
7557 +               usb_gadget_vbus_disconnect(tu->otg.gadget);
7558 +       tu->otg.state = OTG_STATE_B_IDLE;
7559 +
7560 +}
7561 +
7562 +static void tahvo_usb_power_off(struct tahvo_usb *tu)
7563 +{
7564 +       u32 l;
7565 +       int id;
7566 +
7567 +       /* Disable gadget controller if any */
7568 +       if (tu->otg.gadget)
7569 +               usb_gadget_vbus_disconnect(tu->otg.gadget);
7570 +
7571 +       host_suspend(tu);
7572 +
7573 +       /* Disable OTG and interrupts */
7574 +       if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7575 +               id = OTG_ID;
7576 +       else
7577 +               id = 0;
7578 +       l = omap_readl(OTG_CTRL);
7579 +       l &= ~(OTG_CTRL_XCVR_MASK | OTG_CTRL_SYS_MASK | OTG_BSESSVLD);
7580 +       l |= id | OTG_BSESSEND;
7581 +       omap_writel(l, OTG_CTRL);
7582 +       omap_writew(0, OTG_IRQ_EN);
7583 +
7584 +       l = omap_readl(OTG_SYSCON_2);
7585 +       l &= ~OTG_EN;
7586 +       omap_writel(l, OTG_SYSCON_2);
7587 +
7588 +       l = omap_readl(OTG_SYSCON_1);
7589 +       l |= OTG_IDLE_EN;
7590 +       omap_writel(l, OTG_SYSCON_1);
7591 +
7592 +       /* Power off transceiver */
7593 +       tahvo_write_reg(TAHVO_REG_USBR, 0);
7594 +       tu->otg.state = OTG_STATE_UNDEFINED;
7595 +}
7596 +
7597 +
7598 +static int tahvo_usb_set_power(struct otg_transceiver *dev, unsigned mA)
7599 +{
7600 +       struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7601 +
7602 +       dev_dbg(&tu->pt_dev->dev, "set_power %d mA\n", mA);
7603 +
7604 +       if (dev->state == OTG_STATE_B_PERIPHERAL) {
7605 +               /* REVISIT: Can Tahvo charge battery from VBUS? */
7606 +       }
7607 +       return 0;
7608 +}
7609 +
7610 +static int tahvo_usb_set_suspend(struct otg_transceiver *dev, int suspend)
7611 +{
7612 +       struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7613 +       u16 w;
7614 +
7615 +       dev_dbg(&tu->pt_dev->dev, "set_suspend\n");
7616 +
7617 +       w = tahvo_read_reg(TAHVO_REG_USBR);
7618 +       if (suspend)
7619 +               w &= ~USBR_NSUSPEND;
7620 +       else
7621 +               w |= USBR_NSUSPEND;
7622 +       tahvo_write_reg(TAHVO_REG_USBR, w);
7623 +
7624 +       return 0;
7625 +}
7626 +
7627 +static int tahvo_usb_start_srp(struct otg_transceiver *dev)
7628 +{
7629 +       struct tahvo_usb *tu = container_of(dev, struct tahvo_usb, otg);
7630 +       u32 otg_ctrl;
7631 +
7632 +       dev_dbg(&tu->pt_dev->dev, "start_srp\n");
7633 +
7634 +       if (!dev || tu->otg.state != OTG_STATE_B_IDLE)
7635 +               return -ENODEV;
7636 +
7637 +       otg_ctrl = omap_readl(OTG_CTRL);
7638 +       if (!(otg_ctrl & OTG_BSESSEND))
7639 +               return -EINVAL;
7640 +
7641 +       otg_ctrl |= OTG_B_BUSREQ;
7642 +       otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_SYS_MASK;
7643 +       omap_writel(otg_ctrl, OTG_CTRL);
7644 +       tu->otg.state = OTG_STATE_B_SRP_INIT;
7645 +
7646 +       return 0;
7647 +}
7648 +
7649 +static int tahvo_usb_start_hnp(struct otg_transceiver *otg)
7650 +{
7651 +       struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7652 +
7653 +       dev_dbg(&tu->pt_dev->dev, "start_hnp\n");
7654 +#ifdef CONFIG_USB_OTG
7655 +       /* REVISIT: Add this for OTG */
7656 +#endif
7657 +       return -EINVAL;
7658 +}
7659 +
7660 +static int tahvo_usb_set_host(struct otg_transceiver *otg, struct usb_bus *host)
7661 +{
7662 +       struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7663 +       u32 l;
7664 +
7665 +       dev_dbg(&tu->pt_dev->dev, "set_host %p\n", host);
7666 +
7667 +       if (otg == NULL)
7668 +               return -ENODEV;
7669 +
7670 +#if defined(CONFIG_USB_OTG) || !defined(CONFIG_USB_GADGET_OMAP)
7671 +
7672 +       mutex_lock(&tu->serialize);
7673 +
7674 +       if (host == NULL) {
7675 +               if (TAHVO_MODE(tu) == TAHVO_MODE_HOST)
7676 +                       tahvo_usb_power_off(tu);
7677 +               tu->otg.host = NULL;
7678 +               mutex_unlock(&tu->serialize);
7679 +               return 0;
7680 +       }
7681 +
7682 +       l = omap_readl(OTG_SYSCON_1);
7683 +       l &= ~(OTG_IDLE_EN | HST_IDLE_EN | DEV_IDLE_EN);
7684 +       omap_writel(l, OTG_SYSCON_1);
7685 +
7686 +       if (TAHVO_MODE(tu) == TAHVO_MODE_HOST) {
7687 +               tu->otg.host = NULL;
7688 +               tahvo_usb_become_host(tu);
7689 +       } else
7690 +               host_suspend(tu);
7691 +
7692 +       tu->otg.host = host;
7693 +
7694 +       mutex_unlock(&tu->serialize);
7695 +#else
7696 +       /* No host mode configured, so do not allow host controlled to be set */
7697 +       return -EINVAL;
7698 +#endif
7699 +
7700 +       return 0;
7701 +}
7702 +
7703 +static int tahvo_usb_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget)
7704 +{
7705 +       struct tahvo_usb *tu = container_of(otg, struct tahvo_usb, otg);
7706 +
7707 +       dev_dbg(&tu->pt_dev->dev, "set_peripheral %p\n", gadget);
7708 +
7709 +       if (!otg)
7710 +               return -ENODEV;
7711 +
7712 +#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_GADGET_OMAP)
7713 +
7714 +       mutex_lock(&tu->serialize);
7715 +
7716 +       if (!gadget) {
7717 +               if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7718 +                       tahvo_usb_power_off(tu);
7719 +               tu->otg.gadget = NULL;
7720 +               mutex_unlock(&tu->serialize);
7721 +               return 0;
7722 +       }
7723 +
7724 +       tu->otg.gadget = gadget;
7725 +       if (TAHVO_MODE(tu) == TAHVO_MODE_PERIPHERAL)
7726 +               tahvo_usb_become_peripheral(tu);
7727 +
7728 +       mutex_unlock(&tu->serialize);
7729 +#else
7730 +       /* No gadget mode configured, so do not allow host controlled to be set */
7731 +       return -EINVAL;
7732 +#endif
7733 +
7734 +       return 0;
7735 +}
7736 +
7737 +static void tahvo_usb_irq_work(struct work_struct *work)
7738 +{
7739 +       struct tahvo_usb *tu = container_of(work, struct tahvo_usb, irq_work);
7740 +
7741 +       mutex_lock(&tu->serialize);
7742 +       check_vbus_state(tu);
7743 +       mutex_unlock(&tu->serialize);
7744 +}
7745 +
7746 +static void tahvo_usb_vbus_interrupt(unsigned long arg)
7747 +{
7748 +       struct tahvo_usb *tu = (struct tahvo_usb *) arg;
7749 +
7750 +       tahvo_ack_irq(TAHVO_INT_VBUSON);
7751 +       /* Seems we need this to acknowledge the interrupt */
7752 +       tahvo_read_reg(TAHVO_REG_IDSR);
7753 +       schedule_work(&tu->irq_work);
7754 +}
7755 +
7756 +#ifdef CONFIG_USB_OTG
7757 +static ssize_t otg_mode_show(struct device *device,
7758 +                            struct device_attribute *attr, char *buf)
7759 +{
7760 +       struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data;
7761 +       switch (tu->tahvo_mode) {
7762 +       case TAHVO_MODE_HOST:
7763 +               return sprintf(buf, "host\n");
7764 +       case TAHVO_MODE_PERIPHERAL:
7765 +               return sprintf(buf, "peripheral\n");
7766 +       }
7767 +       return sprintf(buf, "unknown\n");
7768 +}
7769 +
7770 +static ssize_t otg_mode_store(struct device *device,
7771 +                             struct device_attribute *attr,
7772 +                             const char *buf, size_t count)
7773 +{
7774 +       struct tahvo_usb *tu = (struct tahvo_usb*) device->driver_data;
7775 +       int r;
7776 +
7777 +       r = strlen(buf);
7778 +       mutex_lock(&tu->serialize);
7779 +       if (strncmp(buf, "host", 4) == 0) {
7780 +               if (tu->tahvo_mode == TAHVO_MODE_PERIPHERAL)
7781 +                       tahvo_usb_stop_peripheral(tu);
7782 +               tu->tahvo_mode = TAHVO_MODE_HOST;
7783 +               if (tu->otg.host) {
7784 +                       printk(KERN_INFO "Selected HOST mode: host controller present.\n");
7785 +                       tahvo_usb_become_host(tu);
7786 +               } else {
7787 +                       printk(KERN_INFO "Selected HOST mode: no host controller, powering off.\n");
7788 +                       tahvo_usb_power_off(tu);
7789 +               }
7790 +       } else if (strncmp(buf, "peripheral", 10) == 0) {
7791 +               if (tu->tahvo_mode == TAHVO_MODE_HOST)
7792 +                       tahvo_usb_stop_host(tu);
7793 +               tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
7794 +               if (tu->otg.gadget) {
7795 +                       printk(KERN_INFO "Selected PERIPHERAL mode: gadget driver present.\n");
7796 +                       tahvo_usb_become_peripheral(tu);
7797 +               } else {
7798 +                       printk(KERN_INFO "Selected PERIPHERAL mode: no gadget driver, powering off.\n");
7799 +                       tahvo_usb_power_off(tu);
7800 +               }
7801 +       } else
7802 +               r = -EINVAL;
7803 +
7804 +       mutex_unlock(&tu->serialize);
7805 +       return r;
7806 +}
7807 +
7808 +static DEVICE_ATTR(otg_mode, 0644, otg_mode_show, otg_mode_store);
7809 +#endif
7810 +
7811 +static int tahvo_usb_probe(struct device *dev)
7812 +{
7813 +       struct tahvo_usb *tu;
7814 +       int ret;
7815 +
7816 +       dev_dbg(dev, "probe\n");
7817 +
7818 +       /* Create driver data */
7819 +       tu = kmalloc(sizeof(*tu), GFP_KERNEL);
7820 +       if (!tu)
7821 +               return -ENOMEM;
7822 +       memset(tu, 0, sizeof(*tu));
7823 +       tu->pt_dev = container_of(dev, struct platform_device, dev);
7824 +#ifdef CONFIG_USB_OTG
7825 +       /* Default mode */
7826 +#ifdef CONFIG_CBUS_TAHVO_USB_HOST_BY_DEFAULT
7827 +       tu->tahvo_mode = TAHVO_MODE_HOST;
7828 +#else
7829 +       tu->tahvo_mode = TAHVO_MODE_PERIPHERAL;
7830 +#endif
7831 +#endif
7832 +
7833 +       INIT_WORK(&tu->irq_work, tahvo_usb_irq_work);
7834 +       mutex_init(&tu->serialize);
7835 +
7836 +       /* Set initial state, so that we generate kevents only on
7837 +        * state changes */
7838 +       tu->vbus_state = tahvo_read_reg(TAHVO_REG_IDSR) & 0x01;
7839 +
7840 +       /* We cannot enable interrupt until omap_udc is initialized */
7841 +       ret = tahvo_request_irq(TAHVO_INT_VBUSON, tahvo_usb_vbus_interrupt,
7842 +                               (unsigned long) tu, "vbus_interrupt");
7843 +       if (ret != 0) {
7844 +               kfree(tu);
7845 +               printk(KERN_ERR "Could not register Tahvo interrupt for VBUS\n");
7846 +               return ret;
7847 +       }
7848 +
7849 +       /* Attributes */
7850 +       ret = device_create_file(dev, &dev_attr_vbus_state);
7851 +#ifdef CONFIG_USB_OTG
7852 +       ret |= device_create_file(dev, &dev_attr_otg_mode);
7853 +#endif
7854 +       if (ret)
7855 +               printk(KERN_ERR "attribute creation failed: %d\n", ret);
7856 +
7857 +       /* Create OTG interface */
7858 +       tahvo_usb_power_off(tu);
7859 +       tu->otg.state = OTG_STATE_UNDEFINED;
7860 +       tu->otg.label = DRIVER_NAME;
7861 +       tu->otg.set_host = tahvo_usb_set_host;
7862 +       tu->otg.set_peripheral = tahvo_usb_set_peripheral;
7863 +       tu->otg.set_power = tahvo_usb_set_power;
7864 +       tu->otg.set_suspend = tahvo_usb_set_suspend;
7865 +       tu->otg.start_srp = tahvo_usb_start_srp;
7866 +       tu->otg.start_hnp = tahvo_usb_start_hnp;
7867 +
7868 +       ret = otg_set_transceiver(&tu->otg);
7869 +       if (ret < 0) {
7870 +               printk(KERN_ERR "Cannot register USB transceiver\n");
7871 +               kfree(tu);
7872 +               tahvo_free_irq(TAHVO_INT_VBUSON);
7873 +               return ret;
7874 +       }
7875 +
7876 +       dev->driver_data = tu;
7877 +
7878 +       /* Act upon current vbus state once at startup. A vbus state irq may or
7879 +        * may not be generated in addition to this. */
7880 +       schedule_work(&tu->irq_work);
7881 +       return 0;
7882 +}
7883 +
7884 +static int tahvo_usb_remove(struct device *dev)
7885 +{
7886 +       dev_dbg(dev, "remove\n");
7887 +
7888 +       tahvo_free_irq(TAHVO_INT_VBUSON);
7889 +       flush_scheduled_work();
7890 +       otg_set_transceiver(0);
7891 +       device_remove_file(dev, &dev_attr_vbus_state);
7892 +#ifdef CONFIG_USB_OTG
7893 +       device_remove_file(dev, &dev_attr_otg_mode);
7894 +#endif
7895 +       return 0;
7896 +}
7897 +
7898 +static struct device_driver tahvo_usb_driver = {
7899 +       .name           = "tahvo-usb",
7900 +       .bus            = &platform_bus_type,
7901 +       .probe          = tahvo_usb_probe,
7902 +       .remove         = tahvo_usb_remove,
7903 +};
7904 +
7905 +static struct platform_device tahvo_usb_device = {
7906 +       .name           = "tahvo-usb",
7907 +       .id             = -1,
7908 +};
7909 +
7910 +static int __init tahvo_usb_init(void)
7911 +{
7912 +       int ret = 0;
7913 +
7914 +       printk(KERN_INFO "Tahvo USB transceiver driver initializing\n");
7915 +       ret = driver_register(&tahvo_usb_driver);
7916 +       if (ret)
7917 +               return ret;
7918 +       ret = platform_device_register(&tahvo_usb_device);
7919 +       if (ret < 0) {
7920 +               driver_unregister(&tahvo_usb_driver);
7921 +               return ret;
7922 +       }
7923 +       ret = driver_register(&omap_otg_driver);
7924 +       if (ret) {
7925 +               platform_device_unregister(&tahvo_usb_device);
7926 +               driver_unregister(&tahvo_usb_driver);
7927 +               return ret;
7928 +       }
7929 +       return 0;
7930 +}
7931 +
7932 +subsys_initcall(tahvo_usb_init);
7933 +
7934 +static void __exit tahvo_usb_exit(void)
7935 +{
7936 +       driver_unregister(&omap_otg_driver);
7937 +       platform_device_unregister(&tahvo_usb_device);
7938 +       driver_unregister(&tahvo_usb_driver);
7939 +}
7940 +module_exit(tahvo_usb_exit);
7941 +
7942 +MODULE_DESCRIPTION("Tahvo USB OTG Transceiver Driver");
7943 +MODULE_LICENSE("GPL");
7944 +MODULE_AUTHOR("Juha Yrjölä, Tony Lindgren, and Timo Teräs");
7945 diff --git a/drivers/cbus/tahvo-user.c b/drivers/cbus/tahvo-user.c
7946 new file mode 100644
7947 index 0000000..873d648
7948 --- /dev/null
7949 +++ b/drivers/cbus/tahvo-user.c
7950 @@ -0,0 +1,405 @@
7951 +/**
7952 + * drivers/cbus/tahvo-user.c
7953 + *
7954 + * Tahvo user space interface functions
7955 + *
7956 + * Copyright (C) 2004, 2005 Nokia Corporation
7957 + *
7958 + * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
7959 + *
7960 + * This file is subject to the terms and conditions of the GNU General
7961 + * Public License. See the file "COPYING" in the main directory of this
7962 + * archive for more details.
7963 + *
7964 + * This program is distributed in the hope that it will be useful,
7965 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7966 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7967 + * GNU General Public License for more details.
7968 + *
7969 + * You should have received a copy of the GNU General Public License
7970 + * along with this program; if not, write to the Free Software
7971 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7972 + */
7973 +
7974 +#include <linux/types.h>
7975 +#include <linux/kernel.h>
7976 +#include <linux/interrupt.h>
7977 +#include <linux/module.h>
7978 +#include <linux/init.h>
7979 +#include <linux/fs.h>
7980 +#include <linux/miscdevice.h>
7981 +#include <linux/poll.h>
7982 +#include <linux/list.h>
7983 +#include <linux/spinlock.h>
7984 +#include <linux/mutex.h>
7985 +
7986 +#include <asm/uaccess.h>
7987 +
7988 +#include "tahvo.h"
7989 +
7990 +#include "user_retu_tahvo.h"
7991 +
7992 +/* Maximum size of IRQ node buffer/pool */
7993 +#define TAHVO_MAX_IRQ_BUF_LEN  16
7994 +
7995 +#define PFX                    "tahvo-user: "
7996 +
7997 +/* Bitmap for marking the interrupt sources as having the handlers */
7998 +static u32 tahvo_irq_bits;
7999 +
8000 +/* For allowing only one user process to subscribe to the tahvo interrupts */
8001 +static struct file *tahvo_irq_subscr = NULL;
8002 +
8003 +/* For poll and IRQ passing */
8004 +struct tahvo_irq {
8005 +       u32 id;
8006 +       struct list_head node;
8007 +};
8008 +
8009 +static spinlock_t tahvo_irqs_lock;
8010 +static struct tahvo_irq *tahvo_irq_block;
8011 +static LIST_HEAD(tahvo_irqs);
8012 +static LIST_HEAD(tahvo_irqs_reserve);
8013 +
8014 +/* Wait queue - used when user wants to read the device */
8015 +DECLARE_WAIT_QUEUE_HEAD(tahvo_user_waitqueue);
8016 +
8017 +/* Semaphore to protect irq subscription sequence */
8018 +static struct mutex tahvo_mutex;
8019 +
8020 +/* This array specifies TAHVO register types (read/write/toggle) */
8021 +static const u8 tahvo_access_bits[] = {
8022 +       1,
8023 +       4,
8024 +       1,
8025 +       3,
8026 +       3,
8027 +       3,
8028 +       3,
8029 +       3,
8030 +       3,
8031 +       3,
8032 +       3,
8033 +       3,
8034 +       3,
8035 +       1
8036 +};
8037 +
8038 +/*
8039 + * The handler for all TAHVO interrupts.
8040 + *
8041 + * arg is the interrupt source in TAHVO.
8042 + */
8043 +static void tahvo_user_irq_handler(unsigned long arg)
8044 +{
8045 +       struct tahvo_irq *irq;
8046 +
8047 +       /* user has to re-enable the interrupt once ready
8048 +        * for receiving them again */
8049 +       tahvo_disable_irq(arg);
8050 +       tahvo_ack_irq(arg);
8051 +
8052 +       spin_lock(&tahvo_irqs_lock);
8053 +       if (list_empty(&tahvo_irqs_reserve)) {
8054 +               spin_unlock(&tahvo_irqs_lock);
8055 +               return;
8056 +       }
8057 +       irq = list_entry((&tahvo_irqs_reserve)->next, struct tahvo_irq, node);
8058 +       irq->id = arg;
8059 +       list_move_tail(&irq->node, &tahvo_irqs);
8060 +       spin_unlock(&tahvo_irqs_lock);
8061 +
8062 +       /* wake up waiting thread */
8063 +       wake_up(&tahvo_user_waitqueue);
8064 +}
8065 +
8066 +/*
8067 + * This routine sets up the interrupt handler and marks an interrupt source
8068 + * in TAHVO as a candidate for signal delivery to the user process.
8069 + */
8070 +static int tahvo_user_subscribe_to_irq(int id, struct file *filp)
8071 +{
8072 +       int ret;
8073 +
8074 +       mutex_lock(&tahvo_mutex);
8075 +       if ((tahvo_irq_subscr != NULL) && (tahvo_irq_subscr != filp)) {
8076 +               mutex_unlock(&tahvo_mutex);
8077 +               return -EBUSY;
8078 +       }
8079 +       /* Store the file pointer of the first user process registering IRQs */
8080 +       tahvo_irq_subscr = filp;
8081 +       mutex_unlock(&tahvo_mutex);
8082 +
8083 +       if (tahvo_irq_bits & (1 << id))
8084 +               return 0;
8085 +
8086 +       ret = tahvo_request_irq(id, tahvo_user_irq_handler, id, "");
8087 +       if (ret < 0)
8088 +               return ret;
8089 +
8090 +       /* Mark that this interrupt has a handler */
8091 +       tahvo_irq_bits |= 1 << id;
8092 +
8093 +       return 0;
8094 +}
8095 +
8096 +/*
8097 + * Unregister all TAHVO interrupt handlers
8098 + */
8099 +static void tahvo_unreg_irq_handlers(void)
8100 +{
8101 +       int id;
8102 +
8103 +       if (!tahvo_irq_bits)
8104 +               return;
8105 +
8106 +       for (id = 0; id < MAX_TAHVO_IRQ_HANDLERS; id++)
8107 +               if (tahvo_irq_bits & (1 << id))
8108 +                       tahvo_free_irq(id);
8109 +
8110 +       tahvo_irq_bits = 0;
8111 +}
8112 +
8113 +/*
8114 + * Write to TAHVO register.
8115 + * Returns 0 upon success, a negative error value otherwise.
8116 + */
8117 +static int tahvo_user_write_with_mask(u32 field, u16 value)
8118 +{
8119 +       u32 mask;
8120 +       u32 reg;
8121 +       u_short tmp;
8122 +       unsigned long flags;
8123 +
8124 +       mask = MASK(field);
8125 +       reg = REG(field);
8126 +
8127 +       /* Detect bad mask and reg */
8128 +       if (mask == 0 || reg > TAHVO_REG_MAX ||
8129 +           tahvo_access_bits[reg] == READ_ONLY) {
8130 +               printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
8131 +                      reg, mask);
8132 +               return -EINVAL;
8133 +       }
8134 +
8135 +       /* Justify value according to mask */
8136 +       while (!(mask & 1)) {
8137 +               value = value << 1;
8138 +               mask = mask >> 1;
8139 +       }
8140 +
8141 +       spin_lock_irqsave(&tahvo_lock, flags);
8142 +       if (tahvo_access_bits[reg] == TOGGLE) {
8143 +               /* No need to detect previous content of register */
8144 +               tmp = 0;
8145 +       } else {
8146 +               /* Read current value of register */
8147 +               tmp = tahvo_read_reg(reg);
8148 +       }
8149 +       /* Generate a new value */
8150 +       tmp = (tmp & ~MASK(field)) | (value & MASK(field));
8151 +       /* Write data to TAHVO */
8152 +       tahvo_write_reg(reg, tmp);
8153 +       spin_unlock_irqrestore(&tahvo_lock, flags);
8154 +
8155 +       return 0;
8156 +}
8157 +
8158 +/*
8159 + * Read TAHVO register.
8160 + */
8161 +static u32 tahvo_user_read_with_mask(u32 field)
8162 +{
8163 +       u_short value;
8164 +       u32 mask, reg;
8165 +
8166 +       mask = MASK(field);
8167 +       reg = REG(field);
8168 +
8169 +       /* Detect bad mask and reg */
8170 +       if (mask == 0 || reg > TAHVO_REG_MAX) {
8171 +               printk(KERN_ERR PFX "invalid arguments (reg=%#x, mask=%#x)\n",
8172 +                      reg, mask);
8173 +               return -EINVAL;
8174 +       }
8175 +
8176 +       /* Read the register */
8177 +       value = tahvo_read_reg(reg) & mask;
8178 +
8179 +       /* Right justify value */
8180 +       while (!(mask & 1)) {
8181 +               value = value >> 1;
8182 +               mask = mask >> 1;
8183 +       }
8184 +
8185 +       return value;
8186 +}
8187 +
8188 +/*
8189 + * Close device
8190 + */
8191 +static int tahvo_close(struct inode *inode, struct file *filp)
8192 +{
8193 +       /* Unregister all interrupts that have been registered */
8194 +       if (tahvo_irq_subscr == filp) {
8195 +               tahvo_unreg_irq_handlers();
8196 +               tahvo_irq_subscr = NULL;
8197 +       }
8198 +
8199 +       return 0;
8200 +}
8201 +
8202 +/*
8203 + * Device control (ioctl)
8204 + */
8205 +static int tahvo_ioctl(struct inode *inode, struct file *filp,
8206 +                      unsigned int cmd, unsigned long arg)
8207 +{
8208 +       struct retu_tahvo_write_parms par;
8209 +       int ret;
8210 +
8211 +       switch (cmd) {
8212 +       case URT_IOCT_IRQ_SUBSCR:
8213 +               return tahvo_user_subscribe_to_irq(arg, filp);
8214 +       case TAHVO_IOCH_READ:
8215 +               return tahvo_user_read_with_mask(arg);
8216 +       case TAHVO_IOCX_WRITE:
8217 +               ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
8218 +               if (ret)
8219 +                       printk(KERN_ERR "copy_from_user failed: %d\n", ret);
8220 +               par.result = tahvo_user_write_with_mask(par.field, par.value);
8221 +               ret = copy_to_user((void __user *) arg, &par, sizeof(par));
8222 +               if (ret)
8223 +                       printk(KERN_ERR "copy_to_user failed: %d\n", ret);
8224 +               break;
8225 +       default:
8226 +               return -ENOIOCTLCMD;
8227 +       }
8228 +       return 0;
8229 +}
8230 +
8231 +/*
8232 + * Read from device
8233 + */
8234 +static ssize_t tahvo_read(struct file *filp, char *buf, size_t count,
8235 +                         loff_t * offp)
8236 +{
8237 +       struct tahvo_irq *irq;
8238 +
8239 +       u32 nr, i;
8240 +
8241 +       /* read not permitted if neither filp nor anyone has registered IRQs */
8242 +       if (tahvo_irq_subscr != filp)
8243 +               return -EPERM;
8244 +
8245 +       if ((count < sizeof(u32)) || ((count % sizeof(u32)) != 0))
8246 +               return -EINVAL;
8247 +
8248 +       nr = count / sizeof(u32);
8249 +
8250 +       for (i = 0; i < nr; i++) {
8251 +               unsigned long flags;
8252 +               u32 irq_id;
8253 +               int ret;
8254 +
8255 +               ret = wait_event_interruptible(tahvo_user_waitqueue,
8256 +                                              !list_empty(&tahvo_irqs));
8257 +               if (ret < 0)
8258 +                       return ret;
8259 +
8260 +               spin_lock_irqsave(&tahvo_irqs_lock, flags);
8261 +               irq = list_entry((&tahvo_irqs)->next, struct tahvo_irq, node);
8262 +               irq_id = irq->id;
8263 +               list_move(&irq->node, &tahvo_irqs_reserve);
8264 +               spin_unlock_irqrestore(&tahvo_irqs_lock, flags);
8265 +
8266 +               ret = copy_to_user(buf + i * sizeof(irq_id), &irq_id,
8267 +                                  sizeof(irq_id));
8268 +               if (ret)
8269 +                       printk(KERN_ERR "copy_to_user failed: %d\n", ret);
8270 +       }
8271 +
8272 +       return count;
8273 +}
8274 +
8275 +/*
8276 + * Poll method
8277 + */
8278 +static unsigned tahvo_poll(struct file *filp, struct poll_table_struct *pt)
8279 +{
8280 +       if (!list_empty(&tahvo_irqs))
8281 +               return POLLIN;
8282 +
8283 +       poll_wait(filp, &tahvo_user_waitqueue, pt);
8284 +
8285 +       if (!list_empty(&tahvo_irqs))
8286 +               return POLLIN;
8287 +       else
8288 +               return 0;
8289 +}
8290 +
8291 +static struct file_operations tahvo_user_fileops = {
8292 +       .owner = THIS_MODULE,
8293 +       .ioctl = tahvo_ioctl,
8294 +       .read = tahvo_read,
8295 +       .release = tahvo_close,
8296 +       .poll = tahvo_poll
8297 +};
8298 +
8299 +static struct miscdevice tahvo_device = {
8300 +       .minor = MISC_DYNAMIC_MINOR,
8301 +       .name = "tahvo",
8302 +       .fops = &tahvo_user_fileops
8303 +};
8304 +
8305 +/*
8306 + * Initialization
8307 + *
8308 + * @return 0 if successful, error value otherwise.
8309 + */
8310 +int tahvo_user_init(void)
8311 +{
8312 +       struct tahvo_irq *irq;
8313 +       int res, i;
8314 +
8315 +       irq = kmalloc(sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN, GFP_KERNEL);
8316 +       if (irq == NULL) {
8317 +               printk(KERN_ERR PFX "kmalloc failed\n");
8318 +               return -ENOMEM;
8319 +       }
8320 +       memset(irq, 0, sizeof(*irq) * TAHVO_MAX_IRQ_BUF_LEN);
8321 +       for (i = 0; i < TAHVO_MAX_IRQ_BUF_LEN; i++)
8322 +               list_add(&irq[i].node, &tahvo_irqs_reserve);
8323 +
8324 +       tahvo_irq_block = irq;
8325 +
8326 +       spin_lock_init(&tahvo_irqs_lock);
8327 +       mutex_init(&tahvo_mutex);
8328 +
8329 +       /* Request a misc device */
8330 +       res = misc_register(&tahvo_device);
8331 +       if (res < 0) {
8332 +               printk(KERN_ERR PFX "unable to register misc device for %s\n",
8333 +                      tahvo_device.name);
8334 +               kfree(irq);
8335 +               return res;
8336 +       }
8337 +
8338 +       return 0;
8339 +}
8340 +
8341 +/*
8342 + * Cleanup.
8343 + */
8344 +void tahvo_user_cleanup(void)
8345 +{
8346 +       /* Unregister our misc device */
8347 +       misc_deregister(&tahvo_device);
8348 +       /* Unregister and disable all TAHVO interrupts */
8349 +       tahvo_unreg_irq_handlers();
8350 +       kfree(tahvo_irq_block);
8351 +}
8352 +
8353 +MODULE_DESCRIPTION("Tahvo ASIC user space functions");
8354 +MODULE_LICENSE("GPL");
8355 +MODULE_AUTHOR("Mikko Ylinen");
8356 diff --git a/drivers/cbus/tahvo.c b/drivers/cbus/tahvo.c
8357 new file mode 100644
8358 index 0000000..e734c4c
8359 --- /dev/null
8360 +++ b/drivers/cbus/tahvo.c
8361 @@ -0,0 +1,442 @@
8362 +/**
8363 + * drivers/cbus/tahvo.c
8364 + *
8365 + * Support functions for Tahvo ASIC
8366 + *
8367 + * Copyright (C) 2004, 2005 Nokia Corporation
8368 + *
8369 + * Written by Juha Yrjölä <juha.yrjola@nokia.com>,
8370 + *           David Weinehall <david.weinehall@nokia.com>, and
8371 + *           Mikko Ylinen <mikko.k.ylinen@nokia.com>
8372 + *
8373 + * This file is subject to the terms and conditions of the GNU General
8374 + * Public License. See the file "COPYING" in the main directory of this
8375 + * archive for more details.
8376 + *
8377 + * This program is distributed in the hope that it will be useful,
8378 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8379 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8380 + * GNU General Public License for more details.
8381 + *
8382 + * You should have received a copy of the GNU General Public License
8383 + * along with this program; if not, write to the Free Software
8384 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8385 + */
8386 +
8387 +#include <linux/module.h>
8388 +#include <linux/init.h>
8389 +
8390 +#include <linux/kernel.h>
8391 +#include <linux/errno.h>
8392 +#include <linux/device.h>
8393 +#include <linux/miscdevice.h>
8394 +#include <linux/poll.h>
8395 +#include <linux/fs.h>
8396 +#include <linux/irq.h>
8397 +#include <linux/interrupt.h>
8398 +#include <linux/platform_device.h>
8399 +#include <linux/gpio.h>
8400 +
8401 +#include <asm/uaccess.h>
8402 +
8403 +#include <mach/mux.h>
8404 +#include <mach/board.h>
8405 +#include <mach/board-nokia.h>
8406 +
8407 +#include "cbus.h"
8408 +#include "tahvo.h"
8409 +
8410 +#define TAHVO_ID               0x02
8411 +#define PFX                    "tahvo: "
8412 +
8413 +static int tahvo_initialized;
8414 +static int tahvo_irq_pin;
8415 +static int tahvo_is_betty;
8416 +
8417 +static struct tasklet_struct tahvo_tasklet;
8418 +spinlock_t tahvo_lock = SPIN_LOCK_UNLOCKED;
8419 +
8420 +static struct completion device_release;
8421 +
8422 +struct tahvo_irq_handler_desc {
8423 +       int (*func)(unsigned long);
8424 +       unsigned long arg;
8425 +       char name[8];
8426 +};
8427 +
8428 +static struct tahvo_irq_handler_desc tahvo_irq_handlers[MAX_TAHVO_IRQ_HANDLERS];
8429 +
8430 +/**
8431 + * tahvo_read_reg - Read a value from a register in Tahvo
8432 + * @reg: the register to read from
8433 + *
8434 + * This function returns the contents of the specified register
8435 + */
8436 +int tahvo_read_reg(int reg)
8437 +{
8438 +       BUG_ON(!tahvo_initialized);
8439 +       return cbus_read_reg(cbus_host, TAHVO_ID, reg);
8440 +}
8441 +
8442 +/**
8443 + * tahvo_write_reg - Write a value to a register in Tahvo
8444 + * @reg: the register to write to
8445 + * @reg: the value to write to the register
8446 + *
8447 + * This function writes a value to the specified register
8448 + */
8449 +void tahvo_write_reg(int reg, u16 val)
8450 +{
8451 +       BUG_ON(!tahvo_initialized);
8452 +       cbus_write_reg(cbus_host, TAHVO_ID, reg, val);
8453 +}
8454 +
8455 +/**
8456 + * tahvo_set_clear_reg_bits - set and clear register bits atomically
8457 + * @reg: the register to write to
8458 + * @bits: the bits to set
8459 + *
8460 + * This function sets and clears the specified Tahvo register bits atomically
8461 + */
8462 +void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear)
8463 +{
8464 +       unsigned long flags;
8465 +       u16 w;
8466 +
8467 +       spin_lock_irqsave(&tahvo_lock, flags);
8468 +       w = tahvo_read_reg(reg);
8469 +       w &= ~clear;
8470 +       w |= set;
8471 +       tahvo_write_reg(reg, w);
8472 +       spin_unlock_irqrestore(&tahvo_lock, flags);
8473 +}
8474 +
8475 +/*
8476 + * Disable given TAHVO interrupt
8477 + */
8478 +void tahvo_disable_irq(int id)
8479 +{
8480 +       unsigned long flags;
8481 +       u16 mask;
8482 +
8483 +       spin_lock_irqsave(&tahvo_lock, flags);
8484 +       mask = tahvo_read_reg(TAHVO_REG_IMR);
8485 +       mask |= 1 << id;
8486 +       tahvo_write_reg(TAHVO_REG_IMR, mask);
8487 +       spin_unlock_irqrestore(&tahvo_lock, flags);
8488 +}
8489 +
8490 +/*
8491 + * Enable given TAHVO interrupt
8492 + */
8493 +void tahvo_enable_irq(int id)
8494 +{
8495 +       unsigned long flags;
8496 +       u16 mask;
8497 +
8498 +       spin_lock_irqsave(&tahvo_lock, flags);
8499 +       mask = tahvo_read_reg(TAHVO_REG_IMR);
8500 +       mask &= ~(1 << id);
8501 +       tahvo_write_reg(TAHVO_REG_IMR, mask);
8502 +       spin_unlock_irqrestore(&tahvo_lock, flags);
8503 +}
8504 +
8505 +/*
8506 + * Acknowledge given TAHVO interrupt
8507 + */
8508 +void tahvo_ack_irq(int id)
8509 +{
8510 +       tahvo_write_reg(TAHVO_REG_IDR, 1 << id);
8511 +}
8512 +
8513 +static int tahvo_7bit_backlight;
8514 +
8515 +int tahvo_get_backlight_level(void)
8516 +{
8517 +       int mask;
8518 +
8519 +       if (tahvo_7bit_backlight)
8520 +               mask = 0x7f;
8521 +       else
8522 +               mask = 0x0f;
8523 +       return tahvo_read_reg(TAHVO_REG_LEDPWMR) & mask;
8524 +}
8525 +
8526 +int tahvo_get_max_backlight_level(void)
8527 +{
8528 +       if (tahvo_7bit_backlight)
8529 +               return 0x7f;
8530 +       else
8531 +               return 0x0f;
8532 +}
8533 +
8534 +void tahvo_set_backlight_level(int level)
8535 +{
8536 +       int max_level;
8537 +
8538 +       max_level = tahvo_get_max_backlight_level();
8539 +       if (level > max_level)
8540 +               level = max_level;
8541 +       tahvo_write_reg(TAHVO_REG_LEDPWMR, level);
8542 +}
8543 +
8544 +/*
8545 + * TAHVO interrupt handler. Only schedules the tasklet.
8546 + */
8547 +static irqreturn_t tahvo_irq_handler(int irq, void *dev_id)
8548 +{
8549 +       tasklet_schedule(&tahvo_tasklet);
8550 +       return IRQ_HANDLED;
8551 +}
8552 +
8553 +/*
8554 + * Tasklet handler
8555 + */
8556 +static void tahvo_tasklet_handler(unsigned long data)
8557 +{
8558 +       struct tahvo_irq_handler_desc *hnd;
8559 +       u16 id;
8560 +       u16 im;
8561 +       int i;
8562 +
8563 +       for (;;) {
8564 +               id = tahvo_read_reg(TAHVO_REG_IDR);
8565 +               im = ~tahvo_read_reg(TAHVO_REG_IMR);
8566 +               id &= im;
8567 +
8568 +               if (!id)
8569 +                       break;
8570 +
8571 +               for (i = 0; id != 0; i++, id >>= 1) {
8572 +                       if (!(id & 1))
8573 +                               continue;
8574 +                       hnd = &tahvo_irq_handlers[i];
8575 +                       if (hnd->func == NULL) {
8576 +                               /* Spurious tahvo interrupt - just ack it */
8577 +                               printk(KERN_INFO "Spurious Tahvo interrupt "
8578 +                                                "(id %d)\n", i);
8579 +                               tahvo_disable_irq(i);
8580 +                               tahvo_ack_irq(i);
8581 +                               continue;
8582 +                       }
8583 +                       hnd->func(hnd->arg);
8584 +                       /*
8585 +                        * Don't acknowledge the interrupt here
8586 +                        * It must be done explicitly
8587 +                        */
8588 +               }
8589 +       }
8590 +}
8591 +
8592 +/*
8593 + * Register the handler for a given TAHVO interrupt source.
8594 + */
8595 +int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name)
8596 +{
8597 +       struct tahvo_irq_handler_desc *hnd;
8598 +
8599 +       if (irq_handler == NULL || id >= MAX_TAHVO_IRQ_HANDLERS ||
8600 +           name == NULL) {
8601 +               printk(KERN_ERR PFX "Invalid arguments to %s\n",
8602 +                      __FUNCTION__);
8603 +               return -EINVAL;
8604 +       }
8605 +       hnd = &tahvo_irq_handlers[id];
8606 +       if (hnd->func != NULL) {
8607 +               printk(KERN_ERR PFX "IRQ %d already reserved\n", id);
8608 +               return -EBUSY;
8609 +       }
8610 +       printk(KERN_INFO PFX "Registering interrupt %d for device %s\n",
8611 +              id, name);
8612 +       hnd->func = irq_handler;
8613 +       hnd->arg = arg;
8614 +       strlcpy(hnd->name, name, sizeof(hnd->name));
8615 +
8616 +       tahvo_ack_irq(id);
8617 +       tahvo_enable_irq(id);
8618 +
8619 +       return 0;
8620 +}
8621 +
8622 +/*
8623 + * Unregister the handler for a given TAHVO interrupt source.
8624 + */
8625 +void tahvo_free_irq(int id)
8626 +{
8627 +       struct tahvo_irq_handler_desc *hnd;
8628 +
8629 +       if (id >= MAX_TAHVO_IRQ_HANDLERS) {
8630 +               printk(KERN_ERR PFX "Invalid argument to %s\n",
8631 +                      __FUNCTION__);
8632 +               return;
8633 +       }
8634 +       hnd = &tahvo_irq_handlers[id];
8635 +       if (hnd->func == NULL) {
8636 +               printk(KERN_ERR PFX "IRQ %d already freed\n", id);
8637 +               return;
8638 +       }
8639 +
8640 +       tahvo_disable_irq(id);
8641 +       hnd->func = NULL;
8642 +}
8643 +
8644 +/**
8645 + * tahvo_probe - Probe for Tahvo ASIC
8646 + * @dev: the Tahvo device
8647 + *
8648 + * Probe for the Tahvo ASIC and allocate memory
8649 + * for its device-struct if found
8650 + */
8651 +static int __devinit tahvo_probe(struct device *dev)
8652 +{
8653 +       const struct omap_em_asic_bb5_config * em_asic_config;
8654 +       int rev, id, ret;
8655 +
8656 +       /* Prepare tasklet */
8657 +       tasklet_init(&tahvo_tasklet, tahvo_tasklet_handler, 0);
8658 +
8659 +       em_asic_config = omap_get_config(OMAP_TAG_EM_ASIC_BB5,
8660 +                                        struct omap_em_asic_bb5_config);
8661 +       if (em_asic_config == NULL) {
8662 +               printk(KERN_ERR PFX "Unable to retrieve config data\n");
8663 +               return -ENODATA;
8664 +       }
8665 +
8666 +       tahvo_initialized = 1;
8667 +
8668 +       rev = tahvo_read_reg(TAHVO_REG_ASICR);
8669 +
8670 +       id = (rev >> 8) & 0xff;
8671 +       if (id == 0x03) {
8672 +               if ((rev & 0xff) >= 0x50)
8673 +                       tahvo_7bit_backlight = 1;
8674 +       } else if (id == 0x0b) {
8675 +               tahvo_is_betty = 1;
8676 +               tahvo_7bit_backlight = 1;
8677 +       } else {
8678 +               printk(KERN_ERR "Tahvo/Betty chip not found");
8679 +               return -ENODEV;
8680 +       }
8681 +
8682 +       printk(KERN_INFO "%s v%d.%d found\n", tahvo_is_betty ? "Betty" : "Tahvo",
8683 +              (rev >> 4) & 0x0f, rev & 0x0f);
8684 +
8685 +       tahvo_irq_pin = em_asic_config->tahvo_irq_gpio;
8686 +
8687 +       if ((ret = gpio_request(tahvo_irq_pin, "TAHVO irq")) < 0) {
8688 +               printk(KERN_ERR PFX "Unable to reserve IRQ GPIO\n");
8689 +               return ret;
8690 +       }
8691 +
8692 +       /* Set the pin as input */
8693 +       gpio_direction_input(tahvo_irq_pin);
8694 +
8695 +       /* Rising edge triggers the IRQ */
8696 +       set_irq_type(gpio_to_irq(tahvo_irq_pin), IRQ_TYPE_EDGE_RISING);
8697 +
8698 +       /* Mask all TAHVO interrupts */
8699 +       tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
8700 +
8701 +       ret = request_irq(gpio_to_irq(tahvo_irq_pin), tahvo_irq_handler, 0,
8702 +                         "tahvo", 0);
8703 +       if (ret < 0) {
8704 +               printk(KERN_ERR PFX "Unable to register IRQ handler\n");
8705 +               gpio_free(tahvo_irq_pin);
8706 +               return ret;
8707 +       }
8708 +#ifdef CONFIG_CBUS_TAHVO_USER
8709 +       /* Initialize user-space interface */
8710 +       if (tahvo_user_init() < 0) {
8711 +               printk(KERN_ERR "Unable to initialize driver\n");
8712 +               free_irq(gpio_to_irq(tahvo_irq_pin), 0);
8713 +               gpio_free(tahvo_irq_pin);
8714 +               return ret;
8715 +       }
8716 +#endif
8717 +       return 0;
8718 +}
8719 +
8720 +static int tahvo_remove(struct device *dev)
8721 +{
8722 +#ifdef CONFIG_CBUS_TAHVO_USER
8723 +       tahvo_user_cleanup();
8724 +#endif
8725 +       /* Mask all TAHVO interrupts */
8726 +       tahvo_write_reg(TAHVO_REG_IMR, 0xffff);
8727 +       free_irq(gpio_to_irq(tahvo_irq_pin), 0);
8728 +       gpio_free(tahvo_irq_pin);
8729 +       tasklet_kill(&tahvo_tasklet);
8730 +
8731 +       return 0;
8732 +}
8733 +
8734 +static void tahvo_device_release(struct device *dev)
8735 +{
8736 +       complete(&device_release);
8737 +}
8738 +
8739 +static struct device_driver tahvo_driver = {
8740 +       .name           = "tahvo",
8741 +       .bus            = &platform_bus_type,
8742 +       .probe          = tahvo_probe,
8743 +       .remove         = tahvo_remove,
8744 +};
8745 +
8746 +static struct platform_device tahvo_device = {
8747 +       .name           = "tahvo",
8748 +       .id             = -1,
8749 +       .dev = {
8750 +               .release = tahvo_device_release,
8751 +       }
8752 +};
8753 +
8754 +/**
8755 + * tahvo_init - initialise Tahvo driver
8756 + *
8757 + * Initialise the Tahvo driver and return 0 if everything worked ok
8758 + */
8759 +static int __init tahvo_init(void)
8760 +{
8761 +       int ret = 0;
8762 +
8763 +       printk(KERN_INFO "Tahvo/Betty driver initialising\n");
8764 +
8765 +       init_completion(&device_release);
8766 +
8767 +       if ((ret = driver_register(&tahvo_driver)) < 0)
8768 +               return ret;
8769 +
8770 +       if ((ret = platform_device_register(&tahvo_device)) < 0) {
8771 +               driver_unregister(&tahvo_driver);
8772 +               return ret;
8773 +       }
8774 +       return 0;
8775 +}
8776 +
8777 +/*
8778 + * Cleanup
8779 + */
8780 +static void __exit tahvo_exit(void)
8781 +{
8782 +       platform_device_unregister(&tahvo_device);
8783 +       driver_unregister(&tahvo_driver);
8784 +       wait_for_completion(&device_release);
8785 +}
8786 +
8787 +EXPORT_SYMBOL(tahvo_request_irq);
8788 +EXPORT_SYMBOL(tahvo_free_irq);
8789 +EXPORT_SYMBOL(tahvo_enable_irq);
8790 +EXPORT_SYMBOL(tahvo_disable_irq);
8791 +EXPORT_SYMBOL(tahvo_ack_irq);
8792 +EXPORT_SYMBOL(tahvo_read_reg);
8793 +EXPORT_SYMBOL(tahvo_write_reg);
8794 +EXPORT_SYMBOL(tahvo_get_backlight_level);
8795 +EXPORT_SYMBOL(tahvo_get_max_backlight_level);
8796 +EXPORT_SYMBOL(tahvo_set_backlight_level);
8797 +
8798 +subsys_initcall(tahvo_init);
8799 +module_exit(tahvo_exit);
8800 +
8801 +MODULE_DESCRIPTION("Tahvo ASIC control");
8802 +MODULE_LICENSE("GPL");
8803 +MODULE_AUTHOR("Juha Yrjölä, David Weinehall, and Mikko Ylinen");
8804 diff --git a/drivers/cbus/tahvo.h b/drivers/cbus/tahvo.h
8805 new file mode 100644
8806 index 0000000..b7a8ee1
8807 --- /dev/null
8808 +++ b/drivers/cbus/tahvo.h
8809 @@ -0,0 +1,61 @@
8810 +/*
8811 + * drivers/cbus/tahvo.h
8812 + *
8813 + * Copyright (C) 2004, 2005 Nokia Corporation
8814 + *
8815 + * Written by Juha Yrjölä <juha.yrjola@nokia.com> and
8816 + *           David Weinehall <david.weinehall@nokia.com>
8817 + *
8818 + * This file is subject to the terms and conditions of the GNU General
8819 + * Public License. See the file "COPYING" in the main directory of this
8820 + * archive for more details.
8821 + *
8822 + * This program is distributed in the hope that it will be useful,
8823 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8824 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8825 + * GNU General Public License for more details.
8826 +
8827 + * You should have received a copy of the GNU General Public License
8828 + * along with this program; if not, write to the Free Software
8829 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8830 + */
8831 +
8832 +#ifndef __DRIVERS_CBUS_TAHVO_H
8833 +#define __DRIVERS_CBUS_TAHVO_H
8834 +
8835 +#include <linux/types.h>
8836 +
8837 +/* Registers */
8838 +#define TAHVO_REG_ASICR                0x00    /* ASIC ID & revision */
8839 +#define TAHVO_REG_IDR          0x01    /* Interrupt ID */
8840 +#define TAHVO_REG_IDSR         0x02    /* Interrupt status */
8841 +#define TAHVO_REG_IMR          0x03    /* Interrupt mask */
8842 +#define TAHVO_REG_LEDPWMR      0x05    /* LED PWM */
8843 +#define TAHVO_REG_USBR         0x06    /* USB control */
8844 +#define TAHVO_REG_MAX          0x0d
8845 +
8846 +/* Interrupt sources */
8847 +#define TAHVO_INT_VBUSON       0
8848 +
8849 +#define MAX_TAHVO_IRQ_HANDLERS 8
8850 +
8851 +int tahvo_read_reg(int reg);
8852 +void tahvo_write_reg(int reg, u16 val);
8853 +void tahvo_set_clear_reg_bits(int reg, u16 set, u16 clear);
8854 +int tahvo_request_irq(int id, void *irq_handler, unsigned long arg, char *name);
8855 +void tahvo_free_irq(int id);
8856 +void tahvo_enable_irq(int id);
8857 +void tahvo_disable_irq(int id);
8858 +void tahvo_ack_irq(int id);
8859 +int tahvo_get_backlight_level(void);
8860 +int tahvo_get_max_backlight_level(void);
8861 +void tahvo_set_backlight_level(int level);
8862 +
8863 +#ifdef CONFIG_CBUS_TAHVO_USER
8864 +int tahvo_user_init(void);
8865 +void tahvo_user_cleanup(void);
8866 +#endif
8867 +
8868 +extern spinlock_t tahvo_lock;
8869 +
8870 +#endif /* __DRIVERS_CBUS_TAHVO_H */
8871 diff --git a/drivers/cbus/user_retu_tahvo.h b/drivers/cbus/user_retu_tahvo.h
8872 new file mode 100644
8873 index 0000000..a5c2190
8874 --- /dev/null
8875 +++ b/drivers/cbus/user_retu_tahvo.h
8876 @@ -0,0 +1,75 @@
8877 +/**
8878 + * drivers/cbus/user_retu_tahvo.h
8879 + *
8880 + * Copyright (C) 2004, 2005 Nokia Corporation
8881 + *
8882 + * Written by Mikko Ylinen <mikko.k.ylinen@nokia.com>
8883 + *
8884 + * Definitions and types used by both retu-user and tahvo-user.
8885 + *
8886 + * This file is subject to the terms and conditions of the GNU General
8887 + * Public License. See the file "COPYING" in the main directory of this
8888 + * archive for more details.
8889 + *
8890 + * This program is distributed in the hope that it will be useful,
8891 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8892 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8893 + * GNU General Public License for more details.
8894 +
8895 + * You should have received a copy of the GNU General Public License
8896 + * along with this program; if not, write to the Free Software
8897 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8898 + */
8899 +
8900 +#ifndef _USER_RETU_TAHVO_H
8901 +#define _USER_RETU_TAHVO_H
8902 +
8903 +/* Chip IDs */
8904 +#define CHIP_RETU      1
8905 +#define CHIP_TAHVO     2
8906 +
8907 +/* Register access type bits */
8908 +#define READ_ONLY              1
8909 +#define WRITE_ONLY             2
8910 +#define READ_WRITE             3
8911 +#define TOGGLE                 4
8912 +
8913 +#define MASK(field)            ((u16)(field & 0xFFFF))
8914 +#define REG(field)             ((u16)((field >> 16) & 0x3F))
8915 +
8916 +/*** IOCTL definitions. These should be kept in sync with user space **********/
8917 +
8918 +#define URT_IOC_MAGIC '`'
8919 +
8920 +/*
8921 + * IOCTL function naming conventions:
8922 + * ==================================
8923 + *  0 -- No argument and return value
8924 + *  S -- Set through a pointer
8925 + *  T -- Tell directly with the argument value
8926 + *  G -- Reply by setting through a pointer
8927 + *  Q -- response is on the return value
8928 + *  X -- S and G atomically
8929 + *  H -- T and Q atomically
8930 + */
8931 +
8932 +/* General */
8933 +#define URT_IOCT_IRQ_SUBSCR            _IO(URT_IOC_MAGIC, 0)
8934 +
8935 +/* RETU */
8936 +#define RETU_IOCH_READ                 _IO(URT_IOC_MAGIC, 1)
8937 +#define RETU_IOCX_WRITE                        _IO(URT_IOC_MAGIC, 2)
8938 +#define RETU_IOCH_ADC_READ             _IO(URT_IOC_MAGIC, 3)
8939 +
8940 +/* TAHVO */
8941 +#define TAHVO_IOCH_READ                        _IO(URT_IOC_MAGIC, 4)
8942 +#define TAHVO_IOCX_WRITE               _IO(URT_IOC_MAGIC, 5)
8943 +
8944 +/* This structure is used for writing RETU/TAHVO registers */
8945 +struct retu_tahvo_write_parms {
8946 +    u32        field;
8947 +    u16        value;
8948 +    u8 result;
8949 +};
8950 +
8951 +#endif
8952 diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
8953 index 4487cc0..0aecaae 100644
8954 --- a/drivers/mmc/host/omap_hsmmc.c
8955 +++ b/drivers/mmc/host/omap_hsmmc.c
8956 @@ -2013,7 +2013,7 @@ static struct platform_driver omap_hsmmc_driver = {
8957  static int __init omap_hsmmc_init(void)
8958  {
8959         /* Register the MMC driver */
8960 -       return platform_driver_register(&omap_hsmmc_driver);
8961 +       return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
8962  }
8963
8964  static void __exit omap_hsmmc_cleanup(void)
8965 diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c
8966 index e75ba9b..7bcf409 100644
8967 --- a/drivers/spi/omap_uwire.c
8968 +++ b/drivers/spi/omap_uwire.c
8969 @@ -52,7 +52,7 @@
8970  #include <asm/mach-types.h>
8971
8972  #include <mach/mux.h>
8973 -#include <mach/omap730.h>      /* OMAP730_IO_CONF registers */
8974 +#include <mach/omap7xx.h>      /* OMAP7XX_IO_CONF registers */
8975
8976
8977  /* FIXME address is now a platform device resource,
8978 @@ -504,7 +504,7 @@ static int __init uwire_probe(struct platform_device *pdev)
8979         }
8980         clk_enable(uwire->ck);
8981
8982 -       if (cpu_is_omap730())
8983 +       if (cpu_is_omap7xx())
8984                 uwire_idx_shift = 1;
8985         else
8986                 uwire_idx_shift = 2;
8987 @@ -573,8 +573,8 @@ static int __init omap_uwire_init(void)
8988         }
8989         if (machine_is_omap_perseus2()) {
8990                 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
8991 -               int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
8992 -               omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
8993 +               int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
8994 +               omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
8995         }
8996
8997         return platform_driver_probe(&uwire_driver, uwire_probe);
8998 diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
8999 index 2407508..5620e92 100644
9000 --- a/drivers/usb/Kconfig
9001 +++ b/drivers/usb/Kconfig
9002 @@ -60,6 +60,7 @@ config USB_ARCH_HAS_EHCI
9003         default y if ARCH_IXP4XX
9004         default y if ARCH_W90X900
9005         default y if ARCH_AT91SAM9G45
9006 +       default y if ARCH_OMAP34XX
9007         default PCI
9008
9009  # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
9010 diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
9011 index 9835e07..44c208c 100644
9012 --- a/drivers/usb/host/ehci-hcd.c
9013 +++ b/drivers/usb/host/ehci-hcd.c
9014 @@ -1108,6 +1108,11 @@ MODULE_LICENSE ("GPL");
9015  #define        PLATFORM_DRIVER         ehci_hcd_au1xxx_driver
9016  #endif
9017
9018 +#ifdef CONFIG_ARCH_OMAP34XX
9019 +#include "ehci-omap.c"
9020 +#define        PLATFORM_DRIVER         ehci_hcd_omap_driver
9021 +#endif
9022 +
9023  #ifdef CONFIG_PPC_PS3
9024  #include "ehci-ps3.c"
9025  #define        PS3_SYSTEM_BUS_DRIVER   ps3_ehci_driver
9026 diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
9027 new file mode 100644
9028 index 0000000..7ba8df3
9029 --- /dev/null
9030 +++ b/drivers/usb/host/ehci-omap.c
9031 @@ -0,0 +1,755 @@
9032 +/*
9033 + * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
9034 + *
9035 + * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
9036 + * Tested on OMAP3430 ES2.0 SDP
9037 + *
9038 + * Copyright (C) 2007-2008 Texas Instruments, Inc.
9039 + *     Author: Vikram Pandita <vikram.pandita@ti.com>
9040 + *
9041 + * Copyright (C) 2009 Nokia Corporation
9042 + *     Contact: Felipe Balbi <felipe.balbi@nokia.com>
9043 + *
9044 + * Based on "ehci-fsl.c" and "ehci-au1xxx.c" ehci glue layers
9045 + *
9046 + * This program is free software; you can redistribute it and/or modify
9047 + * it under the terms of the GNU General Public License as published by
9048 + * the Free Software Foundation; either version 2 of the License, or
9049 + * (at your option) any later version.
9050 + *
9051 + * This program is distributed in the hope that it will be useful,
9052 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9053 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9054 + * GNU General Public License for more details.
9055 + *
9056 + * You should have received a copy of the GNU General Public License
9057 + * along with this program; if not, write to the Free Software
9058 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
9059 + *
9060 + * TODO (last updated Feb 23rd, 2009):
9061 + *     - add kernel-doc
9062 + *     - enable AUTOIDLE
9063 + *     - move DPLL5 programming to clock fw
9064 + *     - add suspend/resume
9065 + *     - move workarounds to board-files
9066 + */
9067 +
9068 +#include <linux/platform_device.h>
9069 +#include <linux/clk.h>
9070 +#include <linux/gpio.h>
9071 +#include <mach/usb.h>
9072 +
9073 +/*
9074 + * OMAP USBHOST Register addresses: VIRTUAL ADDRESSES
9075 + *     Use ehci_omap_readl()/ehci_omap_writel() functions
9076 + */
9077 +
9078 +/* TLL Register Set */
9079 +#define        OMAP_USBTLL_REVISION                            (0x00)
9080 +#define        OMAP_USBTLL_SYSCONFIG                           (0x10)
9081 +#define        OMAP_USBTLL_SYSCONFIG_CACTIVITY                 (1 << 8)
9082 +#define        OMAP_USBTLL_SYSCONFIG_SIDLEMODE                 (1 << 3)
9083 +#define        OMAP_USBTLL_SYSCONFIG_ENAWAKEUP                 (1 << 2)
9084 +#define        OMAP_USBTLL_SYSCONFIG_SOFTRESET                 (1 << 1)
9085 +#define        OMAP_USBTLL_SYSCONFIG_AUTOIDLE                  (1 << 0)
9086 +
9087 +#define        OMAP_USBTLL_SYSSTATUS                           (0x14)
9088 +#define        OMAP_USBTLL_SYSSTATUS_RESETDONE                 (1 << 0)
9089 +
9090 +#define        OMAP_USBTLL_IRQSTATUS                           (0x18)
9091 +#define        OMAP_USBTLL_IRQENABLE                           (0x1C)
9092 +
9093 +#define        OMAP_TLL_SHARED_CONF                            (0x30)
9094 +#define        OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN             (1 << 6)
9095 +#define        OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN            (1 << 5)
9096 +#define        OMAP_TLL_SHARED_CONF_USB_DIVRATION              (1 << 2)
9097 +#define        OMAP_TLL_SHARED_CONF_FCLK_REQ                   (1 << 1)
9098 +#define        OMAP_TLL_SHARED_CONF_FCLK_IS_ON                 (1 << 0)
9099 +
9100 +#define        OMAP_TLL_CHANNEL_CONF(num)                      (0x040 + 0x004 * num)
9101 +#define        OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF            (1 << 11)
9102 +#define        OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE         (1 << 10)
9103 +#define        OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE              (1 << 9)
9104 +#define        OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE               (1 << 8)
9105 +#define        OMAP_TLL_CHANNEL_CONF_CHANEN                    (1 << 0)
9106 +
9107 +#define        OMAP_TLL_ULPI_FUNCTION_CTRL(num)                (0x804 + 0x100 * num)
9108 +#define        OMAP_TLL_ULPI_INTERFACE_CTRL(num)               (0x807 + 0x100 * num)
9109 +#define        OMAP_TLL_ULPI_OTG_CTRL(num)                     (0x80A + 0x100 * num)
9110 +#define        OMAP_TLL_ULPI_INT_EN_RISE(num)                  (0x80D + 0x100 * num)
9111 +#define        OMAP_TLL_ULPI_INT_EN_FALL(num)                  (0x810 + 0x100 * num)
9112 +#define        OMAP_TLL_ULPI_INT_STATUS(num)                   (0x813 + 0x100 * num)
9113 +#define        OMAP_TLL_ULPI_INT_LATCH(num)                    (0x814 + 0x100 * num)
9114 +#define        OMAP_TLL_ULPI_DEBUG(num)                        (0x815 + 0x100 * num)
9115 +#define        OMAP_TLL_ULPI_SCRATCH_REGISTER(num)             (0x816 + 0x100 * num)
9116 +
9117 +#define OMAP_TLL_CHANNEL_COUNT                         3
9118 +#define OMAP_TLL_CHANNEL_1_EN_MASK                     (1 << 1)
9119 +#define OMAP_TLL_CHANNEL_2_EN_MASK                     (1 << 2)
9120 +#define OMAP_TLL_CHANNEL_3_EN_MASK                     (1 << 4)
9121 +
9122 +/* UHH Register Set */
9123 +#define        OMAP_UHH_REVISION                               (0x00)
9124 +#define        OMAP_UHH_SYSCONFIG                              (0x10)
9125 +#define        OMAP_UHH_SYSCONFIG_MIDLEMODE                    (1 << 12)
9126 +#define        OMAP_UHH_SYSCONFIG_CACTIVITY                    (1 << 8)
9127 +#define        OMAP_UHH_SYSCONFIG_SIDLEMODE                    (1 << 3)
9128 +#define        OMAP_UHH_SYSCONFIG_ENAWAKEUP                    (1 << 2)
9129 +#define        OMAP_UHH_SYSCONFIG_SOFTRESET                    (1 << 1)
9130 +#define        OMAP_UHH_SYSCONFIG_AUTOIDLE                     (1 << 0)
9131 +
9132 +#define        OMAP_UHH_SYSSTATUS                              (0x14)
9133 +#define        OMAP_UHH_HOSTCONFIG                             (0x40)
9134 +#define        OMAP_UHH_HOSTCONFIG_ULPI_BYPASS                 (1 << 0)
9135 +#define        OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS              (1 << 0)
9136 +#define        OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS              (1 << 11)
9137 +#define        OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS              (1 << 12)
9138 +#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN             (1 << 2)
9139 +#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN             (1 << 3)
9140 +#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN            (1 << 4)
9141 +#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN             (1 << 5)
9142 +#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS          (1 << 8)
9143 +#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS          (1 << 9)
9144 +#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS          (1 << 10)
9145 +
9146 +#define        OMAP_UHH_DEBUG_CSR                              (0x44)
9147 +
9148 +/* EHCI Register Set */
9149 +#define        EHCI_INSNREG05_ULPI                             (0xA4)
9150 +#define        EHCI_INSNREG05_ULPI_CONTROL_SHIFT               31
9151 +#define        EHCI_INSNREG05_ULPI_PORTSEL_SHIFT               24
9152 +#define        EHCI_INSNREG05_ULPI_OPSEL_SHIFT                 22
9153 +#define        EHCI_INSNREG05_ULPI_REGADD_SHIFT                16
9154 +#define        EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT             8
9155 +#define        EHCI_INSNREG05_ULPI_WRDATA_SHIFT                0
9156 +
9157 +/*-------------------------------------------------------------------------*/
9158 +
9159 +static inline void ehci_omap_writel(void __iomem *base, u32 reg, u32 val)
9160 +{
9161 +       __raw_writel(val, base + reg);
9162 +}
9163 +
9164 +static inline u32 ehci_omap_readl(void __iomem *base, u32 reg)
9165 +{
9166 +       return __raw_readl(base + reg);
9167 +}
9168 +
9169 +static inline void ehci_omap_writeb(void __iomem *base, u8 reg, u8 val)
9170 +{
9171 +       __raw_writeb(val, base + reg);
9172 +}
9173 +
9174 +static inline u8 ehci_omap_readb(void __iomem *base, u8 reg)
9175 +{
9176 +       return __raw_readb(base + reg);
9177 +}
9178 +
9179 +/*-------------------------------------------------------------------------*/
9180 +
9181 +struct ehci_hcd_omap {
9182 +       struct ehci_hcd         *ehci;
9183 +       struct device           *dev;
9184 +
9185 +       struct clk              *usbhost_ick;
9186 +       struct clk              *usbhost2_120m_fck;
9187 +       struct clk              *usbhost1_48m_fck;
9188 +       struct clk              *usbtll_fck;
9189 +       struct clk              *usbtll_ick;
9190 +
9191 +       /* FIXME the following two workarounds are
9192 +        * board specific not silicon-specific so these
9193 +        * should be moved to board-file instead.
9194 +        *
9195 +        * Maybe someone from TI will know better which
9196 +        * board is affected and needs the workarounds
9197 +        * to be applied
9198 +        */
9199 +
9200 +       /* gpio for resetting phy */
9201 +       int                     reset_gpio_port[OMAP3_HS_USB_PORTS];
9202 +
9203 +       /* phy reset workaround */
9204 +       int                     phy_reset;
9205 +
9206 +       /* desired phy_mode: TLL, PHY */
9207 +       enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
9208 +
9209 +       void __iomem            *uhh_base;
9210 +       void __iomem            *tll_base;
9211 +       void __iomem            *ehci_base;
9212 +};
9213 +
9214 +/*-------------------------------------------------------------------------*/
9215 +
9216 +static void omap_usb_utmi_init(struct ehci_hcd_omap *omap, u8 tll_channel_mask)
9217 +{
9218 +       unsigned reg;
9219 +       int i;
9220 +
9221 +       /* Program the 3 TLL channels upfront */
9222 +       for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
9223 +               reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
9224 +
9225 +               /* Disable AutoIdle, BitStuffing and use SDR Mode */
9226 +               reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
9227 +                               | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
9228 +                               | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
9229 +               ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
9230 +       }
9231 +
9232 +       /* Program Common TLL register */
9233 +       reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_SHARED_CONF);
9234 +       reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
9235 +                       | OMAP_TLL_SHARED_CONF_USB_DIVRATION
9236 +                       | OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN);
9237 +       reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
9238 +
9239 +       ehci_omap_writel(omap->tll_base, OMAP_TLL_SHARED_CONF, reg);
9240 +
9241 +       /* Enable channels now */
9242 +       for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
9243 +               reg = ehci_omap_readl(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i));
9244 +
9245 +               /* Enable only the reg that is needed */
9246 +               if (!(tll_channel_mask & 1<<i))
9247 +                       continue;
9248 +
9249 +               reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
9250 +               ehci_omap_writel(omap->tll_base, OMAP_TLL_CHANNEL_CONF(i), reg);
9251 +
9252 +               ehci_omap_writeb(omap->tll_base,
9253 +                               OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe);
9254 +               dev_dbg(omap->dev, "ULPI_SCRATCH_REG[ch=%d]= 0x%02x\n",
9255 +                               i+1, ehci_omap_readb(omap->tll_base,
9256 +                               OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
9257 +       }
9258 +}
9259 +
9260 +/*-------------------------------------------------------------------------*/
9261 +
9262 +/* omap_start_ehc
9263 + *     - Start the TI USBHOST controller
9264 + */
9265 +static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
9266 +{
9267 +       unsigned long timeout = jiffies + msecs_to_jiffies(1000);
9268 +       u8 tll_ch_mask = 0;
9269 +       unsigned reg = 0;
9270 +       int ret = 0;
9271 +
9272 +       dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
9273 +
9274 +       /* Enable Clocks for USBHOST */
9275 +       omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
9276 +       if (IS_ERR(omap->usbhost_ick)) {
9277 +               ret =  PTR_ERR(omap->usbhost_ick);
9278 +               goto err_host_ick;
9279 +       }
9280 +       clk_enable(omap->usbhost_ick);
9281 +
9282 +       omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
9283 +       if (IS_ERR(omap->usbhost2_120m_fck)) {
9284 +               ret = PTR_ERR(omap->usbhost2_120m_fck);
9285 +               goto err_host_120m_fck;
9286 +       }
9287 +       clk_enable(omap->usbhost2_120m_fck);
9288 +
9289 +       omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
9290 +       if (IS_ERR(omap->usbhost1_48m_fck)) {
9291 +               ret = PTR_ERR(omap->usbhost1_48m_fck);
9292 +               goto err_host_48m_fck;
9293 +       }
9294 +       clk_enable(omap->usbhost1_48m_fck);
9295 +
9296 +       if (omap->phy_reset) {
9297 +               /* Refer: ISSUE1 */
9298 +               if (gpio_is_valid(omap->reset_gpio_port[0])) {
9299 +                       gpio_request(omap->reset_gpio_port[0],
9300 +                                               "USB1 PHY reset");
9301 +                       gpio_direction_output(omap->reset_gpio_port[0], 0);
9302 +               }
9303 +
9304 +               if (gpio_is_valid(omap->reset_gpio_port[1])) {
9305 +                       gpio_request(omap->reset_gpio_port[1],
9306 +                                               "USB2 PHY reset");
9307 +                       gpio_direction_output(omap->reset_gpio_port[1], 0);
9308 +               }
9309 +
9310 +               /* Hold the PHY in RESET for enough time till DIR is high */
9311 +               udelay(10);
9312 +       }
9313 +
9314 +       /* Configure TLL for 60Mhz clk for ULPI */
9315 +       omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
9316 +       if (IS_ERR(omap->usbtll_fck)) {
9317 +               ret = PTR_ERR(omap->usbtll_fck);
9318 +               goto err_tll_fck;
9319 +       }
9320 +       clk_enable(omap->usbtll_fck);
9321 +
9322 +       omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
9323 +       if (IS_ERR(omap->usbtll_ick)) {
9324 +               ret = PTR_ERR(omap->usbtll_ick);
9325 +               goto err_tll_ick;
9326 +       }
9327 +       clk_enable(omap->usbtll_ick);
9328 +
9329 +       /* perform TLL soft reset, and wait until reset is complete */
9330 +       ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
9331 +                       OMAP_USBTLL_SYSCONFIG_SOFTRESET);
9332 +
9333 +       /* Wait for TLL reset to complete */
9334 +       while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
9335 +                       & OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
9336 +               cpu_relax();
9337 +
9338 +               if (time_after(jiffies, timeout)) {
9339 +                       dev_dbg(omap->dev, "operation timed out\n");
9340 +                       ret = -EINVAL;
9341 +                       goto err_sys_status;
9342 +               }
9343 +       }
9344 +
9345 +       dev_dbg(omap->dev, "TLL RESET DONE\n");
9346 +
9347 +       /* (1<<3) = no idle mode only for initial debugging */
9348 +       ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
9349 +                       OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
9350 +                       OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
9351 +                       OMAP_USBTLL_SYSCONFIG_CACTIVITY);
9352 +
9353 +
9354 +       /* Put UHH in NoIdle/NoStandby mode */
9355 +       reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
9356 +       reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP
9357 +                       | OMAP_UHH_SYSCONFIG_SIDLEMODE
9358 +                       | OMAP_UHH_SYSCONFIG_CACTIVITY
9359 +                       | OMAP_UHH_SYSCONFIG_MIDLEMODE);
9360 +       reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE;
9361 +
9362 +       ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
9363 +
9364 +       reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
9365 +
9366 +       /* setup ULPI bypass and burst configurations */
9367 +       reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
9368 +                       | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
9369 +                       | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
9370 +       reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
9371 +
9372 +       if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9373 +               reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
9374 +       if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9375 +               reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
9376 +       if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
9377 +               reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
9378 +
9379 +       /* Bypass the TLL module for PHY mode operation */
9380 +        if (omap_rev() <= OMAP3430_REV_ES2_1) {
9381 +               dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
9382 +               if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
9383 +                       (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
9384 +                               (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
9385 +                       reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
9386 +               else
9387 +                       reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
9388 +       } else {
9389 +               dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
9390 +               if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
9391 +                       reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
9392 +               else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
9393 +                       reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
9394 +
9395 +               if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
9396 +                       reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
9397 +               else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
9398 +                       reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
9399 +
9400 +               if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
9401 +                       reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
9402 +               else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
9403 +                       reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
9404 +
9405 +       }
9406 +       ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
9407 +       dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
9408 +
9409 +
9410 +       if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
9411 +               (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
9412 +                       (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
9413 +
9414 +               if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
9415 +                       tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
9416 +               if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
9417 +                       tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
9418 +               if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
9419 +                       tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
9420 +
9421 +               /* Enable UTMI mode for required TLL channels */
9422 +               omap_usb_utmi_init(omap, tll_ch_mask);
9423 +       }
9424 +
9425 +       if (omap->phy_reset) {
9426 +               /* Refer ISSUE1:
9427 +                * Hold the PHY in RESET for enough time till
9428 +                * PHY is settled and ready
9429 +                */
9430 +               udelay(10);
9431 +
9432 +               if (gpio_is_valid(omap->reset_gpio_port[0]))
9433 +                       gpio_set_value(omap->reset_gpio_port[0], 1);
9434 +
9435 +               if (gpio_is_valid(omap->reset_gpio_port[1]))
9436 +                       gpio_set_value(omap->reset_gpio_port[1], 1);
9437 +       }
9438 +
9439 +       return 0;
9440 +
9441 +err_sys_status:
9442 +       clk_disable(omap->usbtll_ick);
9443 +       clk_put(omap->usbtll_ick);
9444 +
9445 +err_tll_ick:
9446 +       clk_disable(omap->usbtll_fck);
9447 +       clk_put(omap->usbtll_fck);
9448 +
9449 +err_tll_fck:
9450 +       clk_disable(omap->usbhost1_48m_fck);
9451 +       clk_put(omap->usbhost1_48m_fck);
9452 +
9453 +       if (omap->phy_reset) {
9454 +               if (gpio_is_valid(omap->reset_gpio_port[0]))
9455 +                       gpio_free(omap->reset_gpio_port[0]);
9456 +
9457 +               if (gpio_is_valid(omap->reset_gpio_port[1]))
9458 +                       gpio_free(omap->reset_gpio_port[1]);
9459 +       }
9460 +
9461 +err_host_48m_fck:
9462 +       clk_disable(omap->usbhost2_120m_fck);
9463 +       clk_put(omap->usbhost2_120m_fck);
9464 +
9465 +err_host_120m_fck:
9466 +       clk_disable(omap->usbhost_ick);
9467 +       clk_put(omap->usbhost_ick);
9468 +
9469 +err_host_ick:
9470 +       return ret;
9471 +}
9472 +
9473 +static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
9474 +{
9475 +       unsigned long timeout = jiffies + msecs_to_jiffies(100);
9476 +
9477 +       dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n");
9478 +
9479 +       /* Reset OMAP modules for insmod/rmmod to work */
9480 +       ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG,
9481 +                       OMAP_UHH_SYSCONFIG_SOFTRESET);
9482 +       while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9483 +                               & (1 << 0))) {
9484 +               cpu_relax();
9485 +
9486 +               if (time_after(jiffies, timeout))
9487 +                       dev_dbg(omap->dev, "operation timed out\n");
9488 +       }
9489 +
9490 +       while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9491 +                               & (1 << 1))) {
9492 +               cpu_relax();
9493 +
9494 +               if (time_after(jiffies, timeout))
9495 +                       dev_dbg(omap->dev, "operation timed out\n");
9496 +       }
9497 +
9498 +       while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS)
9499 +                               & (1 << 2))) {
9500 +               cpu_relax();
9501 +
9502 +               if (time_after(jiffies, timeout))
9503 +                       dev_dbg(omap->dev, "operation timed out\n");
9504 +       }
9505 +
9506 +       ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1));
9507 +
9508 +       while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
9509 +                               & (1 << 0))) {
9510 +               cpu_relax();
9511 +
9512 +               if (time_after(jiffies, timeout))
9513 +                       dev_dbg(omap->dev, "operation timed out\n");
9514 +       }
9515 +
9516 +       if (omap->usbtll_fck != NULL) {
9517 +               clk_disable(omap->usbtll_fck);
9518 +               clk_put(omap->usbtll_fck);
9519 +               omap->usbtll_fck = NULL;
9520 +       }
9521 +
9522 +       if (omap->usbhost_ick != NULL) {
9523 +               clk_disable(omap->usbhost_ick);
9524 +               clk_put(omap->usbhost_ick);
9525 +               omap->usbhost_ick = NULL;
9526 +       }
9527 +
9528 +       if (omap->usbhost1_48m_fck != NULL) {
9529 +               clk_disable(omap->usbhost1_48m_fck);
9530 +               clk_put(omap->usbhost1_48m_fck);
9531 +               omap->usbhost1_48m_fck = NULL;
9532 +       }
9533 +
9534 +       if (omap->usbhost2_120m_fck != NULL) {
9535 +               clk_disable(omap->usbhost2_120m_fck);
9536 +               clk_put(omap->usbhost2_120m_fck);
9537 +               omap->usbhost2_120m_fck = NULL;
9538 +       }
9539 +
9540 +       if (omap->usbtll_ick != NULL) {
9541 +               clk_disable(omap->usbtll_ick);
9542 +               clk_put(omap->usbtll_ick);
9543 +               omap->usbtll_ick = NULL;
9544 +       }
9545 +
9546 +       if (omap->phy_reset) {
9547 +               if (gpio_is_valid(omap->reset_gpio_port[0]))
9548 +                       gpio_free(omap->reset_gpio_port[0]);
9549 +
9550 +               if (gpio_is_valid(omap->reset_gpio_port[1]))
9551 +                       gpio_free(omap->reset_gpio_port[1]);
9552 +       }
9553 +
9554 +       dev_dbg(omap->dev, "Clock to USB host has been disabled\n");
9555 +}
9556 +
9557 +/*-------------------------------------------------------------------------*/
9558 +
9559 +static const struct hc_driver ehci_omap_hc_driver;
9560 +
9561 +/* configure so an HC device and id are always provided */
9562 +/* always called with process context; sleeping is OK */
9563 +
9564 +/**
9565 + * ehci_hcd_omap_probe - initialize TI-based HCDs
9566 + *
9567 + * Allocates basic resources for this USB host controller, and
9568 + * then invokes the start() method for the HCD associated with it
9569 + * through the hotplug entry's driver_data.
9570 + */
9571 +static int ehci_hcd_omap_probe(struct platform_device *pdev)
9572 +{
9573 +       struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data;
9574 +       struct ehci_hcd_omap *omap;
9575 +       struct resource *res;
9576 +       struct usb_hcd *hcd;
9577 +
9578 +       int irq = platform_get_irq(pdev, 0);
9579 +       int ret = -ENODEV;
9580 +
9581 +       if (!pdata) {
9582 +               dev_dbg(&pdev->dev, "missing platform_data\n");
9583 +               goto err_pdata;
9584 +       }
9585 +
9586 +       if (usb_disabled())
9587 +               goto err_disabled;
9588 +
9589 +       omap = kzalloc(sizeof(*omap), GFP_KERNEL);
9590 +       if (!omap) {
9591 +               ret = -ENOMEM;
9592 +               goto err_create_hcd;
9593 +       }
9594 +
9595 +       hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev,
9596 +                       dev_name(&pdev->dev));
9597 +       if (!hcd) {
9598 +               dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret);
9599 +               ret = -ENOMEM;
9600 +               goto err_create_hcd;
9601 +       }
9602 +
9603 +       platform_set_drvdata(pdev, omap);
9604 +       omap->dev               = &pdev->dev;
9605 +       omap->phy_reset         = pdata->phy_reset;
9606 +       omap->reset_gpio_port[0]        = pdata->reset_gpio_port[0];
9607 +       omap->reset_gpio_port[1]        = pdata->reset_gpio_port[1];
9608 +       omap->reset_gpio_port[2]        = pdata->reset_gpio_port[2];
9609 +       omap->port_mode[0]              = pdata->port_mode[0];
9610 +       omap->port_mode[1]              = pdata->port_mode[1];
9611 +       omap->port_mode[2]              = pdata->port_mode[2];
9612 +       omap->ehci              = hcd_to_ehci(hcd);
9613 +       omap->ehci->sbrn        = 0x20;
9614 +
9615 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9616 +
9617 +       hcd->rsrc_start = res->start;
9618 +       hcd->rsrc_len = resource_size(res);
9619 +
9620 +       hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
9621 +       if (!hcd->regs) {
9622 +               dev_err(&pdev->dev, "EHCI ioremap failed\n");
9623 +               ret = -ENOMEM;
9624 +               goto err_ioremap;
9625 +       }
9626 +
9627 +       /* we know this is the memory we want, no need to ioremap again */
9628 +       omap->ehci->caps = hcd->regs;
9629 +       omap->ehci_base = hcd->regs;
9630 +
9631 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9632 +       omap->uhh_base = ioremap(res->start, resource_size(res));
9633 +       if (!omap->uhh_base) {
9634 +               dev_err(&pdev->dev, "UHH ioremap failed\n");
9635 +               ret = -ENOMEM;
9636 +               goto err_uhh_ioremap;
9637 +       }
9638 +
9639 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
9640 +       omap->tll_base = ioremap(res->start, resource_size(res));
9641 +       if (!omap->tll_base) {
9642 +               dev_err(&pdev->dev, "TLL ioremap failed\n");
9643 +               ret = -ENOMEM;
9644 +               goto err_tll_ioremap;
9645 +       }
9646 +
9647 +       ret = omap_start_ehc(omap, hcd);
9648 +       if (ret) {
9649 +               dev_dbg(&pdev->dev, "failed to start ehci\n");
9650 +               goto err_start;
9651 +       }
9652 +
9653 +       omap->ehci->regs = hcd->regs
9654 +               + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase));
9655 +
9656 +       /* cache this readonly data; minimize chip reads */
9657 +       omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params);
9658 +
9659 +       /* SET 1 micro-frame Interrupt interval */
9660 +       writel(readl(&omap->ehci->regs->command) | (1 << 16),
9661 +                       &omap->ehci->regs->command);
9662 +
9663 +       ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
9664 +       if (ret) {
9665 +               dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret);
9666 +               goto err_add_hcd;
9667 +       }
9668 +
9669 +       return 0;
9670 +
9671 +err_add_hcd:
9672 +       omap_stop_ehc(omap, hcd);
9673 +
9674 +err_start:
9675 +       iounmap(omap->tll_base);
9676 +
9677 +err_tll_ioremap:
9678 +       iounmap(omap->uhh_base);
9679 +
9680 +err_uhh_ioremap:
9681 +       iounmap(hcd->regs);
9682 +
9683 +err_ioremap:
9684 +       usb_put_hcd(hcd);
9685 +
9686 +err_create_hcd:
9687 +err_disabled:
9688 +err_pdata:
9689 +       return ret;
9690 +}
9691 +
9692 +/* may be called without controller electrically present */
9693 +/* may be called with controller, bus, and devices active */
9694 +
9695 +/**
9696 + * ehci_hcd_omap_remove - shutdown processing for EHCI HCDs
9697 + * @pdev: USB Host Controller being removed
9698 + *
9699 + * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
9700 + * the HCD's stop() method.  It is always called from a thread
9701 + * context, normally "rmmod", "apmd", or something similar.
9702 + */
9703 +static int ehci_hcd_omap_remove(struct platform_device *pdev)
9704 +{
9705 +       struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
9706 +       struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
9707 +
9708 +       usb_remove_hcd(hcd);
9709 +       omap_stop_ehc(omap, hcd);
9710 +       iounmap(hcd->regs);
9711 +       iounmap(omap->tll_base);
9712 +       iounmap(omap->uhh_base);
9713 +       usb_put_hcd(hcd);
9714 +
9715 +       return 0;
9716 +}
9717 +
9718 +static void ehci_hcd_omap_shutdown(struct platform_device *pdev)
9719 +{
9720 +       struct ehci_hcd_omap *omap = platform_get_drvdata(pdev);
9721 +       struct usb_hcd *hcd = ehci_to_hcd(omap->ehci);
9722 +
9723 +       if (hcd->driver->shutdown)
9724 +               hcd->driver->shutdown(hcd);
9725 +}
9726 +
9727 +static struct platform_driver ehci_hcd_omap_driver = {
9728 +       .probe                  = ehci_hcd_omap_probe,
9729 +       .remove                 = ehci_hcd_omap_remove,
9730 +       .shutdown               = ehci_hcd_omap_shutdown,
9731 +       /*.suspend              = ehci_hcd_omap_suspend, */
9732 +       /*.resume               = ehci_hcd_omap_resume, */
9733 +       .driver = {
9734 +               .name           = "ehci-omap",
9735 +       }
9736 +};
9737 +
9738 +/*-------------------------------------------------------------------------*/
9739 +
9740 +static const struct hc_driver ehci_omap_hc_driver = {
9741 +       .description            = hcd_name,
9742 +       .product_desc           = "OMAP-EHCI Host Controller",
9743 +       .hcd_priv_size          = sizeof(struct ehci_hcd),
9744 +
9745 +       /*
9746 +        * generic hardware linkage
9747 +        */
9748 +       .irq                    = ehci_irq,
9749 +       .flags                  = HCD_MEMORY | HCD_USB2,
9750 +
9751 +       /*
9752 +        * basic lifecycle operations
9753 +        */
9754 +       .reset                  = ehci_init,
9755 +       .start                  = ehci_run,
9756 +       .stop                   = ehci_stop,
9757 +       .shutdown               = ehci_shutdown,
9758 +
9759 +       /*
9760 +        * managing i/o requests and associated device resources
9761 +        */
9762 +       .urb_enqueue            = ehci_urb_enqueue,
9763 +       .urb_dequeue            = ehci_urb_dequeue,
9764 +       .endpoint_disable       = ehci_endpoint_disable,
9765 +       .endpoint_reset         = ehci_endpoint_reset,
9766 +
9767 +       /*
9768 +        * scheduling support
9769 +        */
9770 +       .get_frame_number       = ehci_get_frame,
9771 +
9772 +       /*
9773 +        * root hub support
9774 +        */
9775 +       .hub_status_data        = ehci_hub_status_data,
9776 +       .hub_control            = ehci_hub_control,
9777 +       .bus_suspend            = ehci_bus_suspend,
9778 +       .bus_resume             = ehci_bus_resume,
9779 +
9780 +       .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
9781 +};
9782 +
9783 +MODULE_ALIAS("platform:omap-ehci");
9784 +MODULE_AUTHOR("Texas Instruments, Inc.");
9785 +MODULE_AUTHOR("Felipe Balbi <felipe.balbi@nokia.com>");
9786 +
9787 diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
9788 index f16e421..6f957ce 100644
9789 --- a/drivers/video/omap/dispc.c
9790 +++ b/drivers/video/omap/dispc.c
9791 @@ -204,6 +204,7 @@ static u32 inline dispc_read_reg(int idx)
9792  /* Select RFBI or bypass mode */
9793  static void enable_rfbi_mode(int enable)
9794  {
9795 +       void __iomem *rfbi_control;
9796         u32 l;
9797
9798         l = dispc_read_reg(DISPC_CONTROL);
9799 @@ -216,9 +217,15 @@ static void enable_rfbi_mode(int enable)
9800         dispc_write_reg(DISPC_CONTROL, l);
9801
9802         /* Set bypass mode in RFBI module */
9803 -       l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL));
9804 +       rfbi_control = ioremap(RFBI_CONTROL, SZ_1K);
9805 +       if (!rfbi_control) {
9806 +               pr_err("Unable to ioremap rfbi_control\n");
9807 +               return;
9808 +       }
9809 +       l = __raw_readl(rfbi_control);
9810         l |= enable ? 0 : (1 << 1);
9811 -       __raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL));
9812 +       __raw_writel(l, rfbi_control);
9813 +       iounmap(rfbi_control);
9814  }
9815
9816  static void set_lcd_data_lines(int data_lines)
9817 @@ -1367,6 +1374,7 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
9818         int r;
9819         u32 l;
9820         struct lcd_panel *panel = fbdev->panel;
9821 +       void __iomem *ram_fw_base;
9822         int tmo = 10000;
9823         int skip_init = 0;
9824         int i;
9825 @@ -1441,7 +1449,13 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
9826         }
9827
9828         /* L3 firewall setting: enable access to OCM RAM */
9829 -       __raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
9830 +       ram_fw_base = ioremap(0x68005000, SZ_1K);
9831 +       if (!ram_fw_base) {
9832 +               dev_err(dispc.fbdev->dev, "Cannot ioremap to enable OCM RAM\n");
9833 +               goto fail1;
9834 +       }
9835 +       __raw_writel(0x402000b0, ram_fw_base + 0xa0);
9836 +       iounmap(ram_fw_base);
9837
9838         if ((r = alloc_palette_ram()) < 0)
9839                 goto fail2;