1 /* Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
3 * Copyright (C) 2006, Advanced Micro Devices, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 /* The MFPGT timers on the CS5536 provide us with suitable timers to use
12 * as clock event sources - not as good as a HPET or APIC, but certainly
13 * better then the PIT. This isn't a general purpose MFGPT driver, but
14 * a simplified one designed specifically to act as a clock event source.
15 * For full details about the MFGPT, please consult the CS5536 data sheet.
18 /* We are using the 32Khz input clock - its the only one that has the
19 * ranges we find desirable. The following table lists the suitable
20 * divisors and the associated hz, minimum interval
21 * and the maximum interval:
23 Divisor Hz Min Delta (S) Max Delta (S)
35 #include <linux/kernel.h>
36 #include <linux/interrupt.h>
37 #include <linux/module.h>
38 #include <linux/clocksource.h>
39 #include <linux/clockchips.h>
40 #include <asm/geode.h>
44 #define MFGPT_MAX_TIMERS 8
48 static struct mfgpt_timer_t {
51 } mfgpt_timers[MFGPT_MAX_TIMERS];
53 /* Selected from the table above */
55 #define MFGPT_DIVISOR 16
56 #define MFGPT_SCALE 4 /* divisor = 2^(scale) */
57 #define MFGPT_HZ (32000 / MFGPT_DIVISOR)
58 #define MFGPT_PERIODIC (MFGPT_HZ / HZ)
60 #ifdef CONFIG_GEODE_MFGPT_TIMER
61 static int __init mfgpt_timer_setup(void);
63 #define mfgpt_timer_setup() (0)
66 /* Allow for disabling of MFGPTs */
67 static int disable = 0;
68 static int __init mfgpt_disable(char *s)
73 __setup("nomfgpt", mfgpt_disable);
76 * Check whether any MFGPTs are available for the kernel to use. In most
77 * cases, firmware that uses AMD's VSA code will claim all timers during
78 * bootup; we certainly don't want to take them if they're already in use.
79 * In other cases (such as with VSAless OpenFirmware), the system firmware
80 * leaves timers available for us to use.
82 int __init geode_mfgpt_detect(void)
88 printk(KERN_INFO "geode-mfgpt: Skipping MFGPT setup\n");
92 for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
93 val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
94 if (!(val & MFGPT_SETUP_SETUP)) {
95 mfgpt_timers[i].flags = F_AVAIL;
100 /* set up clock event device, if desired */
101 i = mfgpt_timer_setup();
106 int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
108 u32 msr, mask, value, dummy;
109 int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
111 if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
115 * The register maps for these are described in sections 6.17.1.x of
116 * the AMD Geode CS5536 Companion Device Data Book.
119 case MFGPT_EVENT_RESET:
120 /* XXX: According to the docs, we cannot reset timers above
121 * 6; that is, resets for 7 and 8 will be ignored. Is this
124 mask = 1 << (timer + 24);
127 case MFGPT_EVENT_NMI:
129 mask = 1 << (timer + shift);
132 case MFGPT_EVENT_IRQ:
134 mask = 1 << (timer + shift);
141 rdmsr(msr, value, dummy);
148 wrmsr(msr, value, dummy);
151 EXPORT_SYMBOL(geode_mfgpt_toggle_event);
153 int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable)
158 if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
161 if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
164 rdmsr(0x51400022, val, dummy);
166 offset = (timer % 4) * 4;
168 val &= ~((0xF << offset) | (0xF << (offset + 16)));
171 val |= (irq & 0x0F) << (offset);
172 val |= (irq & 0x0F) << (offset + 16);
175 wrmsr(0x51400022, val, dummy);
178 EXPORT_SYMBOL(geode_mfgpt_set_irq);
180 static int mfgpt_get(int timer, struct module *owner)
182 mfgpt_timers[timer].flags &= ~F_AVAIL;
183 mfgpt_timers[timer].owner = owner;
184 printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer);
188 int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner)
192 if (!geode_get_dev_base(GEODE_DEV_MFGPT))
194 if (timer >= MFGPT_MAX_TIMERS)
198 /* Try to find an available timer */
199 for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
200 if (mfgpt_timers[i].flags & F_AVAIL)
201 return mfgpt_get(i, owner);
203 if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
208 /* If they requested a specific timer, try to honor that */
209 if (mfgpt_timers[timer].flags & F_AVAIL)
210 return mfgpt_get(timer, owner);
213 /* No timers available - too bad */
216 EXPORT_SYMBOL(geode_mfgpt_alloc_timer);
218 #ifdef CONFIG_GEODE_MFGPT_TIMER
220 static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
221 static u16 mfgpt_event_clock;
224 static int __init mfgpt_setup(char *str)
226 get_option(&str, &irq);
229 __setup("mfgpt_irq=", mfgpt_setup);
231 static inline void mfgpt_disable_timer(u16 clock)
233 u16 val = geode_mfgpt_read(clock, MFGPT_REG_SETUP);
234 geode_mfgpt_write(clock, MFGPT_REG_SETUP, val & ~MFGPT_SETUP_CNTEN);
237 static int mfgpt_next_event(unsigned long, struct clock_event_device *);
238 static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
240 static struct clock_event_device mfgpt_clockevent = {
241 .name = "mfgpt-timer",
242 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
243 .set_mode = mfgpt_set_mode,
244 .set_next_event = mfgpt_next_event,
246 .cpumask = CPU_MASK_ALL,
250 static inline void mfgpt_start_timer(u16 clock, u16 delta)
252 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
253 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
255 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
256 MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
259 static void mfgpt_set_mode(enum clock_event_mode mode,
260 struct clock_event_device *evt)
262 mfgpt_disable_timer(mfgpt_event_clock);
264 if (mode == CLOCK_EVT_MODE_PERIODIC)
265 mfgpt_start_timer(mfgpt_event_clock, MFGPT_PERIODIC);
267 mfgpt_tick_mode = mode;
270 static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
272 mfgpt_start_timer(mfgpt_event_clock, delta);
276 /* Assume (foolishly?), that this interrupt was due to our tick */
278 static irqreturn_t mfgpt_tick(int irq, void *dev_id)
280 if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
283 /* Turn off the clock */
284 mfgpt_disable_timer(mfgpt_event_clock);
286 /* Clear the counter */
287 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
289 /* Restart the clock in periodic mode */
291 if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
292 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
293 MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
296 mfgpt_clockevent.event_handler(&mfgpt_clockevent);
300 static struct irqaction mfgptirq = {
301 .handler = mfgpt_tick,
302 .flags = IRQF_DISABLED | IRQF_NOBALANCING,
303 .mask = CPU_MASK_NONE,
304 .name = "mfgpt-timer"
307 static int __init mfgpt_timer_setup(void)
312 timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING, THIS_MODULE);
314 printk(KERN_ERR "mfgpt-timer: Could not allocate a MFPGT timer\n");
318 mfgpt_event_clock = timer;
319 /* Set the clock scale and enable the event mode for CMP2 */
320 val = MFGPT_SCALE | (3 << 8);
322 geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
324 /* Set up the IRQ on the MFGPT side */
325 if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) {
326 printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq);
330 /* And register it with the kernel */
331 ret = setup_irq(irq, &mfgptirq);
334 printk(KERN_ERR "mfgpt-timer: Unable to set up the interrupt.\n");
338 /* Set up the clock event */
339 mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, 32);
340 mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mfgpt_clockevent);
341 mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, &mfgpt_clockevent);
343 printk("mfgpt-timer: registering the MFGT timer as a clock event.\n");
344 clockevents_register_device(&mfgpt_clockevent);
349 geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq);
350 printk(KERN_ERR "mfgpt-timer: Unable to set up the MFGPT clock source\n");